CN111668091A - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
CN111668091A
CN111668091A CN201910172300.0A CN201910172300A CN111668091A CN 111668091 A CN111668091 A CN 111668091A CN 201910172300 A CN201910172300 A CN 201910172300A CN 111668091 A CN111668091 A CN 111668091A
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layer
groove
forming
mask
initial
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CN111668091B (en
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金吉松
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask

Abstract

A semiconductor device and a method of forming the same, the method comprising: providing a substrate, wherein the substrate comprises a plurality of discrete first areas and a plurality of discrete second areas, the first areas and the second areas are arranged at intervals along a first direction, and the adjacent first areas and the adjacent second areas are adjacent; forming a first mask layer on the first area and the second area of the substrate; forming a plurality of mutually-separated first grooves in the first mask layer on the first area; after the first groove is formed, a plurality of mutually-separated division grooves are formed in the first mask layer on the second area, the division grooves divide the first mask layer on the second area in a second direction, and the second direction is perpendicular to the first direction; forming an initial mask side wall layer on the first mask layer, the bottom and the side wall surface of the first groove and the bottom and the side wall surface of the dividing groove, and forming a middle dividing groove in the dividing groove; and forming a filling layer in the middle dividing groove. The method improves the performance of the semiconductor device.

Description

Semiconductor device and method of forming the same
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the continuous progress of semiconductor technology, semiconductor devices are being developed toward higher element density and higher integration. Line width is one of the main parameters of semiconductor devices, and reducing line width can improve integration and reduce the size of semiconductor devices.
When the line width shrinks below the limit of the photolithography process, a Double Patterning Technique (DPT) is used to reduce the line width. The double patterning technique is to divide a set of high-density circuit patterns into two or more sets of circuit patterns with lower density, and then print the circuit patterns onto a target wafer. There are many different methods for realizing double pattern exposure, but the basic steps are printing half of the pattern, developing and etching; then spin coating a layer of photoresist again, printing the other half of the pattern, and finally finishing the whole photoetching process by utilizing a hard mask or selective etching.
However, when fabricating small-linewidth metal layers, the ability of the photolithography process results in metal layer edge shrink (Line-end short). The smaller the line width, the more severe the metal layer edge shrinkage. The conventional method is to perform Optical Proximity Correction (OPC) on the photomask to correct the metal layer shrinkage. When the metal layer shrinks too severely, the correction amount of the required optical proximity effect correction is too large, so that the patterns of two adjacent metal layers on the photomask are overlapped, and the optical proximity effect correction method fails. In this case, a metal layer cutting process (Line-end) has to be added. The cutting process is to cut off two adjacent overlapped metal layers by utilizing the metal layer cutting photoetching and metal layer cutting etching processes added by the cutting mask after lines of the overlapped metal layers are formed.
However, the performance of the semiconductor device formed by the existing process is still poor.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the performance of the semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein the substrate comprises a plurality of discrete first areas and a plurality of discrete second areas, the first areas and the second areas are arranged at intervals along a first direction, and the adjacent first areas and the adjacent second areas are adjacent; forming a first mask layer on the first area and the second area of the substrate; forming a plurality of mutually-separated first grooves in the first mask layer on the first area; after the first groove is formed, a plurality of mutually-separated division grooves are formed in the first mask layer on the second area, the division grooves divide the first mask layer on the second area in a second direction, and the second direction is perpendicular to the first direction; forming an initial mask side wall layer on the first mask layer, the bottom and the side wall surface of the first groove and the bottom and the side wall surface of the dividing groove, and forming a middle dividing groove in the dividing groove; and forming a filling layer in the middle dividing groove.
Optionally, the forming method of the filling layer includes: forming an initial filling layer in the first groove, the middle dividing groove and the initial mask side wall layer; and etching the initial filling layer back by adopting an isotropic etching process until the surface of the initial mask side wall layer at the bottom of the first groove is exposed, and forming the filling layer in the middle partition groove.
Optionally, the isotropic etching process includes: isotropic dry etching or isotropic wet etching.
Optionally, the process for forming the initial filling layer includes: one or more of a spin-on process, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Optionally, the material of the filling layer includes: silicon oxide, silicon nitride, titanium oxide, titanium nitride, aluminum nitride, or aluminum oxide.
Optionally, the material of the initial mask sidewall layer includes: silicon oxide, silicon nitride, titanium oxide, titanium nitride, aluminum nitride, or aluminum oxide.
Optionally, the material of the first mask layer includes: SiO2, SiN, or amorphous silicon.
Optionally, in the second direction, the thickness of the initial mask sidewall layer is less than half of the minimum width of the dividing groove.
Optionally, the method for forming a plurality of separate dividing grooves arranged along the second direction in the first mask layer in the second region includes: forming a first blocking layer on the first mask layer and in the first groove, wherein the first blocking layer exposes a part of the surface of the first mask layer in the second area; and etching the first mask layer by taking the first barrier layer as a mask, and forming dividing grooves in the first mask layer, wherein the dividing grooves transversely cross the second area along the first direction, and the dividing grooves are separately arranged on the second area along the second direction.
Optionally, the plurality of dividing grooves include at least one first dividing groove and at least one second dividing groove, the second dividing groove is in conduction with the first groove, and the first dividing groove and the first groove are isolated from each other; in the second direction, the width of the first dividing groove is smaller than that of the second dividing groove; the initial mask side wall layer covers the side wall and the bottom surface of the first dividing groove and the side wall and the bottom surface of the second dividing groove, so that the first dividing groove is formed into a first middle dividing groove, and the second dividing groove is formed into a second middle dividing groove; and forming a first filling layer in the first middle dividing groove and forming a second filling layer in the second middle dividing groove.
Optionally, the method for forming the first barrier layer includes: forming an initial first barrier layer on the first mask layer and in the first groove; forming a first patterned photoresist layer on the initial first barrier layer, wherein the first photoresist layer exposes a part of the surface of the initial first barrier layer in the second region; etching the initial first barrier layer by using the first photoresist layer as a mask until the first mask layer is exposed, so that the initial first barrier layer forms a first barrier layer; and removing the first photoresist layer after etching the initial first barrier layer by taking the first photoresist layer as a mask.
Optionally, the method further includes: before forming a first mask layer, forming an initial hard mask layer on the surface of the substrate, wherein the initial hard mask layer is positioned between the substrate and the first mask layer; the first groove exposes the surface of the initial hard mask layer of the first area.
Optionally, the material of the initial hard mask layer includes: SiO2, SiN, or amorphous silicon.
Optionally, the initial mask sidewall layer and the filling layer in the dividing groove form a dividing structure; after the filling layer is formed, the method further comprises the following steps: etching back the initial mask side wall layer, and forming a mask side wall layer on the side wall of the first groove; after forming the mask side wall layer, forming a first dividing layer in the first groove, wherein the first dividing layer divides the first groove into first middle grooves along a second direction, the first middle grooves are positioned at two sides of the dividing layer, and part of the initial hard mask layer of the first area is exposed out of the first middle grooves; after the first middle groove is formed, etching the first mask layer of the second area, and forming a discrete second groove in the first mask layer of the second area, wherein the second groove is respectively positioned at two sides of the segmentation structure in the second direction, and the side wall of the second groove is exposed out of the mask side wall layer; with first mask layer, mask lateral wall layer, first segmentation layer and segmentation structure are the mask, and the initial hard mask layer that first intermediate tank bottom of sculpture exposed and the initial hard mask layer that the second groove exposes form the hard mask layer, third groove and fourth groove have in the hard mask layer, the third groove is located the first district, just the third groove is located first segmentation layer both sides respectively, the fourth groove is located the second district, just the fourth groove is located the segmentation structure both sides respectively.
Optionally, the method further includes: after a hard mask layer is formed, etching the substrates at the bottoms of the third groove and the fourth groove by taking the hard mask layer as a mask, forming a first target groove in the substrate at the bottom of the third groove, and forming a second target groove in the substrate at the bottom of the fourth groove; after a first target groove and a second target groove are formed, removing the hard mask layer; after the hard mask layer is removed, a first interconnection layer is formed in the first target groove; and forming a second interconnection layer in the second target groove, wherein the first interconnection layer and the second interconnection layer are separated.
The invention also provides a semiconductor device formed by adopting any one of the methods.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor device, provided by the technical scheme of the invention, the initial mask side wall layer and the filling layer are formed in the dividing groove to fill the dividing groove, so that the initial mask side wall layer and the filling layer form a dividing structure, and the dividing structure provides a mask for a cutting layer for forming the second region subsequently. The dividing structure is formed by adopting a layered structure, so that the thickness of the initial mask side wall layer can be thinner, the thickness of the subsequent mask side wall layer formed in the first groove is thinner, the base area of the bottom of the first groove exposed by the mask side wall layer is larger, the area of the interconnection layer formed in the subsequent first area is larger, the resistance of the interconnection layer of the formed first area is smaller, and the performance of the semiconductor device is improved. Meanwhile, the thickness of the initial mask side wall layer is controlled by adopting a layered structure, so that the method can adapt to the dividing grooves with different sizes, and the adjustability of technological parameters in the manufacturing process is increased, thereby improving the yield during production. In conclusion, the performance of the semiconductor device is improved.
Further, even if the sizes of the respective dividing grooves in the second direction are different from each other, the filling layer may fill the respective dividing grooves as long as the thickness of the initial mask sidewall layer is less than one-half of the width of the minimum dividing groove.
Drawings
Fig. 1 to 5 are schematic structural views during a process of a method of forming a semiconductor device;
fig. 6 to 25 are schematic structural views in the process of performing a method for forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
As described in the background, the existing methods for forming semiconductor devices have poor performance.
Fig. 1 to 5 are schematic structural views in the process of a method for forming a semiconductor device.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 including a plurality of discrete first regions a01 and a plurality of discrete second regions a02, the first regions a01 and the second regions a02 being spaced apart along a first direction X, adjacent first regions a01 and second regions a02 being contiguous.
Referring to fig. 2, a hard mask layer 120 is formed on the first and second regions a01 and a02 of the substrate 100; a discrete first trench 121 is formed in the hard mask layer 120 in the first region a 01.
Referring to fig. 3, the dividing groove 122 is formed in the hard mask layer 120 on the partial second region a02, the extending direction of the dividing groove 122 is parallel to the first direction X, the dividing groove 122 can further extend onto the first region a01, the partial dividing groove 122 is through the first groove 121, and the partial dividing groove 122 is separated from the first groove 121.
Referring to fig. 4, forming a mask sidewall spacer 130 on the sidewall of the first trench 121; in the process of forming the mask sidewall spacers 130, the division mask layer 131 is formed in the division grooves 122, and the division mask layer 131 fills the division grooves 122 on the second region a 02.
Referring to fig. 5, after forming the mask sidewall spacers 130 and the division mask layer 131, a discrete second trench 150 is formed in the hard mask layer 120 in the second region a02, the sidewall of the second trench 150 exposes the mask sidewall spacers 130, and the second trench 150 is cut by the division trench 122 in the second region a02 along a second direction, which is perpendicular to the first direction X.
Since the extending direction of the first grooves 121 and the extending direction of the dividing grooves 122 are different, in order to make the size of the first grooves 121 of the first area a01 in the first direction X and the size of the dividing grooves 122 in the second direction smaller, it is necessary to form the first grooves 121 and the dividing grooves 122, respectively, in different steps.
Since the dividing grooves 122 are formed after the first grooves 121 are formed, the mask material layer used in the process of forming the dividing grooves 122 needs to be filled in the first grooves 121, resulting in that the thickness of the mask material layer located between the first grooves 121 is smaller than the mask material layer located at other positions, and therefore, when openings are formed in the mask material layer, the size of the openings in the mask material layer located between the first grooves 121 is larger, and the openings in the mask material layer located at other positions are smaller. The size of the dividing groove 122 located to penetrate the first groove 121 is larger than the size of the dividing groove 122 separate from the first groove 121. The thickness of the division mask layer 131 needs to be greater than half of the maximum division groove size to ensure that all the division grooves 122 are filled with the division mask layer 131. The thicknesses of the divided doped layer 131 and the mask sidewall spacer 130 are the same, and the thickness of the mask sidewall spacer 130 is thicker, so that the area of the first region a01 exposed by the first trench 121 is smaller, the volume of the interconnection layer formed in the subsequent first region a01 is smaller, and the resistance of the interconnection layer in the first region a01 is larger, thereby causing poor performance of the semiconductor device.
On the basis, the invention provides a method for forming a semiconductor device, wherein an initial mask side wall layer is formed in a dividing groove of a second region, so that the dividing groove is formed into a middle dividing groove, a filling layer is formed in the middle dividing groove, and the middle dividing groove is filled with the filling layer. The performance of the formed semiconductor device is improved. Meanwhile, the structure can be suitable for the dividing grooves with various sizes, the range of technological parameters is large, and the yield in production is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 6 to 25 are schematic structural views in the process of performing a method for forming a semiconductor device according to an embodiment of the present invention.
Referring to fig. 6, a substrate 200 is provided, the substrate 200 including a plurality of discrete first regions a1 and a plurality of discrete second regions a2, the first regions a1 and the second regions a2 being spaced apart along the first direction X, adjacent first regions a1 and second regions a2 being contiguous.
The plurality of first regions a1 are arranged along the first direction X, and the plurality of second regions a2 are arranged along the first direction X.
The first and second zones a1 and a2 arranged at intervals in the first direction X mean that: there is only one second zone between adjacent first zones a1 and only one first zone between adjacent second zones.
In the present embodiment, five first zones a1 and six second zones a2 are exemplified. In other embodiments, other values may be selected for the number of first and second zones.
In other embodiments, the number of first zones and second zones is equal.
The material of the substrate 200 includes silicon oxide or a low-K dielectric layer (K is less than or equal to 3.9).
Referring to fig. 7, 8 and 9, fig. 7 is a schematic view based on fig. 6, fig. 8 is a cross-sectional view taken along a cutting line M1-N1 of fig. 7, and fig. 9 is a cross-sectional view taken along a cutting line M-N of fig. 7, wherein a first mask layer 230 is formed on the first region a1 and the second region a2 of the substrate 200.
In this embodiment, the method further includes: before forming the first mask layer 230, an initial hard mask layer 220 is formed on the surface of the substrate 200, wherein the initial hard mask layer 220 is located between the substrate 200 and the first mask layer 230.
The first groove exposes the surface of the initial hard mask layer of the first area.
The initial hard mask layer 220 covers the entire first region a1 and the entire second region a 2.
In this embodiment, the method further includes: forming a bottom hard mask layer 210 on the substrate 200 before forming the initial hard mask layer 220; after forming the bottom hard mask layer 210, forming an initial hard mask layer 220 on the bottom hard mask layer 210; a first mask layer 230 is formed on the initial hard mask layer 220.
In this embodiment, the bottom hard mask layer 210 is in contact with the substrate 200, the initial hard mask layer 220 is in contact with the bottom hard mask layer 210, and the first mask layer 230 is in contact with the initial hard mask layer 220.
The material of the bottom hard mask layer 210 comprises titanium nitride.
The material of the initial hard mask layer 220 comprises SiO2SiN or amorphous silicon.
The material of the first mask layer 230 includes SiO2SiN or amorphous silicon.
In this embodiment, the initial hard mask layer 220 is made of SiO2The material of the first mask layer 230 is amorphous silicon.
The bottom hard mask layer 210 functions include: the bottom hard mask layer 210 serves as an etch stop layer; the bottom hard mask layer 210 serves as a stop layer for subsequent planarization of the interconnect film; the bottom mask layer 210 is made of a hard mask material, so that when the initial hard mask layer 220 is etched subsequently to form a third groove and a fourth groove, the etching loss of the bottom mask layer 210 is small, and the stability of pattern transfer is high in the process of transferring the pattern in the bottom mask layer 210 to the substrate 200.
In this embodiment, the bottom hard mask layer 210, the initial hard mask layer 220, and the first mask layer 230 are different from each other in material.
Next, a separate first groove 231 is formed in the first mask layer 230 of the first region a 1.
The first groove 231 extends in a second direction Y perpendicular to the first direction X.
The width of the first groove 231 in the first direction X is 40 nm to 300 nm.
In the first direction X, a distance between adjacent first grooves 231 is 40 nm to 300 nm.
Referring to fig. 10, 11 and 12, fig. 10 is a schematic view based on fig. 7, fig. 11 is a cross-sectional view taken along a cutting line M2-N2 in fig. 10, and fig. 12 is a cross-sectional view taken along a cutting line M-N in fig. 10, after the first trenches 231 are formed, discrete dividing trenches are formed in the first mask layer 230 of the second region a2, the dividing trenches divide the first mask layer 230 of the second region a2 in the second direction Y, and a part of the dividing trenches are in electrical communication with the first trenches 231.
The method of forming the separate division grooves arranged in the second direction Y in the first mask layer 230 of the second region a2 includes: forming a first barrier layer (not shown) on the first mask layer 230 and in the first trench 231, the first barrier layer exposing a portion of the surface of the first mask layer 230 in the second region a 2; and etching the first mask layer 230 by using the first barrier layer as a mask, and forming dividing grooves in the first mask layer 230, wherein the dividing grooves cross the second region a2 along the first direction X, and the dividing grooves are separately arranged on the second region a2 along the second direction Y.
In this embodiment, the plurality of dividing grooves include at least one first dividing groove 241 and at least one second dividing groove 242, the second dividing groove 242 is in conduction with the first groove 231, the first dividing groove 241 is not in conduction with the first groove 231, and the width of the first dividing groove 241 is smaller than the width of the second dividing groove 242 in the second direction Y.
Specifically, the method for forming the dividing groove includes: forming a first barrier layer (not shown) on the first mask layer 230 and in the first trench 231, the first barrier layer exposing a portion of the surface of the first mask layer 230 in the second region a 2; the first mask layer 230 is etched by using the first barrier layer as a mask, a first dividing groove 241 and a second dividing groove 242 are formed in the first mask layer 230, the first dividing groove 241 transversely crosses the second region a2 along the first direction, the first dividing groove 241 is not conducted with the first groove 231, the second dividing groove 242 transversely crosses the second region a2 along the first direction X, and the first dividing groove 241 is conducted with the adjacent first groove 231 along the first direction X.
The forming method of the first barrier layer comprises the following steps: forming an initial first barrier layer (not shown) on the first mask layer 230 and within the first trench 231; forming a patterned first photoresist layer (not shown) on the initial first barrier layer, the first photoresist layer exposing portions of the initial first barrier layer surface of the second region a 2; etching the initial first barrier layer by using the first photoresist layer as a mask until the first mask layer 230 is exposed, so that the initial first barrier layer forms a first barrier layer; and removing the first photoresist layer after etching the initial first barrier layer by taking the first photoresist layer as a mask.
In this embodiment, after forming the first dividing groove 241 and the second dividing groove 242, the first barrier layer is removed.
The process for removing the first barrier layer comprises the following steps: a dry etching process or a wet etching process.
Referring to fig. 13, 14 and 15, fig. 13 is a schematic view based on fig. 10, fig. 14 is a sectional view taken along a cutting line M2-N2 of fig. 13, and fig. 15 is a sectional view taken along a cutting line M-N of fig. 13, and an initial mask sidewall layer 250 is formed on the first mask layer 230, the bottom and sidewalls of the first trench 231, and the bottom and sidewalls of the division trench such that the division trench is formed as an intermediate division trench.
The material of the initial mask sidewall layer 250 includes: silicon oxide, silicon nitride, titanium oxide, titanium nitride, aluminum nitride, or aluminum oxide.
The process of forming the initial mask sidewall layer 250 includes: one or more of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the dividing groove includes: a first dividing groove 241 and a second dividing groove 242; the initial mask sidewall layer 250 covers the sidewalls and bottom surfaces of the first dividing grooves 241 and the sidewalls and bottom surfaces of the second dividing grooves 242 such that the first dividing grooves 241 are formed as first intermediate dividing grooves 251 and the second dividing grooves 242 are formed as second intermediate dividing grooves 252.
In the second direction Y, the thickness of the initial mask sidewall layer 250 is less than one-half of the width of the first dividing groove 241.
The thickness of the initial mask sidewall layer 250 is less than one half of the width of the first dividing groove 241, so that after the initial mask sidewall layer 250 is formed, neither the first dividing groove 241 nor the second dividing groove 242 is filled, and thus the first intermediate dividing groove 251 and the second intermediate dividing groove 252 are formed.
In this embodiment, the thickness of the initial mask sidewall layer 250 is 5nm to 20 nm.
In this embodiment, the first intermediate dividing groove 251 has a dimension in the second direction of 1nm to 10 nm.
The second intermediate dividing groove 252 has a dimension in the second direction of 1nm to 10 nm.
Referring to fig. 16 and 17, fig. 16 is a schematic view based on fig. 14, and fig. 17 is a schematic view based on fig. 15, wherein an initial filling layer 260 is formed in the first trench 231, the middle dividing trench and the initial mask sidewall layer 250.
In this embodiment, an initial filling layer 260 is formed in the first trench 231, the first intermediate dividing trench 251, the second intermediate dividing trench 252 and on the initial mask sidewall layer 250.
The initial filling layer 260 fills the first intermediate dividing groove 251 and the second intermediate dividing groove 252.
The material of the initial fill layer 260 includes: silicon oxide, silicon nitride, titanium oxide, titanium nitride, aluminum nitride, or aluminum oxide.
The initial fill layer 260 provides a material layer for subsequently formed fill layers.
The process of forming the initial fill layer 260 includes: one or more of a spin-on process, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the initial filling layer 260 fills the first groove 231.
The material of the initial fill layer 260 is silicon dioxide. The process of forming the initial fill layer 260 is a spin-on process.
In one embodiment, the material of the initial fill layer is a silicon-containing bottom anti-reflective coating.
The initial filling layer formed by the spin coating process has a relatively thick thickness, so that the initial filling layer 260 fills the first trench 231.
In an embodiment, referring to fig. 18 and 19, fig. 18 is a schematic view on the basis of fig. 14, and fig. 19 is a schematic view on the basis of fig. 15; an initial fill layer 270 is formed within the intermediate dividing grooves and on the initial mask sidewall layer 250.
The initial filling layer 270 fills the first intermediate dividing groove 251 and the second intermediate dividing groove 252.
The initial fill layer 270 does not fill the first trench 231.
The initial fill layer 270 is formed using a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The film layer formed by the chemical vapor deposition process, the physical vapor deposition process or the atomic layer deposition process is thin, the size of the first groove 231 is large, and the sizes of the first middle dividing groove 251 and the second middle dividing groove 252 are small, so that after the first middle dividing groove 251 and the second middle dividing groove 252 are filled, the first groove 231 is not filled.
Referring to fig. 20, 21 and 22, fig. 20 is a schematic view based on fig. 13, fig. 21 is a cross-sectional view taken along a cutting line M2-N2 in fig. 20, fig. 22 is a cross-sectional view taken along a cutting line M-N in fig. 20, and the initial filling layer 260 is etched back until the surface of the initial mask sidewall layer 250 at the bottom of the first trench 231 is exposed, so as to form a filling layer in the middle dividing trench.
In this embodiment, the initial filling layer 260 is etched back until the surface of the initial mask sidewall layer 250 at the bottom of the first trench 231 is exposed, a first filling layer 261 is formed in the first intermediate dividing trench 251, and a second filling layer 262 is formed in the second intermediate dividing trench 252.
Since the first and second intermediate dividing grooves 251 and 252 have small sizes, when the initial filling layer 260 is etched back, the initial filling layer 260 in the first and second intermediate dividing grooves 251 and 252 is not removed, and a first filling layer 261 and a second filling layer 262 are formed in the first and second intermediate dividing grooves 251 and 252.
The process of etching back the initial filling layer 260 includes: isotropic dry etching or isotropic wet etching.
The process of etching back the initial filling layer 260 is an isotropic etching process, which can completely remove the initial filling layer 260 on the surface of the initial mask sidewall layer 250 in the first trench 231 without leaving any residue on the sidewalls of the first trench.
The initial mask sidewall layer 250 and the filling layer in the dividing groove form a dividing structure. The dividing structure is a layered structure, the thickness of the initial mask sidewall layer 250 is controlled, the mask sidewall layer can adapt to dividing grooves with different sizes, the adjustability of process parameters in the manufacturing process is increased, and therefore the yield in production is improved.
Referring to fig. 23, 24 and 25, fig. 23 is a schematic view based on fig. 20, fig. 24 is a cross-sectional view taken along the cutting line M2-N2 in fig. 23, and fig. 25 is a cross-sectional view taken along the cutting line M-N in fig. 23, after the filling layer is formed, the initial mask spacer layer 250 is etched back, and a mask spacer layer 254 is formed on the sidewalls of the first trench 231.
In this embodiment, after forming the mask sidewall layer 254, the method further includes: forming a first division layer in the first trench 231, the first division layer contacting the mask sidewall layer and dividing the first trench 231 into first middle trenches along the second direction Y, the first middle trenches being located at both sides of the first division layer; after the first middle groove is formed, etching the first mask layer of the second area A2, and forming a second separated groove in the first mask layer of the second area A2, wherein the second grooves are respectively positioned at two sides of the partition structure in the second direction, and the side wall of the second groove is exposed out of the mask side wall; with first mask layer 230, mask lateral wall layer 254, first segmentation layer and segmentation structure are the mask, and the initial hard mask layer that first middle tank bottom exposure and the initial hard mask layer 210 that the second groove exposes form the hard mask layer, third groove and fourth groove have in the hard mask layer, the third groove is located the first district, just the third groove is located first segmentation layer both sides respectively, the fourth groove is located the second district, just the fourth groove is located the segmentation structure both sides respectively.
In this embodiment, after forming the hard mask layer, the method further includes: etching the substrate 200 at the bottom of the third groove and the fourth groove by taking the hard mask layer as a mask, forming a first target groove in the substrate 200 at the bottom of the third groove, and forming a second target groove in the substrate 200 at the bottom of the fourth groove; after a first target groove and a second target groove are formed, removing the hard mask layer; after the hard mask layer is removed, a first interconnection layer is formed in the first target groove; and forming a second interconnection layer in the second target groove, wherein the first interconnection layer and the second interconnection layer are separated.
The dividing structure provides a mask for a cutting layer which is subsequently formed into the second region a 2. The division structure is formed by using a layered structure, so that the thickness of the initial mask sidewall layer 250 can be relatively thin, the thickness of the mask sidewall layer 254 formed in the first groove a1 subsequently is relatively thin, the area of the substrate 200 at the bottom of the first groove a1 exposed by the mask sidewall layer 254 is relatively large, the area of the first interconnection layer formed in the first region a1 subsequently is relatively large, and the resistance of the first interconnection layer formed in the first region a1 is relatively small, thereby improving the performance of the semiconductor device.
Correspondingly, the embodiment also provides a semiconductor device formed by adopting the method.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (16)

1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a plurality of discrete first areas and a plurality of discrete second areas, the first areas and the second areas are arranged at intervals along a first direction, and the adjacent first areas and the adjacent second areas are adjacent;
forming a first mask layer on the first area and the second area of the substrate;
forming a plurality of mutually-separated first grooves in the first mask layer on the first area;
after the first groove is formed, a plurality of mutually-separated division grooves are formed in the first mask layer on the second area, the division grooves divide the first mask layer on the second area in a second direction, and the second direction is perpendicular to the first direction;
forming an initial mask side wall layer on the first mask layer, the bottom and the side wall surface of the first groove and the bottom and the side wall surface of the dividing groove, and forming a middle dividing groove in the dividing groove;
and forming a filling layer in the middle dividing groove.
2. The method for forming a semiconductor device according to claim 1, wherein the method for forming the filling layer comprises: forming an initial filling layer in the first groove, the middle dividing groove and the initial mask side wall layer; and etching the initial filling layer back by adopting an isotropic etching process until the surface of the initial mask side wall layer in the first groove is exposed, and forming the filling layer in the middle partition groove.
3. The method of claim 2, wherein the isotropic etching process comprises: isotropic dry etching or isotropic wet etching.
4. The method of claim 2, wherein the process of forming the initial fill layer comprises: one or more of a spin-on process, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
5. The method according to claim 1, wherein a material of the filling layer comprises: silicon oxide, silicon nitride, titanium oxide, titanium nitride, aluminum nitride, or aluminum oxide.
6. The method of claim 1, wherein the material of the initial mask sidewall layer comprises: silicon oxide, silicon nitride, titanium oxide, titanium nitride, aluminum nitride, or aluminum oxide.
7. The method for forming a semiconductor device according to claim 1, wherein the material of the first mask layer includes: SiO22SiN or amorphous silicon.
8. The method as claimed in claim 1, wherein the thickness of the initial mask sidewall layer is less than half of the minimum width of the dividing groove in the second direction.
9. The method for forming a semiconductor device according to claim 1, wherein the step of forming the plurality of separate dividing grooves arranged in the second direction in the first mask layer in the second region comprises: forming a first blocking layer on the first mask layer and in the first groove, wherein the first blocking layer exposes a part of the surface of the first mask layer in the second area; and etching the first mask layer by taking the first barrier layer as a mask, and forming dividing grooves in the first mask layer, wherein the dividing grooves transversely cross the second area along the first direction, and the dividing grooves are separately arranged on the second area along the second direction.
10. The method of claim 1, wherein the plurality of dividing grooves include at least one first dividing groove and at least one second dividing groove, the second dividing groove is in conduction with the first groove, and the first dividing groove and the first groove are isolated from each other; in the second direction, the width of the first dividing groove is smaller than that of the second dividing groove; the initial mask side wall layer covers the side wall and the bottom surface of the first dividing groove and the side wall and the bottom surface of the second dividing groove, so that the first dividing groove is formed into a first middle dividing groove, and the second dividing groove is formed into a second middle dividing groove; and forming a first filling layer in the first middle dividing groove and forming a second filling layer in the second middle dividing groove.
11. The method for forming a semiconductor device according to claim 9, wherein the method for forming the first barrier layer comprises: forming an initial first barrier layer on the first mask layer and in the first groove; forming a first patterned photoresist layer on the initial first barrier layer, wherein the first photoresist layer exposes a part of the surface of the initial first barrier layer in the second region; etching the initial first barrier layer by using the first photoresist layer as a mask until the first mask layer is exposed, so that the initial first barrier layer forms a first barrier layer; and removing the first photoresist layer after etching the initial first barrier layer by taking the first photoresist layer as a mask.
12. The method for forming a semiconductor device according to claim 1, further comprising: before forming a first mask layer, forming an initial hard mask layer on the surface of the substrate, wherein the initial hard mask layer is positioned between the substrate and the first mask layer; the first groove exposes the surface of the initial hard mask layer of the first area.
13. The method of claim 12, wherein the material of the initial hard mask layer comprises: SiO22SiN or amorphous silicon.
14. The method of forming a semiconductor device according to claim 12, wherein the initial mask sidewall layer and the filling layer in the dividing groove constitute a dividing structure; after the filling layer is formed, the method further comprises the following steps: etching back the initial mask side wall layer, and forming a mask side wall layer on the side wall of the first groove; after forming the mask side wall layer, forming a first dividing layer in the first groove, wherein the first dividing layer divides the first groove into first middle grooves along a second direction, the first middle grooves are positioned at two sides of the dividing layer, and part of the initial hard mask layer of the first area is exposed out of the first middle grooves; after the first middle groove is formed, etching the first mask layer of the second area, and forming a discrete second groove in the first mask layer of the second area, wherein the second groove is respectively positioned at two sides of the segmentation structure in the second direction, and the side wall of the second groove is exposed out of the mask side wall layer; with first mask layer, mask lateral wall layer, first segmentation layer and segmentation structure are the mask, and the initial hard mask layer that first intermediate tank bottom of sculpture exposed and the initial hard mask layer that the second groove exposes form the hard mask layer, third groove and fourth groove have in the hard mask layer, the third groove is located the first district, just the third groove is located first segmentation layer both sides respectively, the fourth groove is located the second district, just the fourth groove is located the segmentation structure both sides respectively.
15. The method for forming a semiconductor device according to claim 14, further comprising: after a hard mask layer is formed, etching the substrates at the bottoms of the third groove and the fourth groove by taking the hard mask layer as a mask, forming a first target groove in the substrate at the bottom of the third groove, and forming a second target groove in the substrate at the bottom of the fourth groove; after a first target groove and a second target groove are formed, removing the hard mask layer; after the hard mask layer is removed, a first interconnection layer is formed in the first target groove; and forming a second interconnection layer in the second target groove, wherein the first interconnection layer and the second interconnection layer are separated.
16. A semiconductor device formed by the method of any of claims 1 to 15.
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CN107039334A (en) * 2016-02-03 2017-08-11 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN107039335A (en) * 2016-02-03 2017-08-11 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN109427578A (en) * 2017-08-24 2019-03-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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CN101183645A (en) * 2006-11-16 2008-05-21 恩益禧电子股份有限公司 Method of manufacturing semiconductor device
CN102468215A (en) * 2010-11-19 2012-05-23 中国科学院微电子研究所 Trench isolation structure and forming method thereof
CN107039334A (en) * 2016-02-03 2017-08-11 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
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