WO2023024869A1

WO2023024869A1 - Semiconductor surface planarization method, manufactured semiconductor and use

Info

Publication number: WO2023024869A1
Application number: PCT/CN2022/110438
Authority: WO
Inventors: 黄清波; 周雪梅; 翁杰; 潘代强
Original assignee: 上海芯物科技有限公司
Priority date: 2021-08-23
Filing date: 2022-08-05
Publication date: 2023-03-02
Also published as: CN113611663A

Abstract

Disclosed is a semiconductor surface planarization method, the method comprising: in the nth stage manufacturing process of a semiconductor structure having at least two interconnected layers, laying down an initial nth-stage dielectric layer, the nth-stage initial dielectric layer first undergoing planarization in a thickness direction, and obtaining an nth-stage dielectric layer, and then performing a subsequent process; the thickness of the nth-stage initial dielectric layer is greater than the thickness of the nth-stage dielectric layer, and n ≥ 2. In a semiconductor structure having at least two interconnected layers, the method overcomes the impact on additional later-stage processes of a butterfly recess generated in an early-stage manufacturing process, allowing for effectively controlling the size of the butterfly shape.

Description

A method for flattening the surface of a semiconductor, the prepared semiconductor and its use

technical field

The embodiments of the present application relate to the technical field of semiconductor manufacturing, for example, a method for flattening the surface of a semiconductor, and the manufactured semiconductor and its application.

Background technique

In the semiconductor manufacturing process, the chemical mechanical polishing of Cu is mainly used for the planarization of the copper surface of Damascus metal in the back section.

Metal copper chemical mechanical polishing is mainly carried out through three grinding discs. The first grinding disc removes copper under high pressure and removes most of the copper above the groove; the second grinding disc removes the remaining metal copper above the groove with relatively small pressure ; The third grinding disc thins the groove and the oxide layer beside it to the thickness required by the process.

The existing technology usually continues grinding when the second grinding disc detects the grinding end point to ensure that the remaining metallic copper above the groove is completely removed. After the grinding end point is detected, there is generally a period of over-polishing process to ensure that the metallic copper above the groove is removed. clean. In the process of over-throwing, a butterfly structure with copper depressions will be formed, and the longer the over-throwing time, the greater the depth of the butterfly.

In the semiconductor multilayer interconnection structure, the uneven surface of the silicon wafer with severe dishing will cause a series of problems, the most serious of which is the inability to perform patterning on the surface of the silicon wafer, which will lead to the stability of the subsequent process Reduced, affecting the process window for chemical mechanical polishing of copper metal in multilayer interconnect structures.

On the other hand, the dishing produced by excessive grinding during chemical mechanical polishing of copper can also lead to excessive resistance of copper interconnection lines, resulting in slower processing of semiconductor devices, and even the loss of copper due to excessive heat generation. The interconnection line is blown, whereby the disconnection of the semiconductor device occurs.

CN108682650A discloses a surface planarization method and a semiconductor multilayer interconnection structure. The method includes: a first chemical mechanical polishing process, which is to chemically mechanically polish the metal deposited in the deep hole in the semiconductor multilayer interconnection structure; the second medium A layer forming process, forming a second dielectric layer on the surface of the barrier layer in the semiconductor multilayer interconnection structure; and a second chemical mechanical polishing process, performing chemical mechanical polishing on the second dielectric layer and the barrier layer. However, this method adds a second dielectric layer forming process and a chemical mechanical polishing process, and the cost is high. The methods such as CN1855417A and CN1855420A also have the problems of high cost and complicated process.

Therefore, a low-cost semiconductor surface planarization process capable of controlling the size of the butterfly recess is needed.

Contents of the invention

The following is an overview of the topics described in detail in this article. This summary is not intended to limit the scope of the claims.

In view of the problems existing in the related technology, the embodiment of the present application provides a method for planarizing the surface of a semiconductor and the semiconductor and its use. The method only adds a planarization process without changing the original deposition process. The process solves the superposition problem of the butterfly-shaped depressions in the multilayer interconnection structure, and improves the performance of the semiconductor with the multilayer interconnection structure.

In a first aspect, an embodiment of the present application provides a method for planarizing a semiconductor surface, the method comprising:

In the manufacturing process of the nth section of the at least two-layer semiconductor interconnection structure, after the nth section of the initial dielectric layer is covered, the nth section of the initial dielectric layer is first planarized in the thickness direction to obtain the nth section of the dielectric layer, Then proceed to the follow-up process;

The thickness of the nth section of the initial dielectric layer is greater than the thickness of the nth section of the dielectric layer, n≥2.

The method described in this application makes the thickness of the nth initial dielectric layer thicker than that of the prior art when covering the nth initial dielectric layer, and then adds a planarization treatment step to make the processed nth initial dielectric layer The initial dielectric layer no longer has butterfly-shaped depressions, but is a flat surface, thereby solving the superposition problem of butterfly-shaped depressions on the semiconductor surface in the multilayer interconnection structure.

The value range of n mentioned in this application is a natural number ≥ 2, for example, it can be 2, 3, 4, 5 or 6, etc., and can be adjusted according to the actual process, as long as it is a manufacturing process superimposed on the basis of the first stage of manufacturing process That's it.

Preferably, the planarization method includes a chemical mechanical polishing method.

Preferably, the thickness of the n-th initial dielectric layer is greater than the thickness of the first-stage dielectric layer in the first-stage manufacturing process. Due to the planarization treatment step, one layer thickness is removed in the thickness direction, and at the same time, the portion with the recess in the nth segment of the initial dielectric layer is removed to obtain a flat surface of the nth segment of the dielectric layer.

Preferably, the thickness of the nth dielectric layer is equal to the thickness of the first dielectric layer in the first manufacturing process.

In general, the dielectric layers of each layer of the semiconductor of the multilayer interconnection structure are set to be the same, so the thickness of the nth dielectric layer is preferred to be the same as that of the first dielectric layer in this application, but each segment can also be set according to the actual situation. The thickness of the dielectric layer, as long as the thickness of the final nth dielectric layer is combined with the expected design thickness.

Preferably, the surface of the nth initial dielectric layer contains butterfly-shaped depressions. Since the surface topography of the dielectric layer in the first stage or the dielectric layer in the previous stage has a butterfly-shaped depression, this butterfly-shaped depression is due to the grinding of the metal in the first-stage manufacturing process or the first-stage manufacturing process, in order to ensure complete removal The remaining metal above the groove generally requires over-throwing to ensure that the metal above the groove is removed, and the metal inside the groove will be removed during the over-throwing process, resulting in the formation of butterfly-shaped depressions. On the basis of the above process, continue to cover the surface with a dielectric layer, and the previous butterfly-shaped depression will continue to remain, so the surface of the nth initial dielectric layer contains a butterfly-shaped depression.

Preferably, the thickness of the n-th initial dielectric layer is greater than the thickness of the n-th dielectric layer by a value greater than the depth of the butterfly-shaped depression. In order to ensure that the surface of the dielectric layer after planarization has no butterfly-shaped depressions, and its thickness value can meet the standard, the application preferably has the thickness of the nth segment of the initial dielectric layer greater than the thickness of the nth segment of the dielectric layer. The value is greater than the depth value of the butterfly-shaped depression, so as to reserve sufficient operating thickness for planarization.

Preferably, the thickness of the nth initial dielectric layer is 2000-3000A thicker than that of the nth dielectric layer, such as 2000A, 2100A, 2200A, 2300A, 2400A, 2500A, 2600A, 2800A or 3000A. Although the present application can also adjust appropriately the difference between the thickness of the nth section of the initial dielectric layer and the thickness of the nth section of dielectric layer according to the actual process design; The thickness is generally considered to be around 2000A. In this application, it is preferable to limit the thickness of the nth initial dielectric layer to be 2000-3000A thicker than the thickness of the nth dielectric layer, which can better meet the structural design of the semiconductor.

The present application generally does not make special restrictions on the subsequent process, and the subsequent manufacturing process well-known to those skilled in the art can be used, and can also be adjusted according to the actual process situation, but further preferably, in the n-th stage of manufacturing process, the Subsequent processes sequentially include capping the etch barrier layer, photolithography, etching, capping the barrier layer, capping the metal layer, and polishing.

Preferably, said polishing comprises chemical mechanical polishing.

Preferably, the covering metal layer includes photolithography, etching and deposition performed in sequence.

Preferably, the manufacturing process includes a damascene manufacturing process.

The present application has no special restrictions on other process parameters in the Damascus manufacturing process, and any process parameters known to those skilled in the art that can be used in the Damascus manufacturing process can be used, and can also be adjusted according to the actual process.

Preferably, the metal layer comprises a copper layer.

The present application has no special restrictions on the material and thickness of the dielectric layer, and any material and thickness known to those skilled in the art that can be used in semiconductor dielectric layers can be used, for example, oxides and/or nitrides can be included, for example, it can be Silicon nitride or silicon oxide, etc., may have a thickness of 2500 Å, for example.

The present application has no special restrictions on the material and thickness of the barrier layer, and any material and thickness known to those skilled in the art that can be used for barrier layers in semiconductors can be used, for example, it can include oxide and/or nitride, for example, it can be positive Silicon oxide prepared from tetraethyl silicate (TEOS), etc., may have a thickness of 400 Å, for example.

As a preferred technical solution of the present application, the method includes the following steps:

(1) Perform the first stage of Damascus manufacturing process to obtain the first stage of semiconductor structure;

(2) After the surface of the first section of the semiconductor structure in step (1) is covered with the nth section of the initial dielectric layer, the nth section of the initial dielectric layer is first planarized in the thickness direction to obtain the nth section of the dielectric layer ; The thickness of the nth segment of the initial dielectric layer is greater than the thickness of the nth segment of the dielectric layer, n≥2;

(3) Covering the surface of the nth section dielectric layer with an etching barrier layer, photolithography, etching, covering the barrier layer, covering the metal layer and polishing to obtain the nth section semiconductor structure;

Repeat steps (2)-(3) until the designed semiconductor is obtained.

In a second aspect, an embodiment of the present application provides a semiconductor, which is manufactured according to the method for flattening a semiconductor surface described in the first aspect.

Because the semiconductor described in the present application has small bow-shaped depressions and low resistance of metal interconnection lines, the processing speed of the finally formed semiconductor device is fast, and the disconnection phenomenon of the semiconductor device can be reduced.

Preferably, the semiconductor has at least two layers of interconnection structures. The at least two-layer interconnection structure in this application refers to at least two repeated vertically stacked semiconductor structural units.

In this application, there is no special limitation on the structural unit of the semiconductor in each segment, and any semiconductor unit structure known to those skilled in the art can be used, and can also be adjusted according to the actual situation.

Preferably, the semiconductor structure of the first stage from bottom to top in the semiconductor includes a dielectric layer, the surface of the dielectric layer is provided with a first barrier layer, and the dielectric layer and the first barrier layer are provided with grooves at corresponding positions, so The groove of the first barrier layer penetrates from the surface of the first barrier layer into the dielectric layer, the dielectric layer and the first barrier layer correspond to metal deposited in the groove, and the surface of the metal in the groove contains butterfly-shaped depressions. The semiconductor structure of the other stage is preferably the same as the semiconductor structure of the first stage.

Preferably, the semiconductor is a wafer. By further optimizing the wafer, the degree of butterfly dishing of the wafer is significantly reduced.

In a third aspect, the embodiment of the present application provides an application of the semiconductor described in the first aspect in an integrated circuit.

The semiconductor described in the present application has excellent processing speed and low resistance due to the small butterfly depression, and can be used in integrated circuits to greatly increase the operating efficiency of integrated circuits.

Compared with related technologies, the embodiments of the present application have at least the following beneficial effects:

(1) The semiconductor surface planarization method provided by the embodiment of the present application overcomes the influence of the butterfly-shaped depressions produced by the front-end manufacturing process in the at least two-layer interconnection structure, which is superimposed on the back-end process, and only needs to increase the thickness of the dielectric layer in the original step The thinning step can effectively control the size of the butterfly, and the difference between the depth of the butterfly depression of the nth semiconductor structure and the depth of the butterfly depression of the first semiconductor structure is ≤70A, and under optimal conditions ≤20A, It can even reach ≤2A or the depth of the butterfly-shaped recess of the n-th semiconductor structure is smaller than that of the first-stage semiconductor structure, and the preparation process is simple and the cost is low;

(2) The semiconductor provided by the embodiment of the present application has a small butterfly-shaped depression and low resistance of the metal interconnection line, so the processing speed of the final semiconductor device is fast, and the disconnection phenomenon of the semiconductor device can be reduced, so it can be better applied to integrated circuits. in the circuit.

Other aspects will be apparent to others upon reading and understanding the drawings and detailed description.

Description of drawings

The accompanying drawings are used to provide a further understanding of the technical solutions herein, and constitute a part of the description, and are used together with the embodiments of the application to explain the technical solutions herein, and do not constitute limitations to the technical solutions herein.

FIG. 1 is a schematic flowchart of a method for planarizing a semiconductor surface provided by the present application.

FIG. 2 is a schematic flowchart of a method for preparing a semiconductor provided in Comparative Example 1.

In the figure: 1-the first semiconductor structure; 21-the second initial dielectric layer; 22-the butterfly-shaped depression on the surface of the second initial dielectric layer; 23-the second dielectric layer; 24-etching barrier layer; 25-metal copper; 26 - Butterfly-shaped depressions on metallic copper surfaces.

Detailed ways

The technical solution of the present application will be further described below in conjunction with the accompanying drawings and through specific implementation methods.

The application will be further described in detail below. However, the following examples are only simple examples of the present application, and do not represent or limit the protection scope of the present application, and the protection scope of the present application shall be determined by the claims.

It should be understood that in the description of the present application, the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", " The orientation or positional relationship indicated by "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and The description is simplified, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and operate, and thus should not be construed as limiting the application. In addition, the terms "first", "second", etc. are used for descriptive purposes only, and should not be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, a feature defined as "first", "second", etc. may expressly or implicitly include one or more of that feature. In the description of the present application, unless otherwise specified, "plurality" means two or more.

It should be noted that, in the description of this application, unless otherwise clearly stipulated and limited, the terms "set", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it can be mechanical connection or electrical connection; it can be direct connection or indirect connection through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application based on specific situations.

As a specific embodiment of the present application, a method for planarizing the surface of a semiconductor is provided. Taking the two-stage Damascene process as an example, as shown in Figure 1, the method includes the following steps:

(1) Carry out the first section of damascene manufacturing process to obtain the first section of semiconductor structure 1, the first section of semiconductor structure 1 includes a dielectric layer, the surface of the dielectric layer is provided with a first barrier layer, the dielectric layer and the first section of semiconductor structure 1 A barrier layer is provided with a groove at a corresponding position, and the groove of the first barrier layer penetrates from the surface of the first barrier layer into the dielectric layer, and metal copper is deposited in the dielectric layer, and the metal copper in the groove is The surface contains butterfly-shaped depressions;

(2) After the surface of the first stage semiconductor structure 1 described in step (1) is covered with the second initial dielectric layer 21, a semiconductor structure covered with the second initial dielectric layer 21 is obtained, as shown in a in FIG. 1, at this time The butterfly-shaped depression 22 on the surface of the second initial dielectric layer can be seen;

The second initial dielectric layer 21 is first planarized in the thickness direction to obtain a second dielectric layer 23, as shown in b in Figure 1; the thickness of the second initial dielectric layer 21 is greater than that of the second dielectric layer 23 thickness;

(3) covering the etching barrier layer 24, photolithography, etching, covering the second barrier layer (not shown), covering metal copper 25 and polishing successively on the surface of the second dielectric layer 23, after covering the etching barrier layer 24, as As shown in c in Fig. 1, covered with metal copper 25, as shown in d in Fig. 1, and after polishing, as shown in e in Fig. 1, it can be seen that the butterfly-shaped depression of the semiconductor structure 1 in the first stage has not been transferred to the second stage , to obtain the second section of semiconductor structure; the second section of semiconductor structure after molding includes a second dielectric layer 23, the surface of the dielectric layer 23 is provided with grooves, and metal copper is deposited in the corresponding grooves of the dielectric layer 23 25. The surface of the metal copper 25 in the groove contains a butterfly-shaped depression 26 on the surface of the metal copper to obtain a designed double-layer Damascus metal copper wafer.

In the above specific implementation manner, the depth of the groove is not particularly limited, and can be adjusted according to the actual process, for example, it can be 200A. Likewise, the thicknesses of the dielectric layer, the etch barrier layer, the first barrier layer, and the second barrier layer are not particularly limited, and can be adjusted according to the actual process. For example, the thickness of the dielectric layer can be 2500 Å, etc., and the first barrier layer and the second barrier layer The thickness of the layer may be 400A and so on.

Example 1

This embodiment provides a method for flattening a semiconductor surface, the method comprising the following steps:

(1) Carry out the first paragraph of damascene manufacturing process. The first paragraph of damascene manufacturing process specifically includes: performing chemical vapor deposition of 400A of etching barrier layer (silicon oxide) on the surface of dielectric layer (silicon oxide), and then performing photolithography in sequence , etching and copper deposition (electroplating, the process parameter is 7000A), and then perform three chemical mechanical polishing, the first chemical mechanical polishing is ground with high pressure ~ 2psi to remove most of the copper above the trench; the second chemical mechanical polishing is used Relatively small pressure ~1.2psi removes the remaining metal copper above the trench; the third chemical mechanical polishing thins the trench and the silicon oxide next to it to a thickness of ~1000A required by the process, and deposits the first barrier layer. The first barrier layer is a silicon carbide layer used to prevent metal from diffusing into the dielectric layer, with a thickness of 200 Å, to obtain the first-stage semiconductor structure 1; a first barrier layer is provided on the surface of the dielectric layer, and the dielectric layer and the first The barrier layer is provided with grooves at corresponding positions, and the groove of the first barrier layer penetrates from the surface of the first barrier layer into the dielectric layer, and metal copper is deposited in the dielectric layer, and the surface of the metal copper in the groove is Contains butterfly-shaped depressions;

(2) After the second initial dielectric layer 21 is covered on the surface of the second semiconductor structure in step (1), the second initial dielectric layer 21 is first subjected to a planarization process in the thickness direction, and the planarization process is chemical mechanical polishing treatment, the pressure is ~2.0psi, and the time is ~30s to obtain the second dielectric layer 23; the thickness of the second initial dielectric layer 21 is 2500A thicker than the thickness of the second dielectric layer 23;

(3) Cover the etching barrier layer 24 (silicon oxide, 400A) on the surface of the second dielectric layer 23, through photolithography, etching, depositing the second barrier layer and covering metal copper 25 and chemical mechanical polishing three times, wherein the The second barrier layer is a tantalum nitride layer used to prevent the metal from diffusing into the dielectric layer, with a thickness of 100 Å. The three chemical mechanical polishing and deposition steps are carried out with reference to step (1) to obtain the second segment of the semiconductor structure, and the designed double layer damascus metal copper wafer.

Example 2

(1) Carry out the first paragraph of damascene manufacturing process, and the first paragraph of damascene manufacturing process specifically includes: depositing (chemical vapor deposition, process parameter is 300A) etching barrier layer (silicon oxide) on the surface of dielectric layer (silicon oxide) and Perform photolithography, etching and copper deposition (electroplating, process parameters: 7500A) in sequence, and then perform chemical mechanical polishing three times. The first chemical mechanical polishing is performed under high pressure ~ 2.5psi grinding to remove most of the copper above the trench; the second The first chemical mechanical polishing uses a relatively small pressure ~ 1.4psi to remove the remaining metal copper above the trench; the third chemical mechanical polishing thins the trench and the oxide layer next to it to the thickness required by the process ~ 1600A, and deposits the first The barrier layer, that is, silicon carbide, has a thickness of 150 Å, and the first semiconductor structure 1 is obtained; the first semiconductor structure 1 includes a dielectric layer, and a first barrier layer is provided on the surface of the dielectric layer, and the dielectric layer and the first semiconductor structure A barrier layer is provided with a groove at a corresponding position, and the groove of the first barrier layer penetrates from the surface of the first barrier layer into the dielectric layer, and metal copper is deposited in the dielectric layer, and the metal copper in the groove is The surface contains butterfly-shaped depressions;

(2) After the second initial dielectric layer 21 is covered on the surface of the second semiconductor structure in step (1), the second initial dielectric layer 21 is first subjected to a planarization process in the thickness direction, and the planarization process is chemical mechanical polishing treatment, the pressure is ~2.5psi, the time is ~30s, to obtain the second dielectric layer 23; the thickness of the second initial dielectric layer 21 is 2000A thicker than the thickness of the second dielectric layer 23;

(3) Cover the etching barrier layer 24 (500A) on the surface of the second dielectric layer 23, and sequentially undergo photolithography, etching, depositing the second barrier layer and covering the metal copper layer and chemical mechanical polishing three times, wherein the first The second barrier layer is a tantalum nitride layer used to prevent the metal from diffusing into the dielectric layer, with a thickness of 120A. The three chemical mechanical polishing and deposition steps are carried out with reference to step (1) to obtain the second semiconductor structure and the designed double layer Damascus metal copper wafer.

Example 3

(1) Carry out the first paragraph of damascene manufacturing process, and the first paragraph of damascene manufacturing process specifically includes: depositing (chemical vapor deposition, process parameter is 600A) etching barrier layer (silicon oxide) on the surface of dielectric layer (silicon oxide) and Etch the deep hole, then perform photolithography, etching and copper deposition (electroplating, process parameter is 8000A) in sequence, and then perform three chemical mechanical polishing. The first chemical mechanical polishing is performed under high pressure ~ 1.8psi grinding to remove most of the top of the groove Copper; the second chemical mechanical polishing uses a relatively small pressure ~ 1.5psi to remove the remaining metallic copper above the trench; the third chemical mechanical polishing thins the trench and the oxide layer next to it to the thickness required by the process ~ 1200A , to obtain the first semiconductor structure 1; the first semiconductor structure 1 includes a dielectric layer, the surface of the dielectric layer is provided with a first barrier layer, and the dielectric layer and the first barrier layer are provided with grooves at corresponding positions , the groove of the first barrier layer penetrates from the surface of the first barrier layer into the dielectric layer, metal copper is deposited in the dielectric layer, and the surface of the metal copper in the groove contains butterfly-shaped depressions;

(2) After the second initial dielectric layer 21 is covered on the surface of the second semiconductor structure in step (1), the second initial dielectric layer 21 is first subjected to a planarization process in the thickness direction, and the planarization process is Chemical mechanical polishing treatment, the pressure is ~2.1psi, the time is ~35s, to obtain the second dielectric layer 23; the thickness of the second initial dielectric layer 21 is 3000A thicker than the thickness of the second dielectric layer 23;

(3) Cover the etching stopper layer 24 (400A) on the surface of the second dielectric layer 23 and sequentially undergo photolithography, etching, depositing a second stopper layer, covering metal copper 25 and chemical mechanical polishing three times, wherein the second The barrier layer is a tantalum nitride layer used to prevent the metal from diffusing into the dielectric layer, with a thickness of 110 Å. The three steps of chemical mechanical polishing and deposition are carried out with reference to step (1) to obtain the second semiconductor structure;

Steps (2) to (3) are repeated to construct the third semiconductor structure on the second semiconductor structure to obtain a designed three-layer damascene copper wafer.

Example 4

This embodiment provides a method for flattening the surface of a semiconductor. The method is the same as that of Embodiment 1 except that the thickness of the second initial dielectric layer 21 is 6000 Å thicker than that of the second dielectric layer 23 . Compared with the first embodiment, the cost of the present embodiment is increased due to the thicker thickness of the initially deposited dielectric layer.

Example 5

This embodiment provides a method for flattening the surface of a semiconductor. The method is the same as that of Embodiment 1 except that the thickness of the second initial dielectric layer 21 is 200 Å thicker than that of the second dielectric layer 23 . In this embodiment, since the thickness of the initially deposited dielectric layer is not enough to fill the depth of the butterfly-shaped depression accumulated in the first stage of the process, the surface of the second dielectric layer 23 still has a small butterfly-shaped depression after the planarization treatment.

Comparative example 1

This comparative example provides a method for semiconductor preparation, as shown in Figure 2, except that the thickness of the second initial dielectric layer 21 covered in step (2) is directly the same as the thickness of the second dielectric layer 23 in Example 1 , the preparation process parameter in step (1)～(3) is all identical with embodiment 1, specifically comprises the following steps:

(2) Covering the second dielectric layer 23 on the surface of the second semiconductor structure described in step (1);

(3) covering the etching barrier layer 24 (silicon oxide, 400A) on the surface of the second dielectric layer 23 in sequence, and sequentially undergoing photolithography, etching, depositing the second barrier layer, covering metal copper 25 and chemical mechanical polishing three times, Wherein the second barrier layer is a tantalum nitride layer used to prevent the metal from diffusing to the dielectric layer, with a thickness of 100 Å. After the barrier layer 24 is etched, it is shown in c in FIG. 2 , and after covering the metal copper 25, it is shown in d in FIG. 2 As shown in e in Figure 2 after polishing, it can be seen that the butterfly-shaped depression of the first segment of the semiconductor structure 1 continues to be transmitted to the second segment to obtain the second segment of the semiconductor structure; the second segment of the semiconductor structure after molding includes The second dielectric layer 23, the dielectric layer 23 is provided with a groove, the groove deposited on the dielectric layer 23 has metal copper 25, and the surface of the metal copper 25 in the groove contains a butterfly-shaped depression 26 on the surface of the metal copper , the designed double-layer damascene metal copper wafer is obtained, but the butterfly-shaped depression of the second-stage semiconductor structure in the wafer is significantly increased compared with the butterfly-shaped depression of the first-stage semiconductor structure 1.

The method described in the present application is also applicable to the semiconductor manufacturing of other multi-segment semiconductor structures, and will not be repeated here for the sake of space.

Test method: AFM (atomic force microscope) was used to measure the depth of the butterfly-shaped depressions in the wafers prepared in the above examples and comparative examples, and the results are shown in Table 1.

Table 1

The following points can be seen from Table 1:

(1) It can be seen from comprehensive embodiments 1 to 3 that the method for flattening the semiconductor surface provided by the present application can effectively organize the depth value of the butterfly-shaped depression in the semiconductor structure of the first stage in the semiconductor structure manufacturing process of at least two stages. The second-stage semiconductor structure or the third-stage semiconductor structure transformation, that is, the difference between the butterfly-shaped depression depth of the semiconductor structure larger than the first stage and the butterfly-shaped depression depth of the first-stage semiconductor structure is ≤ 20A;

(2) Combining Example 1 and Examples 4 to 5, it can be seen that the thickness of the second initial dielectric layer in Example 1 is 2500 Å thicker than that of the second dielectric layer, compared with Example 4 and Example 5 In terms of the thickness of the second initial dielectric layer being 6000A and 200A thicker than the thickness of the second dielectric layer, the butterfly-shaped depression of the second stage semiconductor structure in Example 1 is only 220A, which is 15A larger than that of the first stage , while in Example 4, although it is only increased by 2A compared with the first section, the thickness of the dielectric layer is increased too much, and the cost increases significantly. In Example 5, the second section is increased by 70A compared with the first section, and the butterfly-shaped depression has a certain degree of transmission. This shows that the present application can reduce the transfer of butterfly-shaped depressions while controlling the cost by controlling the thickness of the nth initial dielectric layer to be thicker than that of the nth dielectric layer within a specific range;

(3) Combining Example 1 and Comparative Example 1, it can be seen that in Comparative Example 1, only the thickness of the final second dielectric layer is deposited directly during deposition, and the butterfly-shaped depression of the final second section of the semiconductor structure is as high as 295 Å, which is higher than that of the first section. The butterfly-shaped depression of the semiconductor structure is 100A high, which is much higher than 15A in Example 1. This shows that the present application significantly reduces the butterfly-shaped depression by increasing the thickness of the dielectric layer during initial deposition and adding a step of chemical mechanical polishing. Transfer between several segments of semiconductor structures.

To sum up, the semiconductor surface planarization method provided by this application overcomes the influence of superposition of butterfly-shaped depressions produced by the front-end manufacturing process in the back-end process in at least two-layer interconnection structures, so that the size of the butterfly is effectively controlled and the cost is reduced. Low, suitable for industrial promotion.

The applicant declares that the present application illustrates the detailed structural features of the present application through the above embodiments, but the present application is not limited to the above detailed structural features, that is, it does not mean that the application must rely on the above detailed structural features to be implemented. Those skilled in the art should understand that any improvement to the application, equivalent replacement of the components selected in the application, addition of auxiliary components, selection of specific methods, etc., all fall within the scope of protection and disclosure of the application.

Claims

A method for flattening a semiconductor surface, comprising:

In the manufacturing process of the nth section of the at least two-layer semiconductor interconnection structure, after the nth section of the initial dielectric layer is covered, the nth section of the initial dielectric layer is first planarized in the thickness direction to obtain the nth section of the dielectric layer, Then proceed to the follow-up process;

The thickness of the nth section of the initial dielectric layer is greater than the thickness of the nth section of the dielectric layer, n≥2.
The method according to claim 1, wherein the thickness of the n-th initial dielectric layer is greater than the thickness of the first-stage dielectric layer in the first-stage manufacturing process.
The method according to claim 1 or 2, wherein the thickness of the nth dielectric layer is equal to the thickness of the first dielectric layer in the first manufacturing process.
The method according to any one of claims 1-3, wherein the surface of the nth stage of initial dielectric layer contains butterfly-shaped depressions.
The method according to claim 4, wherein the thickness of the nth initial dielectric layer is greater than the thickness of the nth dielectric layer by a value greater than the depth of the butterfly-shaped depression.
The method according to any one of claims 1 to 5, wherein the thickness of the nth stage of initial dielectric layer is 2000˜3000 Å greater than the thickness of the nth stage of dielectric layer.
The method according to any one of claims 1 to 6, wherein, in the n-th manufacturing process, the subsequent steps sequentially include covering the etching barrier layer, photolithography, etching, covering the barrier layer, covering the metal layer and polishing.
The method of claim 7, wherein the polishing comprises chemical mechanical polishing.
The method according to any one of claims 1-8, wherein the manufacturing process comprises a damascene manufacturing process.
A semiconductor, characterized in that the semiconductor is produced according to the method for planarizing the surface of a semiconductor according to any one of claims 1-9.
The semiconductor according to claim 10, wherein said semiconductor is a wafer.
Use of a semiconductor according to claim 11 in an integrated circuit.