CN107809838A - Mainboard and server - Google Patents
Mainboard and server Download PDFInfo
- Publication number
- CN107809838A CN107809838A CN201710906636.6A CN201710906636A CN107809838A CN 107809838 A CN107809838 A CN 107809838A CN 201710906636 A CN201710906636 A CN 201710906636A CN 107809838 A CN107809838 A CN 107809838A
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- China
- Prior art keywords
- mainboard
- pairs
- signal lines
- differential signal
- cabling
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0228—Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors
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- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
The present invention provides a kind of mainboard and server.The mainboard uses the stack-design of Dual Stripline patterns, arc ZigZag mode cablings are respectively adopted in two pairs of corresponding differential signal lines in two signals layers up and down of the mainboard, and the angle and distance of separation of setting are kept between two pairs of differential signal lines.The present invention can reduce the signal cross-talk between the parallel cabling of upper and lower two signals layer middle-high densities.
Description
Technical field
The present invention relates to printed circuit board technology field, more particularly to a kind of mainboard and server.
Background technology
Along with the rise of cloud computing, server quickly grows emergence, and in the design of server, signal rate is more next
Higher, high speed signal is constantly being lifted to the spatial design demand and cost of mainboard.To reduce development cost, in stack-design
In, Dual Stripline (biobelt line) pattern enjoys designer to favor.With conventional Stripline (strip line) pattern not
Together, it is the characteristics of the stack-design of Stripline patterns：There are GND or PWR layers between signals layer and signals layer, 12 laminates there are 6 layers
Routing layer；And the characteristics of stack-design of Dual Stripline patterns, is：Two layers of signals layer is designed as adjacent layer, signals layer
It is simultaneously GND or PWR layers, another side is adjacent with other signals layers, and 12 laminates can have 8 layers of routing layer under this pattern.Obviously,
Dual Stripline patterns can reduce the lamination number of plies, cost-effective.
HW High Way is often designed to difference form, when high-speed differential signal line is with Dual Stripline pattern cloth
During line, it is typically due to that mainboard wiring space is limited to cause away line density larger, the parallel cabling of upper and lower two signals layers occurs to walk
The situation of line face, now the parasitic capacitance between signal wire and inductive sensor are maximum, it may appear that serious signal cross-talk.
To reduce the crosstalk between signal wire, there is scheme to propose a kind of staggered parallel cabling mode, as shown in figure 1, the cabling mode
Front and rear two sections of crosstalk noise amplitudes are identical, opposite polarity, in theory total crosstalk noise can be made to cancel out each other.
During the present invention is realized, inventor has found following technical problem in the prior art at least be present：
Staggered parallel cabling mode can only eliminate the crosstalk between two pairs of differential lines of upper and lower two signals layer faces, still
But can not eliminate and adjacent signal layers remaining to the crosstalk between differential lines, therefore for the parallel cabling of high density, the cabling side
Formula can not reduce the crosstalk between signal wire.
The content of the invention
Mainboard and server provided by the invention, it can reduce between the parallel cabling of upper and lower two signals layer middle-high densities
Signal cross-talk.
In a first aspect, the present invention provides a kind of mainboard, the mainboard uses the stack-design of Dual Stripline patterns,
Arc ZigZag mode cablings, institute is respectively adopted in two pairs of corresponding differential signal lines in two signals layers up and down of the mainboard
State the angle and distance of separation that setting is kept between two pairs of differential signal lines.
Alternatively, the angle between two pairs of differential signal lines is 15 ° to 30 °.
Alternatively, the arc ZigZag cabling parameters of two pairs of differential signal lines are identical.
Alternatively, each pair of differential signal line in the same signals layer of the mainboard is parallel to each other.
Second aspect, the present invention provide a kind of server, and the server includes above-mentioned mainboard.
Mainboard and server provided by the invention, the mainboard use the stack-design of Dual Stripline patterns, on
Arc ZigZag mode cablings, two pairs of difference letter is respectively adopted in two pairs of corresponding differential signal lines in lower two signals layers
The angle and distance of separation of setting are kept between number line, compared with prior art, for the high density in the confined space it is parallel walk
Line, be not in the situation of upper and lower layer signal face, the Electromagnetic Wave Propagation direction on the corresponding signal wire of levels occurs
Change, the electromagnetic wave of signal wire coupling is effectively weakened, the crosstalk between levels signal wire can be reduced.
Brief description of the drawings
Fig. 1 is the schematic diagram of existing staggered parallel cabling mode；
Fig. 2 is the schematic diagram of the arc ZigZag cabling modes of the present invention；
Fig. 3 is the schematic diagram that two groups of differential pairs use staggered parallel cabling mode；
Fig. 4 is the schematic diagram that two groups of differential pairs use arc ZigZag cabling modes.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only
Only it is part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, ordinary skill
The every other embodiment that personnel are obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
The embodiment of the present invention provides a kind of mainboard, and the mainboard uses the stack-design of Dual Stripline patterns, institute
Mainboard is stated when entering walking line design, arc is respectively adopted in two pairs of corresponding differential signal lines in upper and lower two signals layers
ZigZag mode cablings, circular arc cabling is used in cabling corner location, other positions use straight line, two pairs of differential signal lines it
Between keep setting angle and distance of separation.Two pairs of corresponding differential signal lines are in two signals layers up and down mentioned here
Two pairs of maximum differential signal lines of cross talk effects between finger.
As shown in Fig. 2 a kind of arc ZigZag for two pairs of differential signal lines corresponding in upper and lower two signals layers is walked
Line schematic diagram, simple in order to design, the arc ZigZag cabling parameters of two pairs of differential signal lines are identical, that is to say, that its
Middle differential pair 1 is identical with the cabling form of differential pair 2, simply the relation of right position translation.Set in differential pair 1 and differential pair 2
One signal line in top face is positive signal line, and a signal line in face is negative signal line, positive signal line and negative signal line on the lower
Parallel, the arc top position of differential pair 1 and the arc bottom position correspondence of differential pair 2, θ represent the folder between differential pair 1 and differential pair 2
Angle, L represent the distance of separation between differential pair 1 and differential pair 2.Herein, distance of separation refers to the arc top of differential pair 1 to difference
To 2 the distance between arc bottom, the distance between respective positive signal line in two differential pairs is generally taken.It is of course also possible to take
The distance between respective negative signal line in two differential pairs.
By taking differential pair 1 as an example, a~e can regard a cycle of arc ZigZag cablings as, and wherein a~b is one section of circle
Arc, b~c are straight lines, and c~d is one section of circular arc, and arc radius is identical with a~b, and d~e is straight line, is repeated cyclically away afterwards
Line.The cabling of signal uses circular arc cabling in corner location, rather than using acute angle, right angle, obtuse angle, because the angle of the latter
Cabling mode can all cause the discontinuous of impedance, and so as to cause the phenomenon of reflection to occur, the energy of signal has been lost, has reduced signal
Reliability transmission.Parasitic capacitance can be additionally produced, is slowed down the rise time, and wedge angle produces EMI etc..Above-mentioned influence with
The continuous improvement of signal frequency, and influence further obvious.
During actual design, if the angle and distance of separation mistake of the corresponding two pairs of differential signal lines of upper and lower two signals layers
Greatly, it can not only increase board area, increase cost, and track lengths can be increased, increase the link load of signal；If angle
It is too small with distance of separation, the crosstalk between cabling can be influenceed because of the Kelvin effect of electric current again, and be unfavorable for evading glass effect
Influence.Here glass effect refers to, because the warp thread weft yarns of glass-fiber-fabric in PCB dielectric layers have gap, causes to be situated between
The localized variation of matter layer relative dielectric constant.PCB dielectric layer is that the liquid solidify afterwards that upper epoxy resin is soaked by glass-fiber-fabric form,
And the difference in dielectric constant of glass-fiber-fabric and epoxy resin, at 2 times or so, with the continuous lifting of signal frequency, glass effect causes
Delay between differential pair is very important.
Therefore two pairs of corresponding differential signal line arc routing modes of two signals layers (mainly include walking line length up and down
Degree, arc radius etc.) and angle each other and distance of separation need to consider following factor：The making of mainboard
Cost, the complexity of cabling and signal cross-talk, arc ZigZag cablings are determined with reference to specific cabling and conditions of demand
Optimum angle and optimal distance of separation.Consider space limitation and signal performance, the angle of two pairs of differential signal lines are generally set
It is calculated as 15 ° to 30 °.
After the completion of cabling, whether given threshold can be more than with the crosstalk signal of post-simulation once mainboard, if more than setting
Threshold value, angle between the corresponding two pairs of differential signal lines of two signals layers up and down and distance of separation are adjusted until the string of mainboard
Disturb signal and be less than given threshold.
It is assumed that the corresponding two pairs of differential signal lines of upper and lower two signals layers are one group, when relative in upper and lower two signals layers
During the differential signal line more than one set answered, exemplified by two groups, differential pair 1 and differential pair 2 are corresponding, differential pair 3 and the phase of differential pair 4
Corresponding, as shown in Figure 3 and Figure 4, respectively two groups of corresponding differential signal lines use staggered parallel mode cabling and arc
ZigZag mode cablings, in the same signals layer of mainboard, each pair of differential signal line is parallel to each other.Differential pair 3 and differential pair 1
Parallel, differential pair 4 is parallel with differential pair 2.
Under the equal environment of lamination, medium, model length, crosstalk emulation point is carried out by the use of HFSS softwares as emulation tool
Analysis.Crosstalk is formed by electromagnetic coupled, signal by during one section of conductor can to cause on its adjacent conductor capacitive coupling noise and
Inductive coupled noise.By the 3D model emulations of HFSS softwares, simulation electromagnetic wave upper and lower two signals under two kinds of cabling modes
Propagation between each differential pair of layer, obtains crosstalk result.Simulation result shows, using crosstalk during cabling mode of the invention
It is significantly less than crosstalk during staggered parallel cabling mode.
Mainboard provided in an embodiment of the present invention, using the stack-design of Dual Stripline patterns, upper and lower two signals
Arc ZigZag mode cablings are respectively adopted in two pairs of corresponding differential signal lines in layer, keep setting between two pairs of differential signal lines
Fixed angle and distance of separation, compared with existing staggered parallel cabling mode, for the high density in the confined space it is parallel walk
Line, be not in the situation of upper and lower layer signal face, the Electromagnetic Wave Propagation direction on the corresponding signal wire of levels occurs
Change, the electromagnetic wave of signal wire coupling is effectively weakened, the crosstalk between levels signal wire can be reduced, improve mainboard
Energy.Board area does not have too many increase simultaneously, has saved cost again while the performance for improving high-speed line, has improved product
The cost performance of design, the competitiveness of lifting product commercially.In addition, the grid of arc ZigZag cablings and glass-fiber-fabric is in certain
Angle, rather than it is in parallel, so avoiding the influence that glass effect is brought.
The embodiment of the present invention also provides a kind of server, and the server includes above-mentioned mainboard.
One of ordinary skill in the art will appreciate that realize all or part of flow in above-described embodiment method, being can be with
The hardware of correlation is instructed to complete by computer program, described program can be stored in a computer read/write memory medium
In, the program is upon execution, it may include such as the flow of the embodiment of above-mentioned each method.Wherein, described storage medium can be magnetic
Dish, CD, read-only memory (Read-Only Memory, ROM) or random access memory (Random Access
Memory, RAM) etc..
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, the change or replacement that can readily occur in, all should
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be defined by scope of the claims.
Claims (5)
1. a kind of mainboard, it is characterised in that the mainboard uses the stack-design of Dual Stripline patterns, the mainboard
Arc ZigZag mode cablings, two pairs of difference is respectively adopted in two pairs of corresponding differential signal lines in upper and lower two signals layers
The angle and distance of separation of setting are kept between signal wire.
2. mainboard according to claim 1, it is characterised in that the angle between two pairs of differential signal lines be 15 ° extremely
30°。
3. mainboard according to claim 1, it is characterised in that the arc ZigZag cablings ginseng of two pairs of differential signal lines
Number is identical.
4. mainboard according to claim 1, it is characterised in that each pair of difference letter in the same signals layer of the mainboard
Number line is parallel to each other.
5. a kind of server, it is characterised in that including the mainboard as any one of Claims 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710906636.6A CN107809838A (en) | 2017-09-29 | 2017-09-29 | Mainboard and server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710906636.6A CN107809838A (en) | 2017-09-29 | 2017-09-29 | Mainboard and server |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107809838A true CN107809838A (en) | 2018-03-16 |
Family
ID=61592032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710906636.6A Pending CN107809838A (en) | 2017-09-29 | 2017-09-29 | Mainboard and server |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107809838A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110398681A (en) * | 2019-07-26 | 2019-11-01 | 苏州浪潮智能科技有限公司 | A kind of biobelt Check Methods and relevant apparatus |
| CN112911802A (en) * | 2020-12-25 | 2021-06-04 | 无锡市同步电子科技有限公司 | Differential signal line wiring method of twisted pair-like staggered layer structure |
| CN117377196A (en) * | 2023-12-06 | 2024-01-09 | 苏州元脑智能科技有限公司 | Differential line design method, system, device and medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0685411A (en) * | 1992-08-31 | 1994-03-25 | Sanyo Electric Co Ltd | Wiring structure of printed board |
| CN1197162C (en) * | 1999-10-12 | 2005-04-13 | 自由度半导体公司 | Integrated circuit with balanced twist of differential signal lines |
| CN104102787A (en) * | 2014-07-23 | 2014-10-15 | 浪潮电子信息产业股份有限公司 | Design method for reducing crosstalk effect of Dual Stripline type wiring |
| CN105117548A (en) * | 2015-08-25 | 2015-12-02 | 浪潮电子信息产业股份有限公司 | Differential routing method suitable for DUAL STRIPLINE design |
| CN105188266A (en) * | 2015-08-27 | 2015-12-23 | 浪潮电子信息产业股份有限公司 | Dual-mode high-speed signal line three-dimensional wiring method |
-
2017
- 2017-09-29 CN CN201710906636.6A patent/CN107809838A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0685411A (en) * | 1992-08-31 | 1994-03-25 | Sanyo Electric Co Ltd | Wiring structure of printed board |
| CN1197162C (en) * | 1999-10-12 | 2005-04-13 | 自由度半导体公司 | Integrated circuit with balanced twist of differential signal lines |
| CN104102787A (en) * | 2014-07-23 | 2014-10-15 | 浪潮电子信息产业股份有限公司 | Design method for reducing crosstalk effect of Dual Stripline type wiring |
| CN105117548A (en) * | 2015-08-25 | 2015-12-02 | 浪潮电子信息产业股份有限公司 | Differential routing method suitable for DUAL STRIPLINE design |
| CN105188266A (en) * | 2015-08-27 | 2015-12-23 | 浪潮电子信息产业股份有限公司 | Dual-mode high-speed signal line three-dimensional wiring method |
Non-Patent Citations (1)
| Title |
|---|
| 朱然刚等: "《中国电子学会第十届青年学术年会论文集 信息和电子技术理论与应用》", 27 September 2004 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110398681A (en) * | 2019-07-26 | 2019-11-01 | 苏州浪潮智能科技有限公司 | A kind of biobelt Check Methods and relevant apparatus |
| CN112911802A (en) * | 2020-12-25 | 2021-06-04 | 无锡市同步电子科技有限公司 | Differential signal line wiring method of twisted pair-like staggered layer structure |
| CN117377196A (en) * | 2023-12-06 | 2024-01-09 | 苏州元脑智能科技有限公司 | Differential line design method, system, device and medium |
| CN117377196B (en) * | 2023-12-06 | 2024-02-13 | 苏州元脑智能科技有限公司 | Differential line design method, system, device and medium |
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Application publication date: 20180316 |
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