CN107799522A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN107799522A CN107799522A CN201610756336.XA CN201610756336A CN107799522A CN 107799522 A CN107799522 A CN 107799522A CN 201610756336 A CN201610756336 A CN 201610756336A CN 107799522 A CN107799522 A CN 107799522A
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- H—ELECTRICITY
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Abstract
The present invention provides a kind of semiconductor structure and forming method thereof, wherein, the structure includes：Substrate, the substrate include：Device region and the first bonding pad and the second bonding pad for being located at device region both sides respectively；The first fin on the first bonding pad substrate and the second fin on the second bonding pad substrate, the first fin and the second fin are arranged in parallel, and the orientation for extending perpendicularly to the first fin and the second fin of the first fin and the second fin；Doped region in device region, the first bonding pad and the second bonding pad substrate and in the first fin and the second fin；The first connector being across on the atop part of the first fin；The second connector being across on the atop part of the second fin.When in use, the cross-sectional area for flowing through passage of electric current is larger for the semiconductor structure, and therefore, the contact resistance between the first fin and the second fin and the doped region is smaller, can improve the semiconductor structure performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
With the raising of semiconductor devices integrated level, the critical size of transistor constantly reduces, the diminution meaning of critical size
Taste can arrange greater number of transistor on chip, and then improve the performance of device.Resistive element is important on chip
Element.
Resistive element can be formed with the semiconductor layer including doped resistor region.In the doped resistor region have doping from
Son, the resistance value of the resistive element can be adjusted by adjusting the concentration of the Doped ions.And the doped region
Both ends can be electrically connected by electric interconnection structure and external circuit.
There is contact resistance between the doped region and electric interconnection structure, if the contact resistance is excessive, easily cause
Resistive element produces more heat, so as to cause self-heating effect, is also easy to make the resistance member in addition, contact resistance is excessive
The resistance value of part is too high, so as to easily influence the performance of the resistive element.
However, the contact resistance of existing resistive element is larger, the poor-performing of resistive element.
The content of the invention
It is of the invention to solve the problems, such as to be to provide a kind of semiconductor structure and forming method thereof, the semiconductor junction can be improved
Structure performance.
To solve the above problems, the present invention provides a kind of semiconductor structure, including：Substrate, the substrate include：Device region
It is located at the first bonding pad and the second bonding pad of the device region both sides respectively；On the substrate of first bonding pad
One fin and the second fin on the substrate of second bonding pad, first fin and the second fin are arranged in parallel,
And the orientation for extending perpendicularly to first fin and the second fin of first fin and the second fin；It is located at
Doped region in the device region, the first bonding pad and the second bonding pad substrate and in the first fin and the second fin；Across
The first connector on the atop part of first fin；Second be across on the atop part of second fin inserts
Plug.
Optionally, in addition to：The 3rd dummy grid on the device region doped region.
Optionally, in addition to：Across the first dummy grid of first fin, the first dummy grid covering described first
Fin partial sidewall and top surface；Across the second dummy grid of second fin, second dummy grid covering described the
Two fin partial sidewalls and top surface.
Optionally, the material of the 3rd dummy grid is polysilicon, polycrystalline germanium or polycrystalline silicon germanium.
Optionally, extension of the 3rd dummy grid bearing of trend perpendicular or parallel to first fin and the second fin
Direction.
Optionally, the material of first dummy grid and the second dummy grid is polysilicon, polycrystalline germanium or polycrystalline silicon germanium.
Optionally, first dummy grid and the second dummy grid extend perpendicularly to first fin and the second fin
Bearing of trend.
Optionally, in addition to：First fin and the dielectric layer of the second fin side wall are covered, first bonding pad is situated between
There is the first contact hole, the first contact hole bottom-exposed goes out the first fin top surface, and described second connects in matter layer
Connecing has the second contact hole in area's dielectric layer, the second contact hole bottom-exposed goes out the second fin top surface；It is described
First connector is located in first contact hole, and second connector is located in second contact hole.
Optionally, the dielectric layer also covers the 3rd dummy grid, the first dummy grid and the second dummy grid top and side
Wall surface.
Optionally, in addition to：On the device region doped region, between first fin on substrate and described
Isolation structure between two fins on substrate；3rd dummy grid is located on the isolation structure.
Optionally, there are Doped ions in the doped region of the device region, have in first fin first adulterate from
Son, there are the second Doped ions, first Doped ions, the second Doped ions and the Doped ions in second fin
Conduction type it is identical.
Optionally, in addition to：The first epitaxial layer at the top of first fin between the connector；Positioned at described
The second epitaxial layer at the top of second fin between the connector.
Accordingly, the present invention also provides a kind of forming method of semiconductor structure, including：Substrate, the substrate bag are provided
Include：Device region and the first bonding pad and the second bonding pad for being located at the device region both sides respectively, first bonding pad substrate
It is upper that there is the first fin, there is the second fin, first fin and the second fin parallel on the substrate of second bonding pad
Row, and the orientation for extending perpendicularly to first fin and the second fin of first fin；In the device
Doped region is formed in area, the first bonding pad and the second bonding pad substrate and in the first fin and the second fin；Be developed across in
The first connector on the atop part of first fin；It is developed across inserting in second on the atop part of second fin
Plug.
Optionally, the forming step of the substrate, the first fin and the second fin includes：Initial substrate is provided；Described
Graph layer is formed in initial substrate, the graph layer exposes the device region initial substrate surface and part described first connects
Meet area and the second bonding pad initial substrate surface；The initial substrate is performed etching using the graph layer as mask, forms lining
Bottom, the first fin on the substrate of first bonding pad and the second fin on the substrate of second bonding pad.
Optionally, the technique performed etching to the initial substrate is dry etch process.
Optionally, in addition to：The 3rd dummy grid is formed on the device region substrate.
Optionally, in addition to：The first dummy grid of first fin is developed across, described in the first dummy grid covering
First fin partial sidewall and top surface；The second dummy grid of second fin is developed across, second dummy grid covers
Cover the second fin partial sidewall and top surface.
Optionally, the step of forming the 3rd dummy grid, the first dummy grid and the second dummy grid includes：Form covering institute
State the first fin, the second fin side wall and top surface, and the grid layer of the device region doped region；The grid layer is entered
Row is graphical, the 3rd dummy grid formed on the device region doped region, across the first dummy grid of first fin,
Across the second dummy grid of second fin.
Optionally, the material of first dummy grid, the second dummy grid and the 3rd dummy grid is polysilicon, polycrystalline germanium or more
Crystal silicon germanium.
Optionally, the step of being mixed described in formation layer includes：The first Doped ions are injected in first fin, in institute
State and the second Doped ions are injected in the second fin；Injected by ion implantation technology in first fin first adulterate from
Son, and inject the second Doped ions in second fin.
Compared with prior art, technical scheme has advantages below：
In the semiconductor structure of the present invention, first fin and the second fin are arranged in parallel, and first fin
Extend perpendicularly to the orientation of first fin and the second fin.The semiconductor structure is in use, electric
When stream flows between the doped region in the first fin and substrate, the cross-sectional area for flowing through passage of electric current is larger, and electric current exists
When being flowed between the doped region in the second fin and substrate, the cross-sectional area for flowing through passage of electric current is also larger, therefore, described
The contact resistance between doped region in one fin and the second fin and the substrate is smaller, can reduce semiconductor structure generation
Heat, so as to reduce the self-heating effect of the semiconductor structure, and then semiconductor structure performance can be improved.
Further, there is the 3rd dummy grid, first bonding pad has across described the on the device region doped region
First dummy grid of one fin, second bonding pad have the second dummy grid across second fin.Described first is pseudo-
Grid and the second dummy grid can reduce the pit formed in the dielectric layer, so as to reduce remained in the pit
One connector and the second plug material, and then the insulating properties of the dielectric layer can be improved, improve semiconductor structure performance.
In the forming method of the semiconductor structure of the present invention, first fin and the second fin are arranged in parallel and described
The orientation for extending perpendicularly to first fin and the second fin of first fin, and form the process of doped region
In, the contact resistance between doped region in first fin, the second fin and the substrate is smaller, can reduce semiconductor
Heat caused by structure, so as to reduce the self-heating effect of the semiconductor structure, and then semiconductor structure performance can be improved.
Further, there is the 3rd dummy grid, first bonding pad has across described the on the device region doped region
First dummy grid of one fin, second bonding pad have the second dummy grid across second fin.Described in formation
During dielectric layer, first dummy grid and the second dummy grid can reduce the pit formed in the dielectric layer, so as to
The first connector formed in the pit and the second plug material can be reduced, and then the insulation of the dielectric layer can be improved
Property, improve semiconductor structure performance.
Brief description of the drawings
Fig. 1 and Fig. 2 is a kind of structural representation of semiconductor structure；
Fig. 3 to Figure 14 is the structural representation of each step of the embodiment of forming method one of semiconductor structure of the present invention.
Embodiment
Problems be present in semiconductor structure, such as：The resistance of semiconductor structure is excessive, semiconductor structure poor-performing.
In conjunction with a kind of resistive element, it is excessive to analyze the resistance of semiconductor structure, the reason for semiconductor structure poor-performing：
Fig. 1 and Fig. 2 is a kind of structural representation of resistive element.
Fig. 1 and Fig. 2 are refer to, Fig. 2 is sectional views of the Fig. 1 along line of cut 1-2, and the resistive element includes：Substrate 100；
Doped region 110 in the substrate 100, there are Doped ions in the doped region 110；It is located at the doped region respectively
Fin 101 on 110 both sides substrates 100, the projecting figure of the fins 101 of the both sides of doped region 110 on the substrate 100 it is short
Side is relative；Positioned at the epitaxial layer 120 of the top surface of fin 101；Cover (Fig. 1 of dielectric layer 131 of the side wall of fin 101
Not shown in), there is contact hole in the dielectric layer 131, the contact hole bottom-exposed goes out the top table of epitaxial layer 120
Face；Connector 130 in the contact hole.
Wherein, the Doped ions in the doped region 110 are used for the resistance for adjusting the doped region 110.The doped region
110 are connected by the fin 101 with the epitaxial layer 120 and connector 130, so as to realize the doped region 110 and external electrical
The electrical connection on road.
The resistive element in use, connects voltage on the connector 130, and electric current is from the doped region 110
The fin 101 of side flows to opposite side fin 101 by the doped region 110.Due to the fin of the both sides of doped region 110
The short side of 101 projecting figure on the substrate 100 is relative, causes the fin 101 and the contact area of doped region 110 (figure
The middle region of sectioned coil 3) electric current flow through passage cross-sectional area it is smaller, so as to cause the fin 101 and the doped region
The resistance of 110 contact areas is larger, the fin 101 is produced self-heating effect with the contact area of doped region 110,
Influence the performance of the resistive element.
To solve the technical problem, the invention provides a kind of semiconductor structure, including：Substrate, the substrate include：
Device region and the first bonding pad and the second bonding pad for being located at the device region both sides respectively；Positioned at first bonding pad substrate
On the first fin and the second fin on the substrate of second bonding pad, first fin and the second fin
Bearing of trend is parallel, and the bearing of trend of first fin is vertical with the orientation of first fin and the second fin；
Doped region in the device region, the first bonding pad and the second bonding pad substrate；Across first fin and the second fin
The connector in portion.
Wherein, first fin is parallel with the bearing of trend of the second fin, and the bearing of trend of first fin with
The orientation of first fin and the second fin is vertical.In use, electric current is in the first fin for the semiconductor structure
When being flowed between portion and doped region, the cross-sectional area for flowing through passage of electric current is larger, and electric current the second fin and doped region it
Between when flowing, the cross-sectional area for flowing through passage of electric current is also larger, therefore, first fin and the second fin and the doping
Contact resistance between area is smaller, can reduce heat caused by semiconductor structure, so as to reduce the semiconductor structure from
Heating effect, and then semiconductor structure performance can be improved.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 3 to Figure 14 is the structural representation of each step of the embodiment of forming method one of semiconductor structure of the present invention.
Substrate is provided, the substrate includes：Device region and respectively positioned at the first bonding pad of the device region both sides and the
Two bonding pads, there is the first fin on the substrate of first bonding pad, there is the second fin, institute on the substrate of second bonding pad
State the first fin and the second fin is arranged in parallel, and first fin extends perpendicularly to first fin and second
The orientation of fin.
In the present embodiment, the forming method of the substrate, the first fin and the second fin is as shown in Figure 3 and Figure 4.
It refer to Fig. 3, there is provided initial substrate 203, the initial substrate 203 include：Device region A and it is located at the device respectively
The the first bonding pad B1 and the second bonding pad B2 of part area A both sides.
In the present embodiment, the device region A is used to be subsequently formed doped region, the first bonding pad B1 and the second bonding pad
B2 is used for the electrical connection for realizing doped region and external circuit.
In the present embodiment, the material of the initial substrate 203 is silicon.In other embodiments, the material of the initial substrate
Material can also be germanium or SiGe.
Graph layer is formed in the initial substrate 203, the graph layer exposes the device region A initial substrates 203
And part the first bonding pad B1 and the surface of the second bonding pad B2 initial substrates 203.
The graph layer is used to define the first fin being subsequently formed, the positions and dimensions of the second fin.
In the present embodiment, the material of the graph layer is silicon nitride.In other embodiments, the material of the graph layer is also
It can be silicon oxynitride.
Fig. 4 is refer to, the initial substrate 203 is performed etching using the graph layer as mask, forms substrate 200, position
In the first fin 201 on the first bonding pad B1 substrates 200 and on the second bonding pad B2 substrates 200
Two fins 202, first fin 201 and the second fin 202 are arranged in parallel, and the bearing of trend of first fin 201 hangs down
Directly in the orientation of the fin 202 of the first fin 201 and second.
The fin 202 of first fin 201 and second is used for the connection for realizing the doped region and external circuit that are subsequently formed.
The bearing of trend of first fin 201 is the long side direction (Y-direction) of first fin 201；Described first
The orientation of fin 201 and second fin 202 is the company at the center of the first fin 201 and the center of the second fin 202
Line direction (X-direction).
In the present embodiment, the initial substrate 203 is performed etching by dry etching.Dry etching has each to different
Property, and there is good profile control, the first fin 201 and the second fin 202 and substrate 200 of formation have well vertical
Property.
In the present embodiment, the material of the substrate 200, the first fin 201 and the second fin 202 is silicon.In other implementations
In example, the material of the substrate, the first fin and the second fin can also be germanium or SiGe.
Fig. 5 and Fig. 6 are refer to, Fig. 6 is sectional views of the Fig. 5 along line of cut 21-22, in the device region A, the first bonding pad
Doped region 210 is formed in B1 and the second bonding pad B2 substrates 200 and in the first fin 201 and the second fin 202.
First fin 201 is arranged in parallel with the second fin 202, and the bearing of trend of first fin 201 hangs down
Directly in the orientation of the fin 202 of the first fin 201 and second.In use, electric current exists the semiconductor structure
Between doped region 210 in first fin 201 and substrate 200, and the first fin and the doped region 210 in substrate 200
Between flow during, the cross-sectional area that electric current flows through passage is larger, so as to reduce the first fin 201 and substrate 200
In doped region 210 between contact resistance, and reduce connecing between the doped region 210 in the second fin 202 and substrate 200
Get an electric shock and hinder, so as to reduce the first fin 201 and the doped region 210 in substrate 200, the second fin 202 and the doping in substrate 200
The self-heating effect of the contact area of area 210, and then improve and form semiconductor structure performance.
There are Doped ions, the Doped ions are used to adjust the electricity for forming semiconductor structure in the doped region 210
Resistance.
In the present embodiment, the doped region 210 is located at the device region A, the first bonding pad A1 and the second bonding pad B2 linings
In bottom 200.
In the present embodiment, include in the substrate 200 the step of formation doped region 210：By ion implanting described
Doped ions are injected in substrate 200, form the doped region 210.
In the present embodiment, formed doped region 210 the step of also include：By the ion implanting in first fin
The first Doped ions are injected in 201；Second Doped ions are injected in second fin 202 by the ion implanting.
In the present embodiment, first Doped ions, the second Doped ions are identical with the conduction type of the Doped ions.
Specifically, first Doped ions, the second Doped ions and the Doped ions are boron ion.In other embodiments, institute
It can also be phosphonium ion or arsenic ion to state the first Doped ions, the second Doped ions and the Doped ions.
Fig. 7 is refer to, is formed after doped region 210, in addition to：Connect in the device region A, the first bonding pad B1, second
Connect formation isolation structure 220, the isolation structure 220 on area's B2 substrates 200 and cover the fin of the first fin 201 and second
202 partial sidewalls.
The isolation structure 220 is used between realizing the first fin 201, the electric isolution between the second fin 202.
In the present embodiment, the material of the isolation structure 220 is silica.
In the present embodiment, the isolation structure 220 is formed by fluid chemistry gas-phase deposition.
Fig. 8 is refer to, is formed after isolation structure 220, the 3rd pseudo- grid are formed on the device region A isolation structures 220
Pole 230；It is developed across the first dummy grid 231 of first fin 201 and the second pseudo- grid across second fin 202
Pole 232.
During the dielectric layer is subsequently formed, the 3rd dummy grid 230, first dummy grid 231 and
Two dummy grids 232 can reduce the pit formed in the dielectric layer, so as to reduce formed in the pit first
Connector and the second plug material, and then the insulating properties of the dielectric layer can be improved, improve semiconductor structure performance.
In the present embodiment, the material of the 3rd dummy grid 230, the first dummy grid 231 and the second dummy grid 232 is polycrystalline
Silicon.In other embodiments, the material of the 3rd dummy grid, the first dummy grid and the second dummy grid can also be polycrystalline germanium or
Polycrystalline silicon germanium.
In the present embodiment, the dummy grid 232 of the first dummy grid 231 and second extends perpendicularly to first fin
201 and second fin 202 bearing of trend.
In the present embodiment, the 3rd dummy grid 230 extends perpendicularly to the fin of the first fin 201 and second
202 bearing of trend.In other embodiments, the 3rd dummy grid bearing of trend can also parallel to first fin and
The bearing of trend of second fin.
In the present embodiment, the 3rd dummy grid 230 is located on the isolation structure 220.
In the present embodiment, the step of forming the 3rd dummy grid 230, the first dummy grid 231 and the second dummy grid 232, wraps
Include：Formed and cover the first fin 201, the side wall of the second fin 202 and the top surface, and the device region A doped regions 220
Grid layer；The grid layer is patterned, the 3rd dummy grid formed on the device region A doped regions 220
230, across the first dummy grid 231 of first fin 201, across the second dummy grid 232 of second fin 202.
In the present embodiment, the step of being patterned to the grid layer, includes：Formed on the grid layer graphical
Mask layer, the grid layer is performed etching using the patterned mask layer as mask, forms the 3rd dummy grid
230th, the first dummy grid 231 and the second dummy grid 232.
In the present embodiment, the technique performed etching to the grid layer includes：Dry etching.In other embodiments, also
The grid layer can be performed etching by wet-etching technology.
It should be noted that in other embodiments, the forming method can not also include：Form the described first pseudo- grid
The step of pole, the second dummy grid and three dummy grids；Or the forming method only step including forming the 3rd dummy grid
Suddenly, the step of not including forming first dummy grid and the second dummy grid；Or the forming method is only included described in formation
The step of first dummy grid and the second dummy grid, the step of not including forming three dummy grid.
Fig. 9 and Figure 10 are refer to, Figure 10 is sectional views of the Fig. 9 along line of cut 23-24, in 231 liang of first dummy grid
The first epitaxial layer 241 is formed in first fin 201 of side；Formed in the second fin 202 of the both sides of the second dummy grid 232
Second epitaxial layer 242.
First epitaxial layer 241 is used for the electrical connection for realizing the first connector and first fin 201 being subsequently formed；
Second epitaxial layer 242 is used for the electrical connection for realizing the second connector and second fin 202 being subsequently formed.
In the present embodiment, the material of the epitaxial layer 242 of the first epitaxial layer 241 and second is SiGe.
In the present embodiment, the epitaxial layer 242 of the first epitaxial layer 241 and second is formed by epitaxial growth technology, and
During the epitaxial growth, doping in situ is carried out to the epitaxial layer 242 of the first epitaxial layer 241 and second, described
Extension ion is mixed in one epitaxial layer 241 and the second epitaxial layer 242.
The extension ion is identical with the conduction type of the Doped ions.Specifically, in the present embodiment, the extension from
Son is boron ion, and in other embodiments, the extension ion can also be phosphonium ion or arsenic ion.
It refer to Figure 11, form the dielectric layer 250 for covering the side wall of 201 and second fin of the first fin 202, described the
There is the first contact hole 251, the bottom-exposed of the first contact hole 251 goes out first fin in one bonding pad B1 dielectric layers 250
The top surface of portion 201, there is the second contact hole 252, second contact hole 252 in the second bonding pad B2 dielectric layers 250
Bottom-exposed goes out the top surface of the second fin 202.
In the present embodiment, the dielectric layer 250 is used to realize the fin 202 of the first fin 201 and second and external electrical
The electric insulation on road.
In the present embodiment, the dielectric layer 250 also covers the separation layer 220 of the device region A.
In the present embodiment, the step of forming dielectric layer 250, includes：Initial be situated between is formed on the isolation structure 220
Matter layer, the initial medium layer surface are higher than the top surface of 231 and second dummy grid of the first dummy grid 232；To described first
Beginning dielectric layer carries out planarization process；After the planarization process, to the epitaxial layer 242 of the first epitaxial layer 241 and second
On initial medium layer perform etching to exposing the top surface of 241 and second epitaxial layer of the first epitaxial layer 242.
It should be noted that due to there is the 3rd dummy grid 230, first fin on the device region A doped regions 210
There is the first dummy grid 231 on 201 tops, there is the second dummy grid 232 on the top of the second fin 202, described in progress
During planarization process, the 3rd dummy grid 230, the first dummy grid 231 and the second dummy grid 232 can reduce described
The planarization rate of initial medium layer, so as to reduce the pit in the dielectric layer 250.
In the present embodiment, planarization process is carried out to the initial medium layer by chemical mechanical milling tech.
In the present embodiment, initial medium layer is performed etching by dry etching.In other embodiments, can also pass through
Wet etching performs etching to the initial medium layer.
It refer to Figure 12 to Figure 14, Figure 13 is sectional views of the Figure 12 along line of cut 25-26, and Figure 14 is Figure 12 along line of cut
27-28 sectional view, it is developed across in the first connector 261 on the atop part of the first fin 201；It is developed across in described
The second connector 262 on the atop part of second fin 202.
It should be noted that because the pit in the dielectric layer 250 is less, first connector 261 and the are being formed
During two connectors 262, the first connector 261 and the material of the second connector 261 in the pit are also less, so as to be not easy shadow
The insulating properties of the dielectric layer 250 is rung, therefore, the forming method can improve formed semiconductor structure performance.
In the present embodiment, the material of the connector 261 of the first connector 261 and second is tungsten.In other embodiments, it is described
The material of first connector and the second connector can also be copper.
In the present embodiment, the connector 261 of the first connector 261 and second is formed by chemical vapor deposition method.
To sum up, in the forming method of the semiconductor structure of the present embodiment, first fin and the second fin are arranged in parallel,
And the orientation for extending perpendicularly to first fin and the second fin of first fin.The semiconductor structure
In use, when being flowed between doped region of the electric current in the first fin and substrate, the cross section for flowing through passage of electric current
Product is larger, and when being flowed between doped region of the electric current in the second fin and substrate, the cross-sectional area for flowing through passage of electric current
Larger, therefore, the contact resistance between doped region in first fin and the second fin and the substrate is smaller, can drop
Heat caused by low semiconductor structure, so as to reduce the self-heating effect of the semiconductor structure, and then semiconductor can be improved
Structural behaviour.
Further, there is the 3rd dummy grid, first bonding pad has across described the on the device region doped region
First dummy grid of one fin, second bonding pad have the second dummy grid across second fin.Described first is pseudo-
Grid and the second dummy grid can reduce the pit formed in the dielectric layer, so as to reduce remained in the pit
One connector and the second plug material, and then the insulating properties of the dielectric layer can be improved, improve semiconductor structure performance.
With continued reference to Figure 12 to Figure 14, the present invention, which also provides a kind of semiconductor structure, to be included：Substrate 200, the substrate 200
Including：Device region A and the first bonding pad B1 and the second bonding pad B2 for being located at the device region A both sides respectively；Positioned at described
The first fin 201 on one bonding pad B1 substrates 200 and the second fin on the second bonding pad B2 substrates 200
202, first fin 201 is arranged in parallel with the second fin 202, and first fin 201 extends perpendicularly to
The orientation of the fin 202 of first fin 201 and second；Connected positioned at the device region A, the first bonding pad B1 and second
Doped region 210 in area's B2 substrates 200 and in the first fin 201 and the second fin 202；It is across first fin 201
Atop part on the first connector 261, the second connector 262 being across on the atop part of second fin 202.
In the present embodiment, the material of the substrate 200, the first fin 201 and the second fin 202 is silicon.In other implementations
In example, the material of the substrate, the first fin and the second fin can also be germanium or SiGe.
First fin 201 is arranged in parallel with the second fin 202, and the bearing of trend of first fin 201 hangs down
Directly in the orientation of the fin 202 of the first fin 201 and second.In use, electric current exists the semiconductor structure
Between first fin 201 and doped region 210, and flowed between the first fin and doped region 210, electric current flows through passage
Cross-sectional area is larger, so as to reduce the first fin 201 and the doped region 210 in substrate 200, the first fin and substrate 200
In doped region 210 between contact resistance, so as to reduce the first fin 201 and the doped region 210 in substrate 200, the first fin
Portion and the self-heating effect of the contact area energy of doped region 210 in substrate 200, and then improve and form semiconductor structure
Energy.
There are Doped ions in the device region A doped regions 210, the resistance of semiconductor structure is formed for adjusting.
In the present embodiment, the doped region 210 is located at the device region A, the first bonding pad B1 and the second bonding pad B2 linings
In bottom 200, the first fin 201 and the second fin 202.
In the present embodiment, there are the first Doped ions in first fin 201, have the in second fin 202
Two Doped ions.
First Doped ions are used for the resistance for reducing first fin 201；Second Doped ions are used to subtract
The resistance of small second fin 202.
In the present embodiment, first Doped ions, the second Doped ions are identical with the conduction type of the Doped ions.
Specifically, first Doped ions, the second Doped ions and the Doped ions are boron ion.In other embodiments, institute
It can also be phosphonium ion or arsenic ion to state the first Doped ions, the second Doped ions and the Doped ions.
The semiconductor structure also includes：It is positioned over the device region A doped regions 210, the partial sidewall of the first fin 201
With the isolation structure 220 of the partial sidewall of the second fin 202.
The isolation structure 220 is used between realizing the first fin 201, the electric isolution between the second fin 202.
The semiconductor structure also includes：The 3rd dummy grid on the device region A doped regions 210；Across described
First dummy grid 231 of the first fin 201, first dummy grid 231 cover the partial sidewall of the first fin 201 and top
Surface；Across the second dummy grid 232 of second fin 202, second dummy grid 232 covers second fin 202
Partial sidewall and top surface.
3rd dummy grid 230, the dummy grid 232 of first dummy grid 231 and second can reduce the dielectric layer
The pit of middle formation, so as to reduce the first connector formed in the pit and the second plug material, and then it can carry
The insulating properties of the high dielectric layer, improves semiconductor structure performance.
In the present embodiment, the 3rd dummy grid 230 is located on the isolation structure 220.
In the present embodiment, the material of the 3rd dummy grid 230, the first dummy grid 231 and the second dummy grid 232 is polycrystalline
Silicon.In other embodiments, the material of the 3rd dummy grid, the first dummy grid and the second dummy grid can also be polycrystalline germanium or
Polycrystalline silicon germanium.
In the present embodiment, the dummy grid 232 of the first dummy grid 231 and second extends perpendicularly to first fin
201 and second fin 202 bearing of trend.
In the present embodiment, the 3rd dummy grid 230 extends perpendicularly to the fin of the first fin 201 and second
202 bearing of trend.In other embodiments, the 3rd dummy grid bearing of trend can also parallel to first fin and
The bearing of trend of second fin.
It should be noted that in other embodiments, the semiconductor structure can not also include the first dummy grid, second
Dummy grid and the 3rd dummy grid；Or the semiconductor structure only includes the 3rd dummy grid, not including the first dummy grid and second
Dummy grid；Or the semiconductor structure only includes the first dummy grid and the second dummy grid, not including the 3rd dummy grid.
The semiconductor structure also includes：The first extension in first fin of both sides 201 of the first dummy grid 231
Layer 241；The second epitaxial layer 242 in second fin of both sides 202 of the second dummy grid 232.
First epitaxial layer 241 is used for the electrical connection for realizing the first connector and first fin 201 being subsequently formed；
Second epitaxial layer 242 is used for the electrical connection for realizing the second connector and second fin 202 being subsequently formed.
In the present embodiment, the material of the epitaxial layer 242 of the first epitaxial layer 241 and second is SiGe.
In the present embodiment, there is extension ion in the epitaxial layer 242 of the first epitaxial layer 241 and second.
The extension ion is identical with the conduction type of the Doped ions.Specifically, in the present embodiment, the extension from
Son is boron ion, and in other embodiments, the extension ion can also be phosphonium ion or arsenic ion.
The semiconductor structure also includes：The dielectric layer 250 of the side wall of 201 and second fin of the first fin 202 is covered,
There is the first contact hole, the first contact hole bottom-exposed goes out described first in the dielectric layer 250 of the first bonding pad A1
The top surface of fin 201, there is the second contact hole, the second contact hole bottom in the dielectric layer 250 of the second bonding pad B2
Portion exposes the top surface of the second fin 202；First connector 251 is located in first contact hole, and described second
Connector 252 is located in second contact hole.
In the present embodiment, the dielectric layer 250 is used to realize the fin 202 of the first fin 201 and second and external electrical
The electric insulation on road.
In the present embodiment, the dielectric layer 250 also covers the device region A separation layers 220.
Due to having the 3rd dummy grid 230 on the device region A doped regions 210, have on the top of the first fin 201
First dummy grid 231, second fin 202 have the second dummy grid 232 on top, are not easy shape in the dielectric layer 250
Into pit.
Because the pit in the dielectric layer 250 is less, the first connector 261 and the material of the second connector 262 in the pit
Material is also less, and so as to be not easy to influence the insulating properties of the dielectric layer 250, therefore, the forming method can improve to be formed
Semiconductor structure performance.
In the present embodiment, the material of the connector 262 of the first connector 261 and second is tungsten.In other embodiments, it is described
The material of first connector and the second connector can also be copper.
To sum up, in the semiconductor structure of the present embodiment, first fin and the second fin are arranged in parallel, and described first
The orientation for extending perpendicularly to first fin and the second fin of fin, and during formation doped region, institute
The contact resistance stated between the doped region in the first fin, the second fin and the substrate is smaller, can reduce semiconductor structure
Caused heat, so as to reduce the self-heating effect of the semiconductor structure, and then semiconductor structure performance can be improved.
Further, there is the 3rd dummy grid, first bonding pad has across described the on the device region doped region
First dummy grid of one fin, second bonding pad have the second dummy grid across second fin.Described in formation
During dielectric layer, first dummy grid and the second dummy grid can reduce the pit formed in the dielectric layer, so as to
The first connector formed in the pit and the second plug material can be reduced, and then the insulation of the dielectric layer can be improved
Property, improve semiconductor structure performance.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (20)
- A kind of 1. semiconductor structure, it is characterised in that including：Substrate, the substrate include：Device region and the first bonding pad and the second bonding pad for being located at the device region both sides respectively；The first fin on the substrate of first bonding pad and the second fin on the substrate of second bonding pad Portion, first fin and the second fin are arranged in parallel, and first fin and the second fin extend perpendicularly to institute State the orientation of the first fin and the second fin；Mixing in the device region, the first bonding pad and the second bonding pad substrate and in the first fin and the second fin Miscellaneous area；The first connector being across on the atop part of first fin；The second connector being across on the atop part of second fin.
- 2. semiconductor structure as claimed in claim 1, it is characterised in that also include：On the device region doped region 3rd dummy grid.
- 3. semiconductor structure as claimed in claim 1 or 2, it is characterised in that also include：Across the first of first fin Dummy grid, first dummy grid cover the first fin partial sidewall and top surface；Across the of second fin Two dummy grids, second dummy grid cover the second fin partial sidewall and top surface.
- 4. semiconductor structure as claimed in claim 2, it is characterised in that the material of the 3rd dummy grid is polysilicon, more Brilliant germanium or polycrystalline silicon germanium.
- 5. semiconductor structure as claimed in claim 2, it is characterised in that the bearing of trend of the 3rd dummy grid is vertical or flat Row is in first fin and the bearing of trend of the second fin.
- 6. semiconductor structure as claimed in claim 3, it is characterised in that the material of first dummy grid and the second dummy grid For polysilicon, polycrystalline germanium or polycrystalline silicon germanium.
- 7. semiconductor structure as claimed in claim 3, it is characterised in that first dummy grid and the second dummy grid extension side To the bearing of trend perpendicular to first fin and the second fin.
- 8. semiconductor structure as claimed in claim 3, it is characterised in that also include：Cover first fin and the second fin The dielectric layer of portion's side wall, there is the first contact hole in the dielectric layer of first bonding pad, the first contact hole bottom-exposed goes out The first fin top surface, there is the second contact hole, the second contact hole bottom in the dielectric layer of second bonding pad Expose the second fin top surface；First connector is located in first contact hole, and second connector is located at In second contact hole.
- 9. semiconductor structure as claimed in claim 8, it is characterised in that the dielectric layer also cover the 3rd dummy grid, First dummy grid and the second dummy grid top and sidewall surfaces.
- 10. semiconductor structure as claimed in claim 2, it is characterised in that also include：On the device region doped region, Isolation structure between first fin on substrate and between second fin on substrate；3rd dummy grid is located on the isolation structure.
- 11. semiconductor structure as claimed in claim 1, it is characterised in that in the doped region of the device region have doping from Son, there are the first Doped ions in first fin, there are the second Doped ions in second fin；First Doped ions, the second Doped ions are identical with the conduction type of the Doped ions.
- 12. semiconductor structure as claimed in claim 1, it is characterised in that also include：Positioned at first fin top and institute State the first epitaxial layer between connector；The second epitaxial layer at the top of second fin between the connector.
- A kind of 13. forming method of semiconductor structure, it is characterised in that including：Substrate is provided, the substrate includes：Device region and the first bonding pad and the second company for being located at the device region both sides respectively Area is met, there is the first fin on the substrate of first bonding pad, there is the second fin on the substrate of second bonding pad, described One fin and the second fin are arranged in parallel, and first fin extends perpendicularly to first fin and the second fin Orientation；Formed in the device region, the first bonding pad and the second bonding pad substrate and in the first fin and the second fin and mixed Miscellaneous area；It is developed across in the first connector on the atop part of first fin；It is developed across in the second connector on the atop part of second fin.
- 14. the forming method of semiconductor structure as claimed in claim 13, it is characterised in that the substrate, the first fin and The forming step of second fin includes：Initial substrate is provided；Graph layer is formed in the initial substrate, the graph layer exposes the device region initial substrate surface and part First bonding pad and the second bonding pad initial substrate surface；The initial substrate is performed etching using the graph layer as mask, substrate is formed, positioned at first bonding pad substrate On the first fin and the second fin on the substrate of second bonding pad.
- 15. the forming method of semiconductor structure as claimed in claim 14, it is characterised in that carved to the initial substrate The technique of erosion is dry etch process.
- 16. the forming method of semiconductor structure as claimed in claim 13, it is characterised in that also include：In the device region The 3rd dummy grid is formed on substrate.
- 17. the forming method of the semiconductor structure as described in claim 13 or 16, it is characterised in that also include：It is developed across covering the first fin partial sidewall in the first dummy grid of first fin, first dummy grid And top surface；Be developed across in the second dummy grid for stating the second fin, second dummy grid covers the second fin partial sidewall And top surface.
- 18. the forming method of semiconductor structure as claimed in claim 17, it is characterised in that formation the 3rd dummy grid, The step of first dummy grid and the second dummy grid, includes：Formed and cover the first fin, the second fin side wall and the top surface, and the grid layer of the device region doped region；The grid layer is patterned, forms the 3rd dummy grid on the device region doped region, across described the First dummy grid of one fin, across the second dummy grid of second fin.
- 19. the forming method of semiconductor structure as claimed in claim 17, it is characterised in that first dummy grid, second The material of dummy grid and the 3rd dummy grid is polysilicon, polycrystalline germanium or polycrystalline silicon germanium.
- 20. the forming method of semiconductor structure as claimed in claim 13, it is characterised in that the step of being mixed described in formation layer Including：The first Doped ions are injected in first fin, inject the second Doped ions in second fin；First Doped ions are injected in first fin by ion implantation technology, and is injected in second fin Two Doped ions.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103283016A (en) * | 2011-01-06 | 2013-09-04 | 国际商业机器公司 | Structure and method to fabricate resistor on fin FET processes |
| CN104160511A (en) * | 2011-12-30 | 2014-11-19 | 英特尔公司 | Wrap-around trench contact structure and methods of fabrication |
| US20160079241A1 (en) * | 2014-09-12 | 2016-03-17 | Samsung Electronics Co., Ltd. | Integrated circuit device including blocking insulating layer |
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2016
- 2016-08-29 CN CN201610756336.XA patent/CN107799522B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103283016A (en) * | 2011-01-06 | 2013-09-04 | 国际商业机器公司 | Structure and method to fabricate resistor on fin FET processes |
| CN104160511A (en) * | 2011-12-30 | 2014-11-19 | 英特尔公司 | Wrap-around trench contact structure and methods of fabrication |
| US20160079241A1 (en) * | 2014-09-12 | 2016-03-17 | Samsung Electronics Co., Ltd. | Integrated circuit device including blocking insulating layer |
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