CN107799522B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN107799522B CN107799522B CN201610756336.XA CN201610756336A CN107799522B CN 107799522 B CN107799522 B CN 107799522B CN 201610756336 A CN201610756336 A CN 201610756336A CN 107799522 B CN107799522 B CN 107799522B
- Authority
- CN
- China
- Prior art keywords
- fin
- dummy gate
- fin portion
- semiconductor structure
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
Abstract
The invention provides a semiconductor structure and a forming method thereof, wherein the structure comprises: a substrate, the substrate comprising: the device comprises a device area, a first connecting area and a second connecting area which are respectively positioned at two sides of the device area; the first fin portion and the second fin portion are arranged in parallel, and the extending direction of the first fin portion and the extending direction of the second fin portion are perpendicular to the arrangement direction of the first fin portion and the second fin portion; doped regions in the device region, the first and second connection region substrates, and the first and second fins; a first plug spanning a portion of the top of the first fin; a second plug spanning a portion of the top of the second fin. When the semiconductor structure is used, the cross section area of a current flowing through a channel is larger, so that the contact resistance between the first fin part and the doped region and the contact resistance between the second fin part and the doped region are smaller, and the performance of the semiconductor structure can be improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the increase of the integration level of semiconductor devices, the critical dimension of transistors is continuously reduced, and the reduction of the critical dimension means that a larger number of transistors can be arranged on a chip, thereby improving the performance of the devices. The resistive element is an important element on the chip.
The resistive element can be formed with a semiconductor layer including a resistively doped region. The resistance doped region is provided with doping ions, and the resistance value of the resistance element can be adjusted by adjusting the concentration of the doping ions. And both ends of the doped region can be electrically connected with an external circuit through the electric interconnection structure.
The contact resistance exists between the doped region and the electrical interconnection structure, if the contact resistance is too large, the resistance element is easy to generate more heat, so that a self-heating effect is caused, and in addition, the resistance value of the resistance element is easy to be too high due to the too large contact resistance, so that the performance of the resistance element is easy to be influenced.
However, the contact resistance of the conventional resistance element is large, and the performance of the resistance element is poor.
Disclosure of Invention
The invention solves the problem of providing a semiconductor structure and a forming method thereof, which can improve the performance of the semiconductor structure.
To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising: the device comprises a device area, a first connecting area and a second connecting area which are respectively positioned at two sides of the device area; the first fin portion and the second fin portion are arranged in parallel, and the extending direction of the first fin portion and the extending direction of the second fin portion are perpendicular to the arrangement direction of the first fin portion and the second fin portion; doped regions in the device region, the first and second connection region substrates, and the first and second fins; a first plug spanning a portion of a top of the first fin; a second plug spanning a portion of a top of the second fin.
Optionally, the method further includes: and the third dummy gate is positioned on the doped region of the device region.
Optionally, the method further includes: a first dummy gate crossing the first fin portion, the first dummy gate covering a portion of a sidewall and a top surface of the first fin portion; and the second dummy gate spans the second fin part and covers partial side wall and the top surface of the second fin part.
Optionally, the third dummy gate is made of polysilicon, poly-germanium, or poly-silicon-germanium.
Optionally, an extending direction of the third dummy gate is perpendicular to or parallel to extending directions of the first fin portion and the second fin portion.
Optionally, the first dummy gate and the second dummy gate are made of polysilicon, poly-germanium, or poly-silicon-germanium.
Optionally, the extending directions of the first dummy gate and the second dummy gate are perpendicular to the extending directions of the first fin portion and the second fin portion.
Optionally, the method further includes: the dielectric layer covers the side walls of the first fin portion and the second fin portion, a first contact hole is formed in the first connection region dielectric layer, the bottom of the first contact hole is exposed out of the top surface of the first fin portion, a second contact hole is formed in the second connection region dielectric layer, and the bottom of the second contact hole is exposed out of the top surface of the second fin portion; the first plug is located in the first contact hole, and the second plug is located in the second contact hole.
Optionally, the dielectric layer further covers the top and sidewall surfaces of the third dummy gate, the first dummy gate and the second dummy gate.
Optionally, the method further includes: isolation structures located on the device region doped region, on the substrate between the first fin portions and on the substrate between the second fin portions; the third dummy gate is located on the isolation structure.
Optionally, doped ions are provided in the doped region of the device region, first doped ions are provided in the first fin portion, second doped ions are provided in the second fin portion, and the conductivity types of the first doped ions, the second doped ions, and the doped ions are the same.
Optionally, the method further includes: a first epitaxial layer located between the top of the first fin and the plug; a second epitaxial layer between the top of the second fin and the plug.
Correspondingly, the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, the substrate comprising: the device comprises a device area, a first connection area and a second connection area, wherein the first connection area and the second connection area are respectively positioned on two sides of the device area; forming doped regions in the device region, the first connection region and the second connection region substrate, and the first fin portion and the second fin portion; forming a first plug that spans across a portion of a top of the first fin; forming a second plug that spans across a portion of a top of the second fin.
Optionally, the forming steps of the substrate, the first fin portion and the second fin portion include: providing an initial substrate; forming a pattern layer on the initial substrate, wherein the pattern layer exposes the surface of the initial substrate of the device area and parts of the surfaces of the initial substrates of the first connection area and the second connection area; and etching the initial substrate by taking the pattern layer as a mask to form a substrate, a first fin part positioned on the first connection region substrate and a second fin part positioned on the second connection region substrate.
Optionally, the process of etching the initial substrate is a dry etching process.
Optionally, the method further includes: and forming a third dummy gate on the device region substrate.
Optionally, the method further includes: forming a first dummy gate crossing the first fin portion, wherein the first dummy gate covers partial side walls and the top surface of the first fin portion; and forming a second dummy gate crossing the second fin portion, wherein the second dummy gate covers partial side wall and the top surface of the second fin portion.
Optionally, the step of forming the third dummy gate, the first dummy gate, and the second dummy gate includes: forming a gate layer covering the first fin part, the side wall and the top surface of the second fin part and the doped region of the device region; and patterning the gate layer to form a third dummy gate on the device region doping region, a first dummy gate crossing the first fin portion, and a second dummy gate crossing the second fin portion.
Optionally, the first dummy gate, the second dummy gate, and the third dummy gate are made of polysilicon, poly-germanium, or poly-silicon-germanium.
Optionally, the step of forming the doped layer includes: implanting first doping ions in the first fin portion and second doping ions in the second fin portion; implanting first doping ions in the first fin portion and second doping ions in the second fin portion by an ion implantation process.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the semiconductor structure of the invention, the first fin portion and the second fin portion are arranged in parallel, and the extending direction of the first fin portion is perpendicular to the arrangement direction of the first fin portion and the second fin portion. In the use process of the semiconductor structure, when current flows between the first fin part and the doped region in the substrate, the cross-sectional area of the current flowing through the channel is larger, and when current flows between the second fin part and the doped region in the substrate, the cross-sectional area of the current flowing through the channel is also larger, so that the contact resistance between the first fin part and the doped region in the substrate and the contact resistance between the second fin part and the doped region in the substrate are smaller, the heat generated by the semiconductor structure can be reduced, the self-heating effect of the semiconductor structure is reduced, and the performance of the semiconductor structure can be improved.
Further, a third dummy gate is arranged on the device region doping region, the first connection region is provided with a first dummy gate crossing the first fin portion, and the second connection region is provided with a second dummy gate crossing the second fin portion. The first dummy gate and the second dummy gate can reduce pits formed in the dielectric layer, so that residual first plug and second plug materials in the pits can be reduced, the insulativity of the dielectric layer can be improved, and the performance of a semiconductor structure can be improved.
In the method for forming the semiconductor structure, the first fin portion and the second fin portion are arranged in parallel, the extending direction of the first fin portion is perpendicular to the arrangement direction of the first fin portion and the second fin portion, and in the process of forming the doped region, the contact resistance among the first fin portion, the second fin portion and the doped region in the substrate is small, so that the heat generated by the semiconductor structure can be reduced, the self-heating effect of the semiconductor structure is reduced, and the performance of the semiconductor structure can be improved.
Further, a third dummy gate is arranged on the device region doping region, the first connection region is provided with a first dummy gate crossing the first fin portion, and the second connection region is provided with a second dummy gate crossing the second fin portion. In the process of forming the dielectric layer, the pits formed in the dielectric layer can be reduced by the first dummy gate and the second dummy gate, so that the materials of the first plug and the second plug formed in the pits can be reduced, the insulativity of the dielectric layer can be improved, and the performance of a semiconductor structure can be improved.
Drawings
FIGS. 1 and 2 are schematic structural diagrams of a semiconductor structure;
fig. 3 to 14 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
Semiconductor structures have a number of problems, such as: the resistance of the semiconductor structure is too high and the performance of the semiconductor structure is poor.
Now, a resistance element is combined to analyze the reason that the resistance of the semiconductor structure is too large and the performance of the semiconductor structure is poor:
fig. 1 and 2 are schematic structural views of a resistance element.
Referring to fig. 1 and 2, fig. 2 is a cross-sectional view of fig. 1 taken along a cutting line 1-2, the resistive element including: a substrate 100; a doped region 110 in the substrate 100, the doped region 110 having dopant ions therein; the fin parts 101 are respectively positioned on the substrate 100 at two sides of the doped region 110, and the short sides of the projection pattern of the fin parts 101 at two sides of the doped region 110 on the substrate 100 are opposite; an epitaxial layer 120 on a top surface of the fin 101; a dielectric layer 131 (not shown in fig. 1) covering the sidewalls of the fin 101, the dielectric layer 131 having a contact hole therein, the bottom of the contact hole exposing the top surface of the epitaxial layer 120; a plug 130 in the contact hole.
Wherein the doped ions in the doped region 110 are used to adjust the resistance of the doped region 110. The doped region 110 is connected to the epitaxial layer 120 and the plug 130 through the fin 101, so that the doped region 110 is electrically connected to an external circuit.
In the use process of the resistor element, a voltage is connected to the plug 130, and a current flows from the fin 101 on one side of the doped region 110 to the fin 101 on the other side through the doped region 110. Because the short sides of the projected patterns of the fin portions 101 on the two sides of the doped region 110 on the substrate 100 are opposite, the cross-sectional area of the current flowing through the channel in the contact region (the region of the cutting coil 3 in the figure) of the fin portion 101 and the doped region 110 is smaller, so that the resistance of the contact region of the fin portion 101 and the doped region 110 is larger, the contact region of the fin portion 101 and the doped region 110 is easy to generate a self-heating effect, and the performance of the resistance element is influenced.
To solve the technical problem, the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising: the device comprises a device area, a first connecting area and a second connecting area which are respectively positioned at two sides of the device area; the first fin portion is located on the first connection region substrate, the second fin portion is located on the second connection region substrate, the extending direction of the first fin portion is parallel to the extending direction of the second fin portion, and the extending direction of the first fin portion is perpendicular to the arrangement direction of the first fin portion and the second fin portion; doped regions in the device region, first connection region and second connection region substrates; a plug spanning the first and second fins.
The extending directions of the first fin portion and the second fin portion are parallel, and the extending direction of the first fin portion is perpendicular to the arrangement direction of the first fin portion and the second fin portion. In the use process of the semiconductor structure, when current flows between the first fin portion and the doping region, the cross-sectional area of the current flowing through the channel is larger, and when current flows between the second fin portion and the doping region, the cross-sectional area of the current flowing through the channel is also larger, so that the contact resistance between the first fin portion and the doping region and the contact resistance between the second fin portion and the doping region are smaller, the heat generated by the semiconductor structure can be reduced, the self-heating effect of the semiconductor structure is reduced, and the performance of the semiconductor structure can be improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 14 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Providing a substrate, the substrate comprising: the device comprises a device area, a first connection area and a second connection area, wherein the first connection area and the second connection area are respectively located on two sides of the device area, a first fin portion is arranged on a substrate of the first connection area, a second fin portion is arranged on a substrate of the second connection area, the first fin portion and the second fin portion are arranged in parallel, and the extending direction of the first fin portion is perpendicular to the arrangement direction of the first fin portion and the second fin portion.
In this embodiment, the method for forming the substrate, the first fin portion and the second fin portion is as shown in fig. 3 and 4.
Referring to fig. 3, an initial substrate 203 is provided, the initial substrate 203 comprising: a device region a and a first connection region B1 and a second connection region B2 located at both sides of the device region a, respectively.
In this embodiment, the device region a is used for forming a doped region, and the first connection region B1 and the second connection region B2 are used for electrically connecting the doped region to an external circuit.
In this embodiment, the initial substrate 203 is made of silicon. In other embodiments, the material of the initial substrate may also be germanium or silicon germanium.
A patterned layer is formed on the initial substrate 203, which patterned layer exposes the device region a initial substrate 203 and portions of the first and second connection regions B1 and B2 initial substrate 203 surfaces.
The pattern layer is used for defining the positions and the sizes of the first fin portion and the second fin portion which are formed subsequently.
In this embodiment, the pattern layer is made of silicon nitride. In other embodiments, the material of the pattern layer may also be silicon oxynitride.
Referring to fig. 4, the initial substrate 203 is etched using the pattern layer as a mask to form a substrate 200, a first fin 201 on the substrate 200 of the first connection region B1, and a second fin 202 on the substrate 200 of the second connection region B2, wherein the first fin 201 and the second fin 202 are arranged in parallel, and an extending direction of the first fin 201 is perpendicular to an arrangement direction of the first fin 201 and the second fin 202.
The first fin portion 201 and the second fin portion 202 are used for connecting a doping region formed later with an external circuit.
The extending direction of the first fin portion 201 is the long side direction (Y direction) of the first fin portion 201; the arrangement direction of the first fin portion 201 and the second fin portion 202 is a connection line direction (X direction) between the center of the first fin portion 201 and the center of the second fin portion 202.
In this embodiment, the initial substrate 203 is etched by dry etching. The dry etching has anisotropy and good profile control, and the formed first fin portion 201 and the second fin portion 202 have good verticality with the substrate 200.
In this embodiment, the substrate 200, the first fin 201, and the second fin 202 are made of silicon. In other embodiments, the material of the substrate, the first fin portion and the second fin portion may also be germanium or silicon germanium.
Referring to fig. 5 and 6, fig. 6 is a cross-sectional view of fig. 5 along a cutting line 21-22, wherein a doped region 210 is formed in the device region a, the first connection region B1 and the second connection region B2 in the substrate 200, and the first fin 201 and the second fin 202.
The first fin portion 201 and the second fin portion 202 are arranged in parallel, and the extending direction of the first fin portion 201 is perpendicular to the arrangement direction of the first fin portion 201 and the second fin portion 202. In the use process of the semiconductor structure, in the process that current flows between the first fin portion 201 and the doped region 210 in the substrate 200 and between the first fin portion and the doped region 210 in the substrate 200, the cross-sectional area of the current flowing through the channel is large, so that the contact resistance between the first fin portion 201 and the doped region 210 in the substrate 200 can be reduced, and the contact resistance between the second fin portion 202 and the doped region 210 in the substrate 200 can be reduced, so that the self-heating effect of the contact region between the first fin portion 201 and the doped region 210 in the substrate 200 and the contact region between the second fin portion 202 and the doped region 210 in the substrate 200 are reduced, and the performance of the formed semiconductor structure is improved.
The doped region 210 has dopant ions therein for adjusting the resistance of the formed semiconductor structure.
In this embodiment, the doped region 210 is located in the device region a, the first connection region a1 and the second connection region B2 substrate 200.
In this embodiment, the step of forming the doped region 210 in the substrate 200 includes: the doped region 210 is formed by implanting dopant ions into the substrate 200 through ion implantation.
In this embodiment, the step of forming the doped region 210 further includes: implanting first doping ions in the first fin portion 201 by the ion implantation; second dopant ions are implanted in the second fin portion 202 by the ion implantation.
In this embodiment, the first doping ion, the second doping ion and the doping ion have the same conductivity type. Specifically, the first doping ion, the second doping ion and the doping ion are boron ions. In other embodiments, the first doping ion, the second doping ion and the doping ion may also be phosphorous ion or arsenic ion.
Referring to fig. 7, after forming the doped region 210, the method further includes: an isolation structure 220 is formed on the substrate 200 in the device region a, the first connection region B1 and the second connection region B2, wherein the isolation structure 220 covers part of the sidewalls of the first fin 201 and the second fin 202.
The isolation structures 220 are used to achieve electrical isolation between the first fins 201 and between the second fins 202.
In this embodiment, the isolation structure 220 is made of silicon oxide.
In this embodiment, the isolation structure 220 is formed by a fluid chemical vapor deposition process.
Referring to fig. 8, after forming the isolation structure 220, a third dummy gate 230 is formed on the device region a isolation structure 220; a first dummy gate 231 is formed across the first fin 201 and a second dummy gate 232 is formed across the second fin 202.
In the subsequent process of forming the dielectric layer, the third dummy gate 230, the first dummy gate 231 and the second dummy gate 232 can reduce the pits formed in the dielectric layer, so that the first plug and the second plug materials formed in the pits can be reduced, the insulation property of the dielectric layer can be further improved, and the performance of the semiconductor structure can be improved.
In this embodiment, the third dummy gate 230, the first dummy gate 231, and the second dummy gate 232 are made of polysilicon. In other embodiments, the material of the third dummy gate, the first dummy gate and the second dummy gate may also be poly germanium or poly silicon germanium.
In this embodiment, the extending directions of the first dummy gate 231 and the second dummy gate 232 are perpendicular to the extending directions of the first fin portion 201 and the second fin portion 202.
In this embodiment, the extending direction of the third dummy gate 230 is perpendicular to the extending direction of the first fin 201 and the second fin 202. In other embodiments, the third dummy gate extending direction may be parallel to the extending directions of the first and second fins.
In this embodiment, the third dummy gate 230 is located on the isolation structure 220.
In this embodiment, the step of forming the third dummy gate 230, the first dummy gate 231, and the second dummy gate 232 includes: forming a gate layer covering the sidewalls and the top surfaces of the first fin portion 201 and the second fin portion 202, and the device region a doped region 220; patterning the gate layer to form a third dummy gate 230 located on the device region a doped region 220, a first dummy gate 231 crossing the first fin portion 201, and a second dummy gate 232 crossing the second fin portion 202.
In this embodiment, the step of patterning the gate layer includes: and forming a patterned mask layer on the gate layer, and etching the gate layer by using the patterned mask layer as a mask to form the third dummy gate 230, the first dummy gate 231 and the second dummy gate 232.
In this embodiment, the process of etching the gate layer includes: and (4) dry etching. In other embodiments, the gate layer may also be etched by a wet etching process.
It should be noted that, in other embodiments, the forming method may not include: forming a first dummy gate, a second dummy gate and a third dummy gate; or, the forming method only comprises the step of forming the third dummy gate, but not comprises the step of forming the first dummy gate and the second dummy gate; alternatively, the forming method only includes a step of forming the first dummy gate and the second dummy gate, and does not include a step of forming the third dummy gate.
Referring to fig. 9 and 10, fig. 10 is a cross-sectional view taken along a cutting line 23-24 in fig. 9, wherein a first epitaxial layer 241 is formed in the first fin 201 at two sides of the first dummy gate 231; second epitaxial layers 242 are formed in the second fin portions 202 on both sides of the second dummy gate 232.
The first epitaxial layer 241 is used for electrically connecting a first plug formed subsequently with the first fin portion 201; the second epitaxial layer 242 is used to electrically connect a subsequently formed second plug to the second fin 202.
In this embodiment, the first epitaxial layer 241 and the second epitaxial layer 242 are made of silicon germanium.
In this embodiment, the first epitaxial layer 241 and the second epitaxial layer 242 are formed by an epitaxial growth process, and in the process of the epitaxial growth, the first epitaxial layer 241 and the second epitaxial layer 242 are doped in situ, and epitaxial ions are doped in the first epitaxial layer 241 and the second epitaxial layer 242.
The epitaxial ions are of the same conductivity type as the dopant ions. Specifically, in this embodiment, the epitaxial ions are boron ions, and in other embodiments, the epitaxial ions may also be phosphorus ions or arsenic ions.
Referring to fig. 11, a dielectric layer 250 covering sidewalls of the first fin 201 and the second fin 202 is formed, the first connection region B1 has a first contact hole 251 in the dielectric layer 250, a bottom of the first contact hole 251 exposes a top surface of the first fin 201, the second connection region B2 has a second contact hole 252 in the dielectric layer 250, and a bottom of the second contact hole 252 exposes a top surface of the second fin 202.
In this embodiment, the dielectric layer 250 is used to electrically insulate the first fin portion 201 and the second fin portion 202 from an external circuit.
In this embodiment, the dielectric layer 250 further covers the isolation layer 220 of the device region a.
In this embodiment, the step of forming the dielectric layer 250 includes: forming an initial dielectric layer on the isolation structure 220, wherein the surface of the initial dielectric layer is higher than the top surfaces of the first dummy gate 231 and the second dummy gate 232; carrying out planarization treatment on the initial dielectric layer; after the planarization treatment, the initial dielectric layer on the first epitaxial layer 241 and the second epitaxial layer 242 is etched until the top surfaces of the first epitaxial layer 241 and the second epitaxial layer 242 are exposed.
It should be noted that, since the device region a doped region 210 has the third dummy gate 230 thereon, the first dummy gate 231 is disposed on the top of the first fin 201, and the second dummy gate 232 is disposed on the top of the second fin 202, during the planarization process, the third dummy gate 230, the first dummy gate 231, and the second dummy gate 232 can reduce the planarization rate of the initial dielectric layer, so as to reduce the pits in the dielectric layer 250.
In this embodiment, the initial dielectric layer is planarized by a chemical mechanical polishing process.
In this embodiment, the initial dielectric layer is etched by dry etching. In other embodiments, the initial dielectric layer may be etched by wet etching.
Referring to fig. 12-14, fig. 13 is a cross-sectional view taken along a cutting line 25-26 of fig. 12, and fig. 14 is a cross-sectional view taken along a cutting line 27-28 of fig. 12, forming a first plug 261 spanning across a portion of the top of the first fin 201; a second plug 262 is formed across the top of a portion of the second fin 202.
It should be noted that, because there are fewer pits in the dielectric layer 250, in the process of forming the first plug 261 and the second plug 262, there are fewer materials of the first plug 261 and the second plug 261 in the pits, so that the insulation property of the dielectric layer 250 is not easily affected, and therefore, the forming method can improve the performance of the formed semiconductor structure.
In this embodiment, the material of the first plug 261 and the second plug 261 is tungsten. In other embodiments, the material of the first plug and the second plug may also be copper.
In this embodiment, the first plug 261 and the second plug 261 are formed by a chemical vapor deposition process.
In summary, in the method for forming a semiconductor structure of the present embodiment, the first fin portion and the second fin portion are arranged in parallel, and the extending direction of the first fin portion is perpendicular to the arrangement direction of the first fin portion and the second fin portion. In the use process of the semiconductor structure, when current flows between the first fin part and the doped region in the substrate, the cross-sectional area of the current flowing through the channel is larger, and when current flows between the second fin part and the doped region in the substrate, the cross-sectional area of the current flowing through the channel is also larger, so that the contact resistance between the first fin part and the doped region in the substrate and the contact resistance between the second fin part and the doped region in the substrate are smaller, the heat generated by the semiconductor structure can be reduced, the self-heating effect of the semiconductor structure is reduced, and the performance of the semiconductor structure can be improved.
Further, a third dummy gate is arranged on the device region doping region, the first connection region is provided with a first dummy gate crossing the first fin portion, and the second connection region is provided with a second dummy gate crossing the second fin portion. The first dummy gate and the second dummy gate can reduce pits formed in the dielectric layer, so that residual first plug and second plug materials in the pits can be reduced, the insulativity of the dielectric layer can be improved, and the performance of a semiconductor structure can be improved.
With continuing reference to fig. 12-14, the present invention further provides a semiconductor structure comprising: a substrate 200, said substrate 200 comprising: a device region a and first and second connection regions B1 and B2 located at both sides of the device region a, respectively; a first fin 201 located on the substrate 200 at the first connection region B1, and a second fin 202 located on the substrate 200 at the second connection region B2, wherein the first fin 201 and the second fin 202 are arranged in parallel, and an extending direction of the first fin 201 is perpendicular to an arrangement direction of the first fin 201 and the second fin 202; doped regions 210 in the device region a, first and second connection regions B1 and B2 substrate 200, and in the first and second fins 201 and 202; a first plug 261 spanning a portion of the top of the first fin 201, and a second plug 262 spanning a portion of the top of the second fin 202.
In this embodiment, the substrate 200, the first fin 201, and the second fin 202 are made of silicon. In other embodiments, the material of the substrate, the first fin portion and the second fin portion may also be germanium or silicon germanium.
The first fin portion 201 and the second fin portion 202 are arranged in parallel, and the extending direction of the first fin portion 201 is perpendicular to the arrangement direction of the first fin portion 201 and the second fin portion 202. In the use process of the semiconductor structure, current flows between the first fin portion 201 and the doped region 210 and between the first fin portion and the doped region 210, and the cross-sectional area of the current flowing through the channel is large, so that the contact resistance between the first fin portion 201 and the doped region 210 in the substrate 200 and the contact resistance between the first fin portion and the doped region 210 in the substrate 200 can be reduced, the self-heating effect of the energy of the contact region between the first fin portion 201 and the doped region 210 in the substrate 200 and the contact region between the first fin portion and the doped region 210 in the substrate 200 can be reduced, and the performance of the formed semiconductor structure can be improved.
The device region a doped region 210 has dopant ions therein for adjusting the resistance of the formed semiconductor structure.
In the present embodiment, the doped region 210 is located in the device region a, the first connection region B1, and the second connection region B2, the substrate 200, the first fin 201, and the second fin 202.
In this embodiment, the first fin portion 201 has first doping ions therein, and the second fin portion 202 has second doping ions therein.
The first doping ions are used for reducing the resistance of the first fin portion 201; the second dopant ions are used to reduce the resistance of the second fin 202.
In this embodiment, the first doping ion, the second doping ion and the doping ion have the same conductivity type. Specifically, the first doping ion, the second doping ion and the doping ion are boron ions. In other embodiments, the first doping ion, the second doping ion and the doping ion may also be phosphorous ion or arsenic ion.
The semiconductor structure further includes: and the isolation structure 220 is positioned on the device region A doped region 210, part of the sidewall of the first fin 201 and part of the sidewall of the second fin 202.
The isolation structures 220 are used to achieve electrical isolation between the first fins 201 and between the second fins 202.
The semiconductor structure further includes: a third dummy gate on the device region a doped region 210; a first dummy gate 231 crossing the first fin 201, the first dummy gate 231 covering a portion of the sidewall and the top surface of the first fin 201; a second dummy gate 232 crossing the second fin 202, the second dummy gate 232 covering a portion of sidewalls and a top surface of the second fin 202.
The third dummy gate 230, the first dummy gate 231 and the second dummy gate 232 can reduce the pits formed in the dielectric layer, so that the first plug and the second plug materials formed in the pits can be reduced, the insulation property of the dielectric layer can be improved, and the performance of the semiconductor structure can be improved.
In this embodiment, the third dummy gate 230 is located on the isolation structure 220.
In this embodiment, the third dummy gate 230, the first dummy gate 231, and the second dummy gate 232 are made of polysilicon. In other embodiments, the material of the third dummy gate, the first dummy gate and the second dummy gate may also be poly germanium or poly silicon germanium.
In this embodiment, the extending directions of the first dummy gate 231 and the second dummy gate 232 are perpendicular to the extending directions of the first fin portion 201 and the second fin portion 202.
In this embodiment, the extending direction of the third dummy gate 230 is perpendicular to the extending direction of the first fin 201 and the second fin 202. In other embodiments, the third dummy gate extending direction may be parallel to the extending directions of the first and second fins.
It should be noted that, in other embodiments, the semiconductor structure may not include the first dummy gate, the second dummy gate, and the third dummy gate; or, the semiconductor structure only comprises a third dummy gate, and does not comprise the first dummy gate and the second dummy gate; or, the semiconductor structure only comprises the first dummy gate and the second dummy gate, and does not comprise the third dummy gate.
The semiconductor structure further includes: the first epitaxial layer 241 is positioned in the first fin portion 201 on two sides of the first dummy gate 231; and the second epitaxial layers 242 are positioned in the second fin portions 202 on two sides of the second dummy gate 232.
The first epitaxial layer 241 is used for electrically connecting a first plug formed subsequently with the first fin portion 201; the second epitaxial layer 242 is used to electrically connect a subsequently formed second plug to the second fin 202.
In this embodiment, the first epitaxial layer 241 and the second epitaxial layer 242 are made of silicon germanium.
In this embodiment, the first epitaxial layer 241 and the second epitaxial layer 242 have epitaxial ions therein.
The epitaxial ions are of the same conductivity type as the dopant ions. Specifically, in this embodiment, the epitaxial ions are boron ions, and in other embodiments, the epitaxial ions may also be phosphorus ions or arsenic ions.
The semiconductor structure further includes: the dielectric layer 250 covers the sidewalls of the first fin 201 and the second fin 202, the dielectric layer 250 of the first connection region a1 has a first contact hole therein, the bottom of the first contact hole exposes the top surface of the first fin 201, the dielectric layer 250 of the second connection region B2 has a second contact hole therein, and the bottom of the second contact hole exposes the top surface of the second fin 202; the first plug 251 is located in the first contact hole, and the second plug 252 is located in the second contact hole.
In this embodiment, the dielectric layer 250 is used to electrically insulate the first fin portion 201 and the second fin portion 202 from an external circuit.
In this embodiment, the dielectric layer 250 further covers the device region a isolation layer 220.
Since the device region a doped region 210 has the third dummy gate 230 thereon, the first fin portion 201 has the first dummy gate 231 on the top thereof, and the second fin portion 202 has the second dummy gate 232 on the top thereof, a recess is not easily formed in the dielectric layer 250.
Because the number of the pits in the dielectric layer 250 is small, and the materials of the first plug 261 and the second plug 262 in the pits are also small, the insulativity of the dielectric layer 250 is not easily affected, and therefore, the forming method can improve the performance of the formed semiconductor structure.
In this embodiment, the material of the first plug 261 and the second plug 262 is tungsten. In other embodiments, the material of the first plug and the second plug may also be copper.
In summary, in the semiconductor structure of this embodiment, the first fin portion and the second fin portion are arranged in parallel, the extending direction of the first fin portion is perpendicular to the arrangement direction of the first fin portion and the second fin portion, and in the process of forming the doped region, the contact resistance between the first fin portion, the second fin portion and the doped region in the substrate is small, so that heat generated by the semiconductor structure can be reduced, the self-heating effect of the semiconductor structure is reduced, and the performance of the semiconductor structure can be improved.
Further, a third dummy gate is arranged on the device region doping region, the first connection region is provided with a first dummy gate crossing the first fin portion, and the second connection region is provided with a second dummy gate crossing the second fin portion. In the process of forming the dielectric layer, the pits formed in the dielectric layer can be reduced by the first dummy gate and the second dummy gate, so that the materials of the first plug and the second plug formed in the pits can be reduced, the insulativity of the dielectric layer can be improved, and the performance of a semiconductor structure can be improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A semiconductor structure, comprising:
a substrate, the substrate comprising: the device comprises a device area, a first connecting area and a second connecting area which are respectively positioned at two sides of the device area;
the first fin portion and the second fin portion are arranged in parallel, and the extending direction of the first fin portion and the extending direction of the second fin portion are perpendicular to the arrangement direction of the first fin portion and the second fin portion;
doped regions in the device region, the first and second connection region substrates, and the first and second fins;
a first plug spanning a portion of a top of the first fin;
a second plug spanning a portion of the top of the second fin;
a first dummy gate crossing the first fin portion, the first dummy gate covering a portion of a sidewall and a top surface of the first fin portion;
and the second dummy gate spans the second fin part and covers partial side wall and the top surface of the second fin part.
2. The semiconductor structure of claim 1, further comprising: and the third dummy gate is positioned on the doped region of the device region.
3. The semiconductor structure of claim 2, wherein a material of the third dummy gate is polysilicon, poly germanium, or poly silicon germanium.
4. The semiconductor structure of claim 2, wherein an extending direction of the third dummy gate is perpendicular or parallel to an extending direction of the first and second fins.
5. The semiconductor structure of claim 1, wherein a material of the first dummy gate and the second dummy gate is polysilicon, poly germanium, or poly silicon germanium.
6. The semiconductor structure of claim 1, wherein the first and second dummy gates extend perpendicular to a direction of extension of the first and second fins.
7. The semiconductor structure of claim 1, further comprising: the dielectric layer covers the side walls of the first fin portion and the second fin portion, a first contact hole is formed in the first connection region dielectric layer, the bottom of the first contact hole is exposed out of the top surface of the first fin portion, a second contact hole is formed in the second connection region dielectric layer, and the bottom of the second contact hole is exposed out of the top surface of the second fin portion; the first plug is located in the first contact hole, and the second plug is located in the second contact hole.
8. The semiconductor structure of claim 7, further comprising: and the dielectric layer also covers the top and the side wall surfaces of the third dummy gate, the first dummy gate and the second dummy gate.
9. The semiconductor structure of claim 2, further comprising: the isolation structures are positioned on the device region doping region, the substrate between the first fin parts and the substrate between the second fin parts;
the third dummy gate is located on the isolation structure.
10. The semiconductor structure of claim 1, wherein a doped region of the device region has dopant ions therein, the first fin has first dopant ions therein, and the second fin has second dopant ions therein;
the first doping ion, the second doping ion and the doping ion have the same conductivity type.
11. The semiconductor structure of claim 1, further comprising: a first epitaxial layer located between the top of the first fin and the plug; a second epitaxial layer between the top of the second fin and the plug.
12. A method of forming a semiconductor structure, comprising:
providing a substrate, the substrate comprising: the device comprises a device area, a first connection area and a second connection area, wherein the first connection area and the second connection area are respectively positioned on two sides of the device area;
forming doped regions in the device region, the first connection region and the second connection region substrate, and the first fin portion and the second fin portion;
forming a first plug that spans across a portion of a top of the first fin;
forming a second plug that spans across a portion of a top of the second fin;
forming a first dummy gate crossing the first fin portion, wherein the first dummy gate covers partial side walls and the top surface of the first fin portion;
and forming a second dummy gate crossing the second fin, wherein the second dummy gate covers partial side walls and the top surface of the second fin.
13. The method of forming a semiconductor structure of claim 12, wherein the forming the substrate, the first fin, and the second fin comprises:
providing an initial substrate;
forming a pattern layer on the initial substrate, wherein the pattern layer exposes the surface of the initial substrate of the device area and parts of the surfaces of the initial substrates of the first connection area and the second connection area;
and etching the initial substrate by taking the pattern layer as a mask to form a substrate, a first fin part positioned on the first connection region substrate and a second fin part positioned on the second connection region substrate.
14. The method of forming a semiconductor structure of claim 13, wherein the process of etching the initial substrate is a dry etching process.
15. The method of forming a semiconductor structure of claim 12, further comprising: and forming a third dummy gate on the device region substrate.
16. The method of forming a semiconductor structure of claim 15, wherein the step of forming the third dummy gate, the first dummy gate, and the second dummy gate comprises:
forming a gate layer covering the first fin part, the side wall and the top surface of the second fin part and the doped region of the device region;
and patterning the gate layer to form a third dummy gate on the device region doping region, a first dummy gate crossing the first fin portion, and a second dummy gate crossing the second fin portion.
17. The method for forming the semiconductor structure according to claim 12, wherein a material of the first dummy gate, the second dummy gate, and the third dummy gate is polysilicon, poly germanium, or poly silicon germanium.
18. The method of forming a semiconductor structure of claim 12, wherein the step of forming the doped layer comprises: implanting first doping ions in the first fin portion and second doping ions in the second fin portion;
implanting first doping ions in the first fin portion and second doping ions in the second fin portion by an ion implantation process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610756336.XA CN107799522B (en) | 2016-08-29 | 2016-08-29 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610756336.XA CN107799522B (en) | 2016-08-29 | 2016-08-29 | Semiconductor structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107799522A CN107799522A (en) | 2018-03-13 |
| CN107799522B true CN107799522B (en) | 2020-07-10 |
Family
ID=61528988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610756336.XA Active CN107799522B (en) | 2016-08-29 | 2016-08-29 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107799522B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103283016A (en) * | 2011-01-06 | 2013-09-04 | 国际商业机器公司 | Structure and method to fabricate resistor on fin FET processes |
| CN104160511A (en) * | 2011-12-30 | 2014-11-19 | 英特尔公司 | Wrap-around trench contact structure and methods of fabrication |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160031327A (en) * | 2014-09-12 | 2016-03-22 | 삼성전자주식회사 | Integrated circuit device having blocking insulating layer |
-
2016
- 2016-08-29 CN CN201610756336.XA patent/CN107799522B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103283016A (en) * | 2011-01-06 | 2013-09-04 | 国际商业机器公司 | Structure and method to fabricate resistor on fin FET processes |
| CN104160511A (en) * | 2011-12-30 | 2014-11-19 | 英特尔公司 | Wrap-around trench contact structure and methods of fabrication |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107799522A (en) | 2018-03-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5189741B2 (en) | Method for manufacturing MOS field effect transistor having multiple channels and MOS field effect transistor having multiple channels manufactured thereby | |
| KR100618861B1 (en) | Semiconductor device having local recess channel transistor and method of fabricating the same | |
| TWI548086B (en) | Trench lateral diffusion metal oxide semiconductor device and manufacturing method of the same | |
| KR101575401B1 (en) | Structure and method for vertical tunneling field effect transistor with leveled source and drain | |
| KR100545863B1 (en) | Semiconductor device having a fin structure and method of manufacturing the same | |
| KR100745917B1 (en) | Method for fabricating semiconductor device | |
| US20130292776A1 (en) | Semiconductor device employing fin-type gate and method for manufacturing the same | |
| KR100908522B1 (en) | Semiconductor device and manufacturing method thereof | |
| KR20060099876A (en) | Method for forming gate in semiconductor device | |
| KR100541054B1 (en) | Method of fabricating a three dimensional MOSFET employing a hardmask spacer | |
| US10290712B1 (en) | LDMOS finFET structures with shallow trench isolation inside the fin | |
| CN109216193B (en) | Semiconductor device and method for manufacturing the same | |
| US10497804B2 (en) | Vertical semiconductor device | |
| KR100718248B1 (en) | Method of forming a recess structure, a recessed channel type transistor having the recess structure, and method of manufacturing the recessed channel type transistor | |
| CN109585558B (en) | LDMOS FINFET structure with multiple gate structures | |
| TWI485807B (en) | Semiconductor component and method of manufacture | |
| CN107799522B (en) | Semiconductor structure and forming method thereof | |
| TW201733136A (en) | Semiconductor device | |
| KR100732269B1 (en) | Semiconductor device and method for fabricating the same | |
| CN113903806B (en) | Semiconductor structure and forming method thereof | |
| CN112289861B (en) | Semiconductor structure and manufacturing method thereof | |
| KR100827522B1 (en) | Semiconductor device and method for fabricating the same | |
| KR100698068B1 (en) | A fin-FET and a method for fabricating the same | |
| KR101004482B1 (en) | Method for Manufacturing Semiconductor Device | |
| CN109285779B (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |