CN104600116B - Field-effect semiconductor component and its manufacture method - Google Patents

Field-effect semiconductor component and its manufacture method Download PDF

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Publication number
CN104600116B
CN104600116B CN201410592595.4A CN201410592595A CN104600116B CN 104600116 B CN104600116 B CN 104600116B CN 201410592595 A CN201410592595 A CN 201410592595A CN 104600116 B CN104600116 B CN 104600116B
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semiconductor
junction
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CN104600116A (en
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M·聪德尔
K-H·巴赫
A·伍德
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Infineon Technologies AG
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Infineon Technologies AG
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    • H01L29/0873—Drain regions
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

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Abstract

The present invention relates to a kind of field-effect component, including semiconductor body, its edge region extends to the surface of semiconductor body from the back side, and semiconductor body includes semiconductor mesa, semiconductor mesa perpendicular to the vertical direction at the back side and/or surface to extend to be placed on surface height (hM) place semiconductor mesa top side, wherein, semiconductor body also includes in vertical cross section：Drift region, it at least extends to surface in edge region and is partly placed among semiconductor mesa；And it is at least partially located at the body region among semiconductor mesa, it forms the first pn-junction with drift region, first pn-junction extends between two side walls of semiconductor mesa, wherein, vertical range (d) of first pn-junction in the horizontal direction from semiconductor mesa top side can change and in the middle section separated by two side walls using maximum value (d1), and wherein, the maximum value (d1) it is at least height (hM) 70%.

Description

Field-effect semiconductor component and its manufacture method
Technical field
The form of implementation of the present invention is related to field-effect semiconductor component, more particularly, to vertical field-effect semiconductor crystal Manage and be related to the manufacture method of field-effect semiconductor component.
Background technology
The semiconductor transistor such as n metal oxide semiconductor field-effects of semiconductor transistor especially field-effect control Transistor (MOSFET) and with insulated gate electrode bipolar transistor (IGBT) different applications will be used among, wherein especially It is used as in power supply device and rectifier, electric car, air-conditioning and the switch even among stereo set.
So far, power semiconductor component is mainly according to the small electric conduction in area requirements (A) as small as possible Hinder (Ron), optimized especially in accordance with small product Ron*A, according to quick switch and/or relatively low switching loss. Inductance type load can produce larger due to voltage spikes in switching process, so as to additionally protect controlled power semiconductor structure Part.
Especially for usually used DMOS- field-effect transistors for high-power circuit, such as DMOSFET (double expansions Dispersed metallic oxide semiconductor field effect transistor), form its channel design by Dual Implantations.So far, DMOS crystal Pipe is embodied as flat DMOS transistors or is embodied as channel MOS transistor (trenched mos transistor).Flat DMOS transistors are outstanding It is higher blanking voltage (>Relatively large semiconductor area is needed when 30V), this will cause the product to become expensive.Ditch Groove MOS transistor needs very small semiconductor area, but higher technique expense will be brought when it is manufactured, and is, for example, There is provided for a suitable edge closure of voltage class.As a rule, area is made a profit and can exceeded in trenched mos transistor Extra technique expense, has thus generally reached cost savings.Power limited and/or so-called multicore flake products ( This, which is additional to DMOS- transistors, needs other signal path and wire) among fully can not be made a profit using the area, because To need some minimum semiconductor area for the energy and/or wire and pad for the treatment of rectification.However, such area exists It is expensive in complicated DMOS technologies.
Accordingly, there exist for improved field-effect semiconductor component and field-effect semiconductor component improved The demand of manufacture method.
The content of the invention
According to a kind of form of implementation, field-effect component includes semiconductor body, the semiconductor body edge region from The back side extends to the surface of the semiconductor body, and the semiconductor body includes semiconductor mesa, the semiconductor platform Face perpendicular to the vertical direction at the back side and/or the surface to extend to be placed on the surface height The semiconductor mesa top side at place, wherein, the semiconductor body also includes in vertical cross section：Drift region, it at least exists The surface is extended in the fringe region and is partly placed among the semiconductor mesa；And at least in part The body region being placed among the semiconductor mesa, it forms the first pn-junction with the drift region, and first pn-junction is in institute State and extend between two side walls of semiconductor mesa, wherein, first pn-junction is in the horizontal direction from the semiconductor mesa The vertical range of top side can change and in the middle section separated by two side walls using maximum value, and wherein, institute The value for stating maximum is at least the 70% of the height.
According to a kind of form of implementation, field-effect component includes semiconductor body, and its edge region extends to table from the back side Face, and the semiconductor body includes semiconductor mesa, the semiconductor mesa with the normal vector parallel to the back side and/ Or the vertical direction of the normal vector on the surface extends to the semiconductor mesa top side being placed on the surface, wherein, The semiconductor body also includes in vertical cross section：Drift region, it at least extends to described in the fringe region Surface and partly it is placed among the semiconductor mesa；And it is at least partially located among the semiconductor mesa Body region, it include two respectively with an adjacent Part I region in two side walls of the semiconductor mesa and The Part II region disposed between two Part I regions, wherein, described two Part I regions and described second Subregion forms the first pn-junction with the drift region, and first pn-junction is prolonged between two side walls of the semiconductor mesa Stretch, wherein, the Part II region is vertically deeper prolonged in the drift region than described two Part I regions Stretch, and wherein, the Part II region has bigger maximum dopant concentration than described two Part I regions.
According to a kind of form of implementation, the method for manufacturing field-effect component comprises the following steps：Wafer, the crystalline substance are provided Circle include the first semiconductor layer of the first power type, be placed in first semiconductor layer the second power type the Two semiconductor layers and the 3rd semiconductor layer for being placed in second semiconductor layer, second semiconductor layer and described the Semi-conductor layer forms the first pn-junction, and the 3rd semiconductor layer forms the second pn-junction with second semiconductor layer and extended To the top side of the wafer；The table top mask with multiple openings is formed on the top side of the wafer；By described Table top mask etches the wafer so that produces multiple deep raceway grooves and is placed in multiple between the multiple deep raceway groove Semiconductor mesa, wherein, the multiple deep raceway groove extends into first semiconductor layer；And by first power type Dopant inject at least one semiconductor regions adjacent with first pn-junction.
For professional, other feature is can be derived that when reading following detailed description of book and checking accompanying drawing And advantage.
Brief description of the drawings
Part in the accompanying drawings is not necessarily certain drawn to scale, wherein, emphasis is to illustrate the present invention in fact Basic conception.In addition, identical reference describes corresponding part in the accompanying drawings.In accompanying drawing：
Figure 1A and Figure 1B shows the vertical sectional view through the field-effect semiconductor component according to a form of implementation；
Fig. 2 shows the vertical sectional view through the field-effect semiconductor component according to a form of implementation；And
Fig. 3 to Fig. 9 show according to the present invention method multiple steps during or after pass through semiconductor die Round vertical sectional view.
Embodiment
Referred to as the part of this document and wherein schematically in ensuing detailed description Show the accompanying drawing for the specific form of implementation that the present invention actually realizes.Direction instruction as " on ", " under ", "front", "rear", " above ", use to upper described direction with reference to the accompanying drawings " below " etc..Because the component of some forms of implementation can It is positioned on a series of different directions, so direction indicates to be used to illustrate rather than limit.Indicating can use in addition Form of implementation and take structural or logic change, without beyond the scope of this invention.Therefore from next detailed Thin explanation can't read restricted implication and the scope of the present invention will be determined by claim.In addition, It is also represented by this association：The feature either device of combinations of features (such as material or its combination) and/or multiple fields, these Device explicitly only adds a public affairs with reference to a kind of device in the description, in the accompanying drawings and/or in multiple claims Open, as long as not providing others for those skilled in the art then similarly discloses the corresponding of affiliated manufacture method Feature or combinations of features.With for the feature disclosed in professional or combinations of features analogously, in specification, attached Only expressly feature or combinations of features also correspondingly give with reference to disclosed in being subject to manufacture method in figure and/or claim The corresponding feature or combinations of features of manufactured device.
Different forms of implementation is will be explained in detail from now on, and one or more of which example will in the accompanying drawings Show.It is that each example is for purposes of illustration and provided and and be not understood to the limitation for the present invention.It is exemplary Ground, can as the feature that a part for some form of implementation is shown or described can among other forms of implementation or Person is applied in association with other forms of implementation, so as to draw other form of implementation.The present invention should include such Change or modification.These examples will be described using specific language, and these language are not intended to the appended right of limitation will The scope asked.Purpose that is that accompanying drawing is not necessarily to scale and being only used for signal.For clear cause, as long as be Show to distinguish, the identical element or manufacturing step among different accompanying drawings will be retouched with identical reference State.
Statement " level " should describe such direction among the scope of this specification, and the direction is arranged essentially parallel to half Conductor matrix is either extended first or horizontal surface of semiconductor body.It can be, for example, wafer or chip Surface.
It can be derived that among this specification：The second surface of semiconductor substrate either semiconductor body by following or The surface (back side) at the back side is formed, and it is typically flat and parallel to first surface.
" vertical " such direction described in the scope of this specification is stated, the direction is substantially perpendicular to the first table Face and/or second surface, that is to say, that substantially with the normal direction of semiconductor substrate or the first surface of semiconductor body And/or the normal direction of second surface is parallel.Concept " above " and " following " are described with reference to another with vertical directional correlation The relative arrangement of the architectural feature of outer architectural feature.
The concept " table top (Mesa) " and " semiconductor mesa " synonymously used in the context of present patent application describes Semiconductor regions between two adjacent raceway grooves, the two adjacent raceway grooves extend into semiconductor substrate or semiconductor master Among the vertical cross section of body.Typically, at least two semiconductor regions for forming pn-junction are set among the semiconductor mesa.
Typically, in the region of activation, multiple semiconductor mesas extend to half on vertical direction from first surface Conductor matrix either the top side being arranged on first surface of semiconductor body or limits the top side.The semiconductor substrate or Next the top side of person's semiconductor body will be described as semiconductor mesa top side.Typically, the semiconductor mesa top side is basic It is upper parallel with first surface and/or second surface.
In the present patent application, the semiconductor regions of n doping are described as the semiconductor regions of the first power type, and p The semiconductor regions of doping are described as the semiconductor regions of the second power type.Alternatively, can construct with contrast Doping relation semiconductor component so that the first power type corresponding to p adulterate and the second power type can correspond to n Doping.In addition, in some drawings by providing "-" or "+" for doping type to provide relative doping concentration.For example, " n- " represents less than the doping concentration of the doping concentration of " n " doped region, and " n+ " doped region has and is more than " n " doped region Doping concentration doping concentration.When giving relative doping concentration, proposed as long as being not known, be then not meant to have The doped region of identical relative doping concentration must possess the absolute doping concentration of identical.For example, two different n+ doping Region has different absolute doping concentrations.It is also suitable similarly for the example of n+ doped regions and p+ doped regions.
In the present patent application described specific form of implementation especially but not merely refer to that field-effect is partly led Body component, more particularly, to such as vertical MOSFET field-effect semiconductor transistor and its manufacture method.
Typically relate to the source metal level for being arranged on top side and be typically positioned at semiconductor near top side The vertical power of the grid of the insulation among raceway groove between table top and the leakage metal level being arranged on the opposite back side MOSFET.These metal levels typically also provide corresponding connection end, such as among contact surface region.The vertical semiconductor Power transistor includes multiple units, such as MOSFET units typically among the region of activation, for transmitting and/or controlling Load current.In addition, by from the point of view of above, the face of the activation can be wrapped by least one edge closure structure at least in part Enclose.
In the context of the present specification, statement " metal level " should describe to have metal or intimate metal on The region of the characteristic of electric conductivity or layer.One metal level can contact with semiconductor regions and construct electrode, contact surface (weldering Disk) and/or semiconductor component connection end.The metal level can be made up of such as Al, Ti, W, Cu and Co metal or including Such metal, but can also be manufactured by the material of the characteristic of metal the or intimate metal on electric conductivity, such as The silicide such as TaSi of strong n Si polymer, TiN or conduction that either p is adulterated2、TiSi2、PtSi、CoSi2、WSi2Or Such.The metal level can also include different conductive materials, such as the superposition (Stapel) of multiple material.
Statement " edge closure structure " such as its used among present patent application such knot should be described like that Structure, it provides transitional region, and the high electric field in region of the activation of semiconductor component is surrounded among the transitional region little by little Change turns to turns to reference potential such as in the potential at the edge of the component and/or change.The edge closure structure can pass through Electric field line distribution is for example avoided into the field strength near the pn-junction in join domain.
Statement " power semiconductor component " should be described in the range of present patent application with high voltage and/or high electricity Flow control or contact capacity () single chip on semiconductor component.In other words, should Power semiconductor component is typically covered in the range of ampere level for high electric current and/or high voltage is for example in about 10V On or about on 500V.In the range of present patent application, term " power semiconductor component " and " semiconductor power element Part " is synonym.
Statement " field-effect " describes " passage " that has ducting capacity of the first power type in the range of present patent application The control for passing through construction that electric field obtains and/or ducting capacity and/or logical in the semiconductor regions of the second power type The body region of the form in road, typically the second power type.Due to the reason of field-effect, constructed by the passage area And/or source region and with the body region adjacent first power type of the control in first power type adjacent with body region The current path of monopole between drift region.The drift region can be with the first power type more highly doped drain region contact.
The drain region contacts with leakage metal level ohm formula.The source region and the body region contact with source metal level ohm formula. In the context of the application, when at the semiconductor component and/or on do not apply any voltage or only apply less inspection When electrical verification is pressed, statement " contact of ohm formula " describes has ohm between corresponding element or a part for semiconductor component The current path of formula.Among the scope of present patent application, statement " electrical contact ", " electrical connection " and " contact of ohm formula " is as same Adopted word uses.
In the context of the present patent application, concept " MOS " (metal-oxide semiconductor (MOS)) should be understood to include generally Concept " MIS " (metal separators semiconductor).For example, concept MOSFET (mos field effect transistor) should When being interpreted as including the field-effect transistor (FET) with gate isolation device, it is not oxide or, in other words, MOSFET It is used for IGFET (semiconductor field effect transistor with the grid of isolation) or MISFET (metals in the general sense Isolator semiconductor field effect transistor).
In the context of the present patent application, statement " switch " describes such semiconductor structure, and it is typically described Power MOSFET or power IGBT, is so configured, so as to its can transmit generally ampere level load current simultaneously And the load current can be interrupted.
In the context of the present patent application, statement " grid " describe such electrode, its it is adjacent with body region and Insulate and so configured so that can be constructed and/or controlled by body region by the suitable control to grid Make the passage area between source region and drift region.
Next following form of implementation is illustrated referring especially to silicon semiconductor component, it is related to semiconductor component and for structure The method of manufacturing semiconductor component.Correspondingly, single-crystal semiconductor region either single-crystal semiconductor layer be typically crystal region or Silicon layer.However, the semiconductor body can be also subject to by the suitable semi-conducting material of manufacture respectively for semiconductor component Manufacture.For example, such material especially such as silicon (Si) either germanium (Ge), such as carborundum (SiC) or SiGe (SiGe) IV group iii v compound semiconductor materials, two kinds, three kinds or four kinds of III-V group semi-conductor material such as gallium nitride (GaN), GaAs (GaAs), gallium phosphide (GaP), indium phosphide (InP), InGaP (InGaPa), aluminium gallium nitride alloy (AlGaN), Aluminum indium nitride (AlInN), nitrogen indium gallium (InGaN), aluminum indium gallium nitride (AlGaInN) or indium arsenic phosphide gallium (InGaAsP) and Two kinds or three kinds of Group II-VI semiconductor materials, such as cadmium telluride (CdTe) and cadmium mercury telluride (HgCdTe), only to enumerate one A little materials.Semi-conducting material mentioned above can also be described as the semiconductor material with homojunction (Homo ü bergang) Material.When two kinds of different semi-conducting materials are mutually combined, a kind of semi-conducting material is constructed with homojunction.Such as For the semi-conducting material of homojunction especially without limitation for the aluminium gallium nitride alloy (AlGaN) with homojunction- Aluminum indium gallium nitride (AlGaInN), indium gallium nitrogen (InGaN)-aluminum indium gallium nitride (AlGaInN), indium gallium nitrogen (InGaN)-gallium nitride (GaN), aluminium gallium nitride alloy (AlGaN)-gallium nitride (GaN), InGaN (InGaN)-aluminium gallium nitride alloy (AlGaN), silicon, carborundum (SixC1-x) and silicon-germanium semi-conducting material.For power semiconductor application, at present main silicon, carborundum, GaAs and Gallium nitride material can be applied.When semiconductor body include such as carborundum or gallium nitride have higher band gap (> During material 2eV), it has high disruptive field intensity or high crucial avalanche breakdown field strength (avalanche breakdown field strength), so The doping of semiconductor regions can be elected as higher accordingly, and this will reduce opening resistance RON, next it is also been described as Connect resistance RON。
Figure 1A shows the vertical section through vertical field-effect semiconductor component 100a.The field-effect semiconductor component 100a includes semiconductor body 40, and it is among fringe region 120, and the fringe region, which extends up to, substantially perpendicularly to be oriented Side or side 41, such as extend to from the back side 102 of semiconductor body 40 the saw edge of first surface 101.Next, One surface 101 is also described as surface 101.The back side 102 is formed by the second surface of semiconductor body 40, and it is typically substantially Parallel to first surface 101, such as the normal vector e in two introducingsnAs identifying.In addition, the semiconductor body 40 has There is the semiconductor mesa 20 with two side walls 21 substantially perpendicularly oriented, but in figure ia for clear among the two The cause of Chu only shows the side wall on the left side with reference 21.The semiconductor mesa 20 has vertical height or maximum Vertical dimension hM.According to the difference of voltage class, height hMAmong about 500nm to about 5 μm of scope, typically about Among 500nm to about 2 μm of scope.
In the embodiment of example, the semiconductor mesa 20 and the side wall 21 are with vertical direction enExtend up to and setting Height h on 3rd surface 103 of the semiconductor body 40 on first surface 101M, the 3rd surface is substantially parallel In the first and second surfaces 101,102 and form the top side 103 of the semiconductor body 40.
In a further embodiment, side wall 21 tilts relative to first and/or second surface 101,102.
In addition, the surface 103 of semiconductor mesa 20 is also classified into some and/or at least portion in vertical cross sectional view It is bending to divide ground.In this embodiment, semiconductor mesa 20 also define one substantially with the first and second surfaces 101st, the top side 103 of 102 parallel semiconductor bodies 40, it is located at first surface 101 at a distance of hMPlace.
Because either multiple semiconductor mesas 20 form or at least partially defined the top side 103 to the table top 20, Next the top side 103 is also described as table top top side 103.
Typically, the semiconductor body 40 has multiple semiconductor mesas 20 among the region 110 of activation, and they are from One surface 101 extends to top side 103, wherein, adjacent semiconductor mesa passes through depth respectively in vertical cross sectional view For hMDeep (vertical) raceway groove 50 be spaced from each other.Then, Figure 1A corresponds to the edge section on the left side of corresponding cross section, Edge section on the right of it is typically implemented as symmetrical in mirror with Figure 1A.Typically, the region 110 of activation in top view by Fringe region 120 is surrounded.
According to a form of implementation, semiconductor body 40 has the drift of the first power type in addition on vertical cross section Move area 1 (being next also described as drift region), the second power type body region 2 (being next also described as body region) and The source region 3 (being next also described as source region) of first power type.Wherein, drift region 1 is in border area 120 and in depth First surface 101 is extended in raceway groove 50 and is extended partially among the semiconductor mesa 20 in the region 110 of the activation.With On the contrary, source region 3 fully or the body region 2 is arranged among semiconductor mesa 20 at least most ofly.Body region 2 with Drift region 1 is collectively forming the first pn-junction 14 and is collectively forming the second pn-junction 15 with source region 3, and second pn-junction 15 is arranged on first On pn-junction 14 and extend to side wall 21.
Typically, multiple table tops 20 are provided among the region of activation, they are mutual by corresponding deep raceway groove 50 Separate.As being set forth in hereinafter with reference to Fig. 3 to Fig. 9, it can manufacture particularly effectively and in cost-effective manner Such semiconductor structure including optional marginal texture.Wherein, will be real before any topological pattern is generated on wafer The technology for being applied to generation bilateral diffusion MOS basic structure (injection, spreading to generate body region and source region 2,3) is more sensitive Processing step.During thus, it is possible to when the effective area of identical utilizing, for example in traditional generation channel mosfet, additionally The control brought due to the rank at multiple table tops 20 and side effect is at least further avoided, and therefore significantly decreases work Skill controls.Because separating source region and body region 2,3 in same edge region 120 in mesa etch, it is furthermore possible to bright Reduce or even save completely aobviously and spent for the additional technique of marginal texture.
According to a kind of form of implementation, the first pn-junction 14 extends between two side walls 21 of the semiconductor mesa 20, wherein, The pn-junction 14 and the vertical distance of semiconductor mesa top side 103 change on the direction of level, that is to say, that are the side walls 21 Horizontal distance non-constant function, and assume its maximum d1Semiconductor mesa 20 by the institute of two side walls 21 every Among the middle section 2c opened, i.e., the semiconductor mesa 20 reference level direction centre or central region 2c Among.Wherein, maximum d1For height hMAt least 70%, more typically height hMAt least 80% and very To more typically height hMAt least 90%.Typically, maximum d1Less than height hM200% be, for example, less than Height hM150%, more typically less than height hM120% and be even more typically less than height hM's 110%.Maximum d1Selection can depend on semiconductor component 100a voltage class and absolute altitude (channel depth) hM。 So there is 500nm or at least maximum d at very flat semiconductor mesa 201Also height h can be more thanM's 200% such as height hMAbout 300%.In figure ia in shown exemplary embodiment, as the horizontal of side wall 21 The pn-junction 14 of the function of distance is piecewise constant and at side wall 21 from the vertical distance d of semiconductor mesa top side 103 And its surrounding uses its minimum value d2, the minimum value is less than height hMAnd such as it is at height hM50% to Among 90% scope.
Thus the body region 2 vertically extends deeper into the drift region 1 in the middle section of the table top 20, and this will draw Rise, at that namely in the first pn-junction 14, when the side of blocking is run up, the electric field line can become close in the case of blocking, so that Obtaining can be placed under middle section 2c high accordingly when blocking voltage in the avalanche breakdown among drift region 1.With such Mode can reach the high stability of the component, for the avalanche breakdown repeated.
Therefore, first pn-junction 14 and body region 2 on vertical cross section on central perpendicular by the table top 20 D-axis mirror is symmetrical, so as to the avalanche breakdown point in horizontal direction is placed in the centre substantially of the table top 20 and so that Two side walls 21 of the avalanche current away from table top 20 and the dielectric medium that typically applies at that, therefore protection can be able to make it From the intrusion of energy carrier (" hot charge carrier ").But the pn-junction 14 also can be asymmetricly carried out, to avenge Electric current is suitably guided out in the case of collapsing breakdown.
It is furthermore possible to set the body region 2 near the pn-junction and among middle section 2c with than in body region 2 from side wall 21 closer to region among higher maximum dopant material concentration.Thus, the electric field line in the case where blocking Focusing and the thus focusing of the electric current line in the case of avalanche breakdown are further improved.In other words, in the first pn The gradient of dopant material concentration can change and in the middle section 2c separated by two side walls 21 in the horizontal direction at knot Among take maximum.In particular, the body region 2 among middle section 2c, which can have, carries elevated dopant material concentration Subregion, as being illustrated by detail referring next to Figure 1B.
In fig. ib as in the exemplary embodiment of the field-effect component 100b shown by vertical cross section, semiconductor Main body 40 includes drift region 1 and the body region 2 being at least partially disposed among semiconductor mesa 20, and drift region 1 is in marginal zone First surface 101 is extended in domain 120 and is partially disposed among semiconductor mesa 20, body region 2 have two with by The adjacent Part I region 2a of two side walls 21 of semiconductor mesa 20 and one set between two Part I region 2a The Part II region 2b put, wherein, two Part I region 2a and the Part II region 2b and drift region 1 form the One pn-junction 14, it extends between two side walls 21 of semiconductor mesa 20, wherein, Part II region 2b is vertically than two Part I region 2a is extended deeper among drift region 1 and than two Part I region 2a tools of Part II region 2b There is bigger maximum dopant material concentration.
Because the Part II region 2b set among middle section 2c of table top 20 vertically extends deeper into drift Move among area 1 and there is higher dopant material concentration than adjacent Part I region 2a, so blocking feelings there Electric field line is so concentrated under condition so that it is corresponding it is high block voltage in the case of avalanche breakdown among drift region 1 put Under middle section 2c.Reached in this way in particular for the avalanche breakdown repeated the component it is higher steady It is qualitative.
Typically, Part II region 2b maximum dopant material concentration has been enhanced relative to Part I region 2a At least five times of maximum dopant material concentration, more typically at least ten times.
Typically, in top side 103 and respectively, one in two Part I region 2a is formed between drift region 1 The first pn-junction 14 the first segmentation between vertical the first distance of maximum (because clearly reason is not shown in fig. ib, D is corresponded in figure ia2) it is less than the vertical distance h between top side 103 and first surface 101M, and in the He of top side 103 Maximum between second segmentation of the first pn-junction 14 formed between Part II region 2b and drift region 1 it is vertical second Distance is (because clearly reason is equally not shown in fig. ib, in figure ia corresponding to d1) be more than maximum vertical first away from From.But reference picture 1A elaboration is analogously with, maximum vertical second distance can also be more than height hM's 200%.
Typically, (such as the thermal oxide of gate dielectric region 30 is provided with least one in the side wall of table top 20 Thing) and the grid 12 adjacent with the gate dielectric region 30 and set source metal level 10 on semiconductor mesa 20 with The 2 ohm of formula contacts in body region 2 and source region, wherein, the grid 12 among raceway groove insulate with source metal level.In addition, overleaf Typical leakage metal level unshowned in fig. ib is placed in contact with 1 ohm of drift region formula on 102 so that field-effect component 100b can be run as vertical MOSFET.
Source metal level 10 is typically only arranged on the first pn-junction 14, and grid 12 is typically partially disposed at this On first pn-junction 14 and partly under it, typically, however it is provided only on the first surface 101.
In the exemplary embodiment, source region 2 and Part II region 2b pass through the raceway groove among flat raceway groove 51 Contact is connected with 10 ohm of formulas of source metal level, wherein, Part II region 2b can be undertaken including corresponding channel region simultaneously The function of Part I region 2a body contact region, so as to the locking stability realized.Among another form of implementation, Part II region 2b extends up to top side 103 or at least extends nearly to the top side 103.Another form of implementation it In, Part II region 2b by it is corresponding highly doped and set on the 2b of Part II region, can also play master Halfth area of the effect of body contact zone or silicide and be connected with the 10 ohm of formulas of source metal level being arranged on top side 103.
Fig. 2 shows the section diagram through the left side of the vertical cross section of field-effect component 100.The field-effect component 100 with it is similar above with reference to field-effect component 100a, 100b that Figure 1A and Figure 1B are illustrated and being capable of same conduct MOSFET is run.Among the region 110 of activation, but it is provided with multiple table tops 20.In addition, overleaf set on 102 There is leakage metal level 11, it is contacted by highly doped drain region 4 with 1 ohm of drift region formula.In addition, the first pn-junction 14 is in body region It is not piecewise linearity respectively among shown exemplary cross-sectional is shown between 2 and drift region 1 but so bends, makes Accordingly the first pn-junction 14 from top side 103 it is vertical with a distance from as horizontal distance function first from corresponding table top 20 A side wall rise and increase, then then fallen after rise during close to the second corresponding side wall using maximum and again.
This by cause the electric field line in the case of blocking focusing and thus in avalanche breakdown when electric current line focusing. This is lucidly stated the equipotential line 19 in avalanche breakdown additionally marked in fig. 2, in electric field line thereon or Electric current line is vertical.In addition, the region of highest ionization by collision is shown by the roundlet of point-like in fig. 2.There it can be seen that It can realize and avalanche breakdown is placed under the first pn-junction and is set to respectively on corresponding table top 20 in the horizontal direction It is middle.As the accurate analysis of the digital simulation of the invention being based on, thus, it is possible on the one hand cause avalanche breakdown electric current Be evenly distributed on table top 20 and on the other hand the side wall away from table top 20 and thus away from be arranged on grid 12, Gate dielectric 30 between 12a and table top 20.This will significantly increase the n-channel MOSFET 100 of example relative to repetition The robustness of avalanche breakdown, so that MOSFET100 is good for corresponding application, especially power application such as motor control It is suitable well.Inductance type load can produce big due to voltage spikes in switching process, and semiconductor switch 100 can pass through restriction The avalanche breakdown effect (avalanche breakdown multiplier effect) that ground flows through preferably protects it from the injury of due to voltage spikes in breakdown. Therefore, it is possible to save the protector wiring of respective external.
Curve by the equipotential line 19 to side 41 is clear in addition, i.e., electric equipotential line 19 is due to the marginal zone in deeper inside Domain 120 and be flatly arranged under the face of total very much, only extension is straight on vertical direction for the fringe region To first surface 101.This is (single for unshowned supplementary structure such as electric current or temperature sensor and in the region of activation First field areas) grid among 110 refer to it is especially very favorable for the additional injection of (Gatefingern).In particular, The electric field improved in semiconductor body 40 can depth raceway groove 50,50a angle at avoid edge cells (to edge 41 with And or to supplementary structure) and thus improve the reliability of transistor.Typically, the deep raceway groove 50,50a extend up into Enter the identical depth h of semiconductor bodyM.Also it can set deep raceway groove 50 among the region 120 of activation compared on side Deep raceway groove 50a among edge region 120 somewhat extends deeper into semiconductor body and/or drift region 1 or in side The semiconductor body among edge region 120 near 41 also reaches at somewhat higher than the region 120 in activation, still It is not extended to top side 103.
It is furthermore possible to set substantially only through some table tops in table top 20 to be guided out avalanche breakdown electric current, for example, it is logical Cross each second or the 3rd semiconductor mesa 20 realize so that the body region of other table tops is at least in middle section Among do not extend into deeply among drift region 1 so.
According to one embodiment, at least one edge closure structure 12b is set among the fringe region 120 of component 100, It is set in top view between semiconductor mesa 20 and side 41.Energy is blocked thus, it is possible to improve semiconductor component 100 Power.Typically, among shown cross section the fringe region at about 30 μm to about 50 μm either to about 100 μm or even Among scope between to 200 μm.
In fig. 2 among shown exemplary embodiment, the edge closure structure is implemented as being arranged on first surface Field plate 12a, 12b on 101, it also functions to the effect of grid in the segmentation 12a adjacent with the table top 20 close to edge.So And this is only an example.The edge closure structure can also have field plate, the floating field being connected with source metal level 10 The semiconductor that plate, (floating in the air) p of one or more floating injected in drift region 1 near first surface 101 are adulterated Area's (" Floating Guard "), so-called VLD- structures (" change laterally adulterated ") and/or at least one in the He of first surface 101 The passage stop zone of n doping that side 41 is nearby set and high.
It is described below for manufacturing reference picture 1A to Fig. 2 the method for field-effect semiconductor component that illustrates.Wherein, The vertical cross section diagram through the semiconductor component structure is respectively illustrated into Fig. 9 in Fig. 3.
First, there is provided such as Silicon Wafer of semiconductor crystal wafer 40, next it is being also been described as wafer 40.The semiconductor die The second of the monocrystalline that the first semiconductor layer 1, the p being arranged on the first semiconductor layer 1 that circle 40 includes the monocrystalline of n doping are adulterated 3rd semiconductor layer 3 of semiconductor layer 2 and the monocrystalline for the n doping being arranged on the second semiconductor layer 2, the second semiconductor layer 2 The first pn-junction 14 is formed with the first semiconductor layer 1 and the semiconductor layer 1 of the 3rd semiconductor layer 3 to the first higher adulterates and with the Two semiconductor layers 2 form the second pn-junction 15 and extend up to the top side 103 of wafer 40.In the field-effect semiconductor structure manufactured Among part 100, remaining part of the first semiconductor layer 1, the second semiconductor layer 2 and the 3rd semiconductor layer 3 forms drift region 1st, body region 2 and source region 3.
According to one embodiment, dielectric layer 31 is produced in whole region on top side 103, such as pass through separation or hot oxygen Change.
After this, the photo-structuring mask 7 with multiple openings is produced on the top side 103 of wafer 40, these Opening is subsequently used for producing semiconductor mesa and is therefore also been described as table top mask 7.Thus the structure 100 drawn is being schemed Shown in 3.Fig. 3 is typically only the sub-fraction of whole wafer 40 and then shown from multiple parallel Substantially semiconductor component in the semiconductor component 100 of ground manufacture, its side drawn in division process afterwards Face (side) 41 is shown by the vertical curve of void in figure 3.Typically, multiple first openings in mask 7 are shown Vertical cross section among among the separated region afterwards than the second opening among the mask 7 between the multiple first openings With bigger horizontal clearance (or with bigger aperture area in top view).
As illustrated in Figure 3, wafer 40 includes the 4th semiconductor layer of the monocrystalline of typically additional n doping 4, it is higher adulterated than the first semiconductor layer 1, and it extends up to the back side 102 of the wafer and in the component 100 manufactured In be typically formed drain region 4.4th semiconductor layer 4 can be directly adjacent with the first semiconductor layer 1.In other implementation shape Among formula, the semiconductor layer of another n doping is set between the 4th semiconductor layer 4 and the first semiconductor layer 1, its maximum doping Material concentration is in the maximum dopant material concentration and the 4th semiconductor layer 4 of the first semiconductor layer 1 typically among the region Maximum dopant material concentration between and can form among the semiconductor component manufactured a stop-layer.
First, second, and third semiconductor layer 1,2,3 can be by extension and corresponding injection and thermal annealing (" at heat Reason ") produce.This is typically so realized so that 15 mutual and and top side of the first pn-junction 14 and the second pn-junction 103 and the back side 102 it is substantially parallel.
Now, wafer 40 is etched in the case where using table top mask 7, wherein, also etch dielectric layer 31.This will be as This place realized, i.e., deep raceway groove 50,50a and the semiconductor mesa 20 that is set between the raceway groove 50,50a of depth form height hM, wherein, substantially parallel with the back side 102 first that deep raceway groove 50,50a are extended up among the first semiconductor layer 1 Surface 101.Thus the structure 100 drawn is shown in Fig. 4.
Typically, deep raceway groove 50,50a extend up to entrance with the scope of about 500nm to about 2 μm or even about 5 μm First semiconductor layer 1.
Typically, positioned at fringe region 120 deep raceway groove 50a in shown vertical cross section have than positioned at The bigger horizontal clearance of deep raceway groove 50 among the region 110 of activation.This closes the edge simplified among the fringe region Close the generation after structure.
Now, the raceway groove 50 in depth, the grid 12, the 12a that are insulated among 50a can be formed.Wherein, in the raceway groove of depth 50th, 50a bottom and table top 20 side wall 21 and depth raceway groove 50, at 50a for example by thermal oxide or by Other dielectric regions 33 are typically formed in separating technology.After this, deep raceway groove 50,50a can be partially by leading Logical material for example highly doped poly- silicon is filled, to form grid 12,12a.This can pass through separation and following part Ground is etched back separated material to realize.Wherein, dielectric medium area 33 in addition is realized in such a way, i.e., other dielectric medium area 33 exists Thickness among deep raceway groove 50a is with being different and/or other dielectric medium areas 33 among deep raceway groove 50 in side wall 21 Thickness with the thickness at corresponding deep raceway groove 50,50a or corresponding table top 20 be different.It is furthermore possible to set Put, form another dielectric medium area 34, such as the thermal oxide by separated poly- silicon respectively on grid 12 (12a).
According to another embodiment, the grid 12a of the insulation among the raceway groove 50a of depth is so constructed, so as to Be formed as the field plate with semiconducting insulation simultaneously, it is side on first surface 101 and with corresponding adjacent side 41 To being extended and there is one or more rank.Another dielectric medium area 33 can be in the raceway groove of depth in this embodiment So formed in 50a so that its thickness is that vertical gap is improved to ensuing in one or more rank Side 41.
After this, the interlevel dielectric matter 9 of such as TEOS (tetraethyl orthosilicate) oxide separates from top side 103, so as to Cover grid 12,12a.Can be in top side in such as CMP- techniques (chemical-mechanical polish) among ensuing planarization process 103, which form a layer, is used to contact printing.Fig. 5 shows structure 100, forms corresponding light on top side 103 after which Mask 62.
Next interlevel dielectric matter 9 and Jie after mesa etch on table top 20 will be passed through by means of photomask 62 The part of the reservation of the layer 31 of electricity etches flat raceway groove 51, so as in the source region 3 of the partially exposed table top 20 of middle section.Fig. 6 Show the structure 100 after photomask 62 removes again.Among other forms of implementation, formed grid 12,12a it The preceding dielectric typically even removed again before formation dielectric medium area 33 among deep raceway groove 50,50a on table top 20 The layer 31 of matter.
Now, flat raceway groove 51 can become deeper by other etching step, so that the flat energy of raceway groove 51 Body region 2 is enough extended up to by source region 3 or even extends partly into body region 2, but is typically not extended to drift region 1 Among.
Replace, flat raceway groove 51 can also pass through interlevel dielectric matter 9, dielectric layer 31 and source region among etching step 3 etch.
As arrow by a dotted line is shown in the figure 7, nowadays p-type (such as boron) dopant material is from top side 103 Body region 2 and/or drift region 1 are injected by flat raceway groove 51.When replacement n-channel field-effect semiconductor component manufactures p-channel During field-effect semiconductor component, the doping of shown n and p-type doped region can mutually change and the n in this step Type (such as phosphorus) dopant material can be injected from top side 103.
Wherein, also a variety of injections can be realized in different depth, wherein, a variety of injections at least one of can be real Present first pn-junction 14 slightly above or in its lower section, that is to say, that first pn-junction 14, example are surrounded in vertical scope As corresponded to height hM10%.
It is typically capable of performing one to injecting three times according to the difference of the vertical depth of flat raceway groove 51.So in phase It is enough to p injections among the raceway groove 51 of depth, typically realizes so high doping in addition so that neighbouring corresponding flat ditch The region (after warming) in road 51 also can be implemented as body contact region (see also Figure 1B).In addition, replace half The flat raceway groove 51 extended among conductor main body 40 can also carry out multiple p injections.
Ensuing heating step will cause the activation of injected dopant material, so that the first pn-junction 14 is in depth Raceway groove 50, extend deeper into vertically among the first semiconductor layer 1 among the central region 2c between 50a, compared to such as Shown in Fig. 8 at the side wall 21 of semiconductor mesa 20 or its nearby for.The dopant material being capable of root during heating step According to Bu Tong deeper diffusing at least in part among the first semiconductor layer 1 for temperature, semi-conducting material and dopant material.The liter Warm step can for example be embodied as so-called " rapid thermal annealing " process.
Because the control at table top 20 is among Part II region 2b realization under any circumstance only for mixing The distribution of miscellaneous material makes less contribution, so will implement this method with very small technique change.
This method is typically so carried out so that in being separated by the side wall 21 of corresponding semiconductor mesa 20 Doping concentration among the region 2c of centre rises on corresponding first pn-junction 14 or nearby.
Typically, this method is so implemented so that in top side 103 and first pn-junction 14 and the corresponding phase of side wall 21 The first distance of maximum vertically between the first adjacent segmentation is less than corresponding second in the top side 103 and first pn-junction 14 Maximum vertical second distance between segmentation, this corresponding second is separately positioned on multiple the first of first pn-junction 14 Between two in segmentation.Typically, the vertical second distance of the maximum is in vertical distance (hM) about 80% to about Between 150%, but according to the different of component level or even it can be more than or less than selected.In addition, this method can So it is carried out so that the first pn-junction 14 and the first table among the central region 2c of corresponding semiconductor mesa 20 Between face 101 maximum vertical distance (| d1-hM|) it is less than the height h of the semiconductor mesa 20M30%, more typically Less than 20% or even less than 10%.As being illustrated above with reference to Figure 1A to Fig. 2, the first pn-junction 14 can extend into phase Among the central region 2c answered and it can also extend deeper among the drift region 1.
Now, such as can be optional by separating conductive material (such as metal or poly- silicon of conducting) and another kind Planarization process produces raceway groove contact and the generating source metal level 10 on first surface 101 in flat raceway groove 51.In addition, It is optionally able to form silicide at the side wall of flat raceway groove 51 and/or bottom wall.
Fig. 9 shows MOSFET 100, thereafter the overleaf generation leakage metal level 11 and wafer 40 is along more on 102 Wide deep raceway groove 50a is divided into single semiconductor component.
It can be generated by means of described method highly reliably and with relatively low technique change with body region 2 Avalanche breakdown type semiconductor component 100,200, they respectively have centrally disposed region 2c among Part II region 2b, it forms a part for pn-junction 14 and with higher maximum dopant concentration and/or than the body region 2 with drift region 1 The Part I region 2a adjacent with Part II region 2b is extended deeper among drift region 1.
Although the invention discloses different exemplary forms of implementation, it can be entered for professional The different change of row or modification be it will be apparent that by means of such change and modification can reach the present invention some are excellent Point is without being thereby deviating from the spirit and scope of the invention.In addition, using the other parts for realizing identical function come corresponding Replaced for common professional and obvious in ground.As can be seen here, illustrated with reference to specific accompanying drawing Feature can be mutually combined with the feature of other accompanying drawings, that is to say, that these features are not stated in some cases. The modification of such design for the present invention should be summarized by appended claims.
Concept spatially such as " under ", " following ", " following ", " on ", " above " and the like will have Used beneficial to more preferable description, to describe relative position of the element with respect to the second element.These concepts should Include the different directions of the component in addition to different directions described in the accompanying drawings.In addition, such as " first ", " the Two " also be used to describe different elements, region, scope etc. and are similarly not limited to such statement.Whole Identical conceptual description identical element in individual specification.
In language use in this, concept " having ", " containing ", "comprising", " comprising " and such generally comprise The existing concept of shown element either feature is but it is not excluded that extra element or feature.Article "one" and "the" should include plural number and odd number, as long as not within a context it is clear and definite additionally provided if.
In view of modification and application field above can be derived that：The present invention by foregoing specification or will not will not both lead to Accompanying drawing is crossed to be any limitation as.In contrast, the present invention is subject to only by claims below and its legal equivalents Limitation.

Claims (20)

1. a kind of field-effect component (100), it includes semiconductor body (40), the semiconductor body edge region (120) The surface (101) of the semiconductor body (40) is extended to from the back side (102), wherein, the fringe region (120) extends to institute The vertically oriented side (41) of semiconductor body (40) is stated, the side (41) extends to described from the back side (102) Surface (101), and the semiconductor body includes semiconductor mesa (20), and the semiconductor mesa is with perpendicular to the back side (102) and/or the vertical direction of the surface (101) extends to a height being placed on the surface (101) (hM) place semiconductor mesa top side (103), wherein, the semiconductor body (40) also includes in vertical cross section：
- drift region (1), the drift region at least extend to the surface (101) in the fringe region and partly pacified Put among the semiconductor mesa (20)；And
- the body region (2) being at least partially located among the semiconductor mesa (20), the body region and the drift region (1) the first pn-junction (14) is formed, first pn-junction extends between two side walls (21) of the semiconductor mesa (20), its In, vertical range (d) of first pn-junction (14) in the horizontal direction from the semiconductor mesa top side (103) can change simultaneously And using maximum value (d in the middle section (2c) separated by two side walls (21)1), and wherein, the maximum value (d1) it is at least the height (hM) 70%.
2. field-effect component (100) according to claim 1, wherein, the maximum value (d1) it is less than the height (hM) 200%.
3. field-effect component (100) according to any one of the preceding claims, wherein, the body region (2) has peace The Part II region (2b) in the middle section (2c) is put, the Part II region is formed with the drift region (1) A part for first pn-junction (14) and there is the Part I region more adjacent than with the Part II region (2b) (2a) higher maximum dopant concentration.
4. field-effect component (100) according to claim 1 or 2, wherein, first pn-junction (14) is described vertical On vertical axle it is specular or asymmetry in cross section.
5. field-effect component (100) according to claim 3, wherein, the semiconductor mesa (20) is described vertical There is another to be placed in the source region (3) on the body region (2), the source region is formed with the body region (2) in cross section Second pn-junction (15).
6. field-effect component (100) according to claim 5, also more including being placed among the vertical cross section Gate dielectric region (30,33) at least one in individual side wall (21), it is placed on the gate dielectric region (33) Grid (12), it is placed in being contacted with the body region (2) and the source region (3) ohm formula on the semiconductor body (40) Source metal level (10) and/or the leakage metal level contacted with the drift region (1) ohm formula being placed on the back side (102) (11)。
7. field-effect component (100) according to claim 6, wherein, the source metal level (10) and the grid (12) It is placed on the surface (101).
8. the field-effect component (100) according to claim 6 or 7, wherein, the semiconductor body (40) is additionally included in institute The side (41) extended between the back side (102) and the surface (101) and at least one edge closure structure (12b) are stated, it is described Edge closure structure is placed in top view between the semiconductor mesa (20) and the side (41).
9. the field-effect component (100) according to claim 6 or 7, in addition to flat raceway groove (51), the raceway groove is described The body region (2) is extended into from the semiconductor mesa top side (103) and/or extend to the main body in middle section (2c) The Part I region (2a) in area (2).
10. field-effect component (100) according to claim 1 or 2, wherein, the semiconductor body (40) is in activation Region (110) has multiple semiconductor mesas (20).
11. field-effect component (100) according to claim 10, also includes temperature in the region of the activation (110) Sensor, current sensor and/or grid refer to.
12. field-effect component (100) according to claim 10, also include in the region of the activation (110) another Individual semiconductor mesa (20), another described semiconductor mesa include body region (2), the body region and the drift region (1) Pn-junction (14) is formed, wherein, the body region (2) of another semiconductor mesa (20) is on vertical direction and described in discord The body region (2) of semiconductor mesa (20) equally extends into the drift region (1) deeply.
13. a kind of field-effect component (100), including semiconductor body (40), the semiconductor body edge region (120) from The back side (102) extends to surface (101), wherein, the fringe region (120) extends to the vertical of the semiconductor body (40) The side (41) of ground orientation, the side (41) extends to the surface (101) from the back side (102), and described partly leads Phosphor bodies include semiconductor mesa (20), and the semiconductor mesa is with the normal vector (e parallel to the back side (102)n) and/or Normal vector (the e of the surface (101)n) vertical direction extend to the semiconductor platform being placed on the surface (101) Face top side (103), wherein, the semiconductor body (40) also includes in vertical cross section：
- drift region (1), the drift region at least extend to the surface (101) in the fringe region and partly pacified Put among the semiconductor mesa (20)；And
- the body region (2) being at least partially located among the semiconductor mesa (20), the body region include two difference With an adjacent Part I region (2a) in two side walls (21) of the semiconductor mesa (20) and at two first The Part II region (2b) disposed between subregion (2a), wherein, described two Part I regions (2a) and described Two subregions (2b) form the first pn-junction (14) with the drift region (1), and first pn-junction is in the semiconductor mesa (20) extend between two side walls (21), wherein, the Part II region (2b) is in the drift region (1) vertically than institute State two Part I regions (2a) deeper to be extended, and wherein, the Part II region (2b) has than described The bigger maximum dopant concentration of two Part I regions (2a).
14. field-effect component (100) according to claim 13, wherein, in the semiconductor mesa top side (103) and institute State one in described two Part I regions (2a) of the first pn-junction (14) is formed between the drift region (1) Maximum vertical first distance (d between one segmentation2) be less than on the semiconductor mesa top side (103) and the surface (101) the vertical distance (h betweenM), and/or wherein, in the semiconductor mesa top side (103) and first pn-junction (14) it is maximum vertical between the formed between the Part II region (2b) and the drift region (1) second segmentation Second distance (d1) it is in the vertical distance (hM) 80% to 150% scope among.
15. one kind is used for the method for manufacturing field-effect component (100), including：
- wafer (40) is provided, the first semiconductor layer (1) of the wafer including the first power type, it is placed in described the first half The second semiconductor layer (2) of the second power type on conductor layer (1) and it is placed on second semiconductor layer (2) 3rd semiconductor layer (3), second semiconductor layer and first semiconductor layer (1) form the first pn-junction (14), and described the Three semiconductor layers form the second pn-junction (15) with second semiconductor layer (2) and extend to the top side of the wafer (40) (103)；
- the table top mask (7) with multiple openings is formed on the top side (103) of the wafer (40)；
- wafer (40) etched by the table top mask (7) so that produce multiple deep raceway grooves (50,50a) and placement Multiple semiconductor mesas (20) between the multiple deep raceway groove (50,50a), wherein, the multiple deep raceway groove (50, 50a) extend into first semiconductor layer (1)；And
- injection of the dopant of first power type is at least one with the adjacent semiconductor region of first pn-junction (14) Domain.
16. according to the method for claim 15, be additionally included in the multiple deep raceway groove (50) at least several it It is middle to form the grid (12,33) of insulation, and/or the multiple of the top side (103) are formed among the semiconductor mesa (20) Flat raceway groove (51).
17. the method according to claim 15 or 16, it is additionally included among the semiconductor component along the multiple depth Raceway groove (50a) in several separate the wafer (40).
18. the method according to claim 15 or 16, in addition to temperature adjustment step, wherein, there is provided there is the to be parallel to each other The wafer (40) of one pn-junction (14) and the second pn-junction (15), and wherein, methods described is so implemented so that described One pn-junction (14) after the temperature adjustment step the multiple semiconductor mesa (20) it is at least one among in middle section Vertically than extending deeper into described the first half in the side wall (21) of at least one semiconductor mesa (20) in (2c) Conductor layer (1).
19. the method according to claim 15 or 16, methods described are so carried out so that are partly led the multiple Object table face (20) it is at least one in the center that multiple side walls (21) by least one semiconductor mesa (20) separate Doping concentration in region (2c) is brought up on first pn-junction (14).
20. according to the method for claim 18, wherein, methods described is so carried out so that described the first half lead Body layer (1) forms first surface (101) outside the semiconductor mesa (20), and the first surface is located at from the top side (103) vertical distance (hM) place, wherein, the top side (103) and first pn-junction (14) with it is the multiple The first vertical distance (d between the first adjacent segmentation of the side wall (21) of one in semiconductor mesa (20)2) be less than Second segmentation adjacent with the first segmentation of first pn-junction (14) of the top side (103) and first pn-junction (14) Between vertical second distance (d1), and the first distance (d2) be in the top side (103) and the first surface (101) the vertical distance (h betweenM) 80% to 150% scope among.
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US9391192B2 (en) 2016-07-12
US9847387B2 (en) 2017-12-19
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CN108231868B (en) 2022-01-14
US20150115353A1 (en) 2015-04-30

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