CN107785274A - A kind of method for improving flash memory programming efficiency - Google Patents
A kind of method for improving flash memory programming efficiency Download PDFInfo
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- CN107785274A CN107785274A CN201711099985.8A CN201711099985A CN107785274A CN 107785274 A CN107785274 A CN 107785274A CN 201711099985 A CN201711099985 A CN 201711099985A CN 107785274 A CN107785274 A CN 107785274A
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- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000002955 isolation Methods 0.000 claims abstract description 30
- 238000001259 photo etching Methods 0.000 claims abstract description 24
- 230000008859 change Effects 0.000 claims abstract description 18
- 238000001039 wet etching Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 239000000725 suspension Substances 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000003628 erosive effect Effects 0.000 claims 1
- 238000002347 injection Methods 0.000 abstract description 20
- 239000007924 injection Substances 0.000 abstract description 20
- 230000005684 electric field Effects 0.000 abstract description 8
- 238000007667 floating Methods 0.000 description 19
- 230000008569 process Effects 0.000 description 14
- 239000002784 hot electron Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 7
- 238000012545 processing Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention discloses a kind of method for improving flash memory programming efficiency, the method for improving flash memory programming efficiency, it is the gate oxide pattern by changing the edge of shallow trench isolation, so that the gate oxide pattern is the structure of stepped setting, or the structure in concave shape setting, to improve the electric field of shallow groove isolation edge, and then improve thermoelectron injection.The method that the present invention improves flash memory programming efficiency, by carrying out active area photoetching and wet etching, to change the pattern of the gate oxide, the gate oxide part at the edge of shallow trench isolation is removed, the thickness of edge gate oxide is thinned, the electric field of shallow groove isolation edge is not only improved, and then improves thermoelectron injection, and reduces operating voltage when programming.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of method for improving flash memory programming efficiency.
Background technology
Nonvolatile storage using flash memory as representative can be wiped because of the data retention under its powering-off state and repeatedly
The advantages that writing data is widely used in various products, for example, mobile phone, notebook, palm PC and solid state hard disc etc. storage and
Communication apparatus.Wherein, NOR flash memory is deposited because the code that its random read take speed is fast and is widely used in the mobile terminals such as mobile phone
Store up in chip.
The programming of NOR flash memory is mainly injected by thermoelectron.Programming can not only be improved by improving thermoelectron injection efficiency
Efficiency, while the operating voltage of grid can also be reduced, disturbed so as to reduce caused by grid.Publication No.
A kind of compiling machine of US5300803 A U.S. Patent Publication is SSI (Source Side Injection) non-volatile storage
Device structure, the patent solve the problems, such as the inefficient injection of floating gate flash memory device and high power consumption.The background technology of the patent is situated between
Continued traditional floating gate flash memory device, to ensure high channel hot electron generation rate and high thermoelectron injection efficiency, in drain terminal
Apply high voltage with grid, electronics flows to drain electrode from source electrode and accelerates to produce thermoelectron, portion under the effect of vicinity high electric field
Divide thermoelectron to enter floating boom through the oxide layer below floating boom, complete programming operation.But this traditional floating gate flash memory device band
The problem of channel hot electron injection efficiency is low and current power dissipation is big is carried out.To solve the problem, the patent proposes one kind
Point row flash memory in grating device, the grid of left and right are control gate, and the grid on right side is floating boom, and floating boom and control gate spatially stagger row
Row, wherein, floating boom applies high voltage, and control gate applies low-voltage, and drain terminal applies high voltage.Due to reducing control-grid voltage,
Cause the inversion charge number of sensing less, shorten the distance of electronics acceleration, reduce thermionic number so that programming electricity
Stream is reduced, while adds the electronics of injection floating boom, therefore improves channel hot electron injection efficiency, and drops current power dissipation
It is low.
But the technical scheme in the patent has another problem, because the voltage ratio that drain terminal applies is higher, cause to leak
The depletion width that end extends to substrate is bigger, and source and depletion region are led together with being easy to touch in case of high pressures
Device break-through and failure are caused, that is, produces channel punchthrough effect (Channel Punch through effect), is source and leakage
A kind of phenomenon that the depletion region at end is connected, this defect often limit flush memory device carried out in technique technology node upgrading and
The diminution of critical size.
With the development of semiconductor technology, flash memory market occupation rate more and more higher.For traditional grid flash memory device, one
As programming be use hot electron programming, and erasing be by F-N tunnels.For flush memory device, the programming of flash memory how is improved
Efficiency, while the research that can reduce the operating voltage of flash memory again has great significance.
Therefore the problem of existing for prior art, this case designer is by the experience of the industry for many years is engaged in, actively research
Improvement, then there is a kind of method for improving flash memory programming efficiency of the invention.
The content of the invention
The present invention be directed in the prior art, not only channel hot electron injection efficiency is low for traditional floating gate flash memory device,
And current power dissipation it is big the defects of provide it is a kind of improve flash memory programming efficiency method.
To realize the purpose of the present invention, the present invention provides a kind of method for improving flash memory programming efficiency, the raising flash memory
The method of programming efficiency, it is the gate oxide pattern by changing the edge of shallow trench isolation so that the gate oxide pattern
For the structure of stepped setting, or the structure in concave shape setting.
Alternatively, the gate oxide apart from the edge of the shallow trench isolation distance according to the shallow trench isolation electricity
Characteristic is learned to determine.
Alternatively, the change of the pattern of the gate oxide is realized by active area photoetching and wet-etching technology.
Alternatively, by active area photoetching and wet etching, the gate oxide part at the edge of shallow trench isolation is removed,
The thickness of edge gate oxide is thinned.
Alternatively, the method for improving flash memory programming efficiency, including：
Perform step S1：Silicon-based substrate, and the oxide layer to being arranged in the silicon-based substrate, silicon nitride layer are provided, and
Silicon-based substrate progress shallow ridges is groove etched, to form shallow trench isolation；
Perform step S2：Shallow trench isolating oxide layer is formed to the shallow trench isolation oxidation, and is filled, shallow trench
Planarization process；
Perform step S3：Remove removing oxide layer and silicon nitride layer；
Perform step S4：Grid oxygen oxidation is carried out to the silicon-based substrate, forms gate oxide；
Perform step S5：Active area photoetching and wet etching are carried out, to change the pattern of the gate oxide；
Perform step S6：Polysilicon deposit is carried out on the gate oxide of the pattern change, to form suspension gate layer.
Alternatively, the method for improving flash memory programming efficiency further comprises forming control gate, and is formed and be arranged on
Grid oxygen dielectric layer between the suspension gate layer and control gate.
Alternatively, in step s3, silicon nitride layer is removed by wet processing completely.
Alternatively, in step s 4, the gate oxide is grown by boiler tube dry-oxygen oxidation technique.
Alternatively, in step s 5, change the pattern of the gate oxide, be by using photolithography plate, photoresist, to tool
The active area for having source, drain terminal, grid carries out photoetching and wet etching and obtained.
Alternatively, photoetching only develops drain terminal, the covering of source photoresist.
In summary, the method that the present invention improves flash memory programming efficiency, by carrying out active area photoetching and wet etching, with
Change the pattern of the gate oxide, the gate oxide part at the edge of shallow trench isolation is removed, edge gate oxide is thinned
Thickness, in programming process, thermoelectron is easier tunnel, not only improve shallow groove isolation edge electric field, and then improve heat
Electron injection, and reduce operating voltage when programming.
Brief description of the drawings
Fig. 1~Fig. 6 show the technological process stage structural representation that the present invention improves the method for flash memory programming efficiency；
Fig. 7 (a) show the first embodiment flush memory device knot for realizing the method that the present invention improves flash memory programming efficiency
Composition；
Fig. 7 (b) show the second embodiment flush memory device knot for realizing the method that the present invention improves flash memory programming efficiency
Composition；
The first embodiment that Fig. 8 (a)~Fig. 8 (b) show the method for improving flush memory device programming efficiency increases photoetching newly
Process structure schematic diagram；
The second embodiment that Fig. 9 (a)~Fig. 9 (b) show the method for improving flush memory device programming efficiency increases photoetching newly
Process structure schematic diagram.
Embodiment
To describe technology contents, construction feature, institute's reached purpose and effect of the invention in detail, below in conjunction with reality
Apply example and coordinate accompanying drawing to be described in detail.
Nonvolatile storage using flash memory as representative can be wiped because of the data retention under its powering-off state and repeatedly
The advantages that writing data is widely used in various products, for example, mobile phone, notebook, palm PC and solid state hard disc etc. storage and
Communication apparatus.Wherein, NOR flash memory is deposited because the code that its random read take speed is fast and is widely used in the mobile terminals such as mobile phone
Store up in chip.
The programming of NOR flash memory is mainly injected by thermoelectron, and programming can not only be improved by improving thermoelectron injection efficiency
Efficiency, while the operating voltage of grid can also be reduced, disturbed so as to reduce caused by grid.Publication No.
A kind of compiling machine of US5300803 A U.S. Patent Publication is SSI (Source Side Injection) non-volatile storage
Device structure, the patent solve the problems, such as the inefficient injection of floating gate flash memory device and high power consumption.The background technology of the patent is situated between
Continued traditional floating gate flash memory device, to ensure high channel hot electron generation rate and high thermoelectron injection efficiency, in drain terminal
Apply high voltage with grid, electronics flows to drain electrode from source electrode and accelerates to produce thermoelectron, portion under the effect of vicinity high electric field
Divide thermoelectron to enter floating boom through the oxide layer below floating boom, complete programming operation.But this traditional floating gate flash memory device band
The problem of channel hot electron injection efficiency is low and current power dissipation is big is carried out.To solve the problem, the patent proposes one kind
Point row flash memory in grating device, the grid of left and right are control gate, and the grid on right side is floating boom, and floating boom and control gate spatially stagger row
Row, wherein, floating boom applies high voltage, and control gate applies low-voltage, and drain terminal applies high voltage.Due to reducing control-grid voltage,
Cause the inversion charge number of sensing less, shorten the distance of electronics acceleration, reduce thermionic number so that programming electricity
Stream is reduced, while adds the electronics of injection floating boom, therefore improves channel hot electron injection efficiency, and drops current power dissipation
It is low.
But the technical scheme in the patent has another problem, because the voltage ratio that drain terminal applies is higher, cause to leak
The depletion width that end extends to substrate is bigger, and source and depletion region are led together with being easy to touch in case of high pressures
Device break-through and failure are caused, that is, produces channel punchthrough effect (Channel Punch through effect), is source and leakage
A kind of phenomenon that the depletion region at end is connected, this defect often limit flush memory device carried out in technique technology node upgrading and
The diminution of critical size.
With the development of semiconductor technology, flash memory market occupation rate more and more higher.For traditional grid flash memory device, one
As programming be use hot electron programming, and erasing be by F-N tunnels.For flush memory device, the programming of flash memory how is improved
Efficiency, while the research that can reduce the operating voltage of flash memory again has great significance.
Fig. 1~Fig. 6, Fig. 7 (a), Fig. 7 (b) are referred to, Fig. 1~Fig. 6 show the side that the present invention improves flash memory programming efficiency
The technological process stage structural representation of method.Fig. 7 (a), which is shown, realizes the of the method that the present invention improves flash memory programming efficiency
One embodiment flash memory device structure figure.Fig. 7 (b) show the second reality for realizing the method that the present invention improves flash memory programming efficiency
Apply mode flash memory device structure figure.In order to improve the programming efficiency of flash memory, while the operating voltage of flash memory is reduced, in the present invention
In, the method for improving flash memory programming efficiency, is the gate oxide pattern by changing the edge of shallow trench isolation, to improve
The electric field of shallow groove isolation edge, and then improve thermoelectron injection.Without limitation, for example, the gate oxide pattern be in
The structure of stepped setting, or the structure in concave shape setting.The gate oxide is apart from the edge of the shallow trench isolation
Distance according to the shallow trench isolation electrology characteristic determine.As embodiment, the pattern of the gate oxide changes
Becoming can be realized by active area photoetching and wet-etching technology.That is, by active area photoetching and wet etching, shallow trench is isolated
Edge gate oxide part remove, be thinned edge gate oxide thickness, in programming process, thermoelectron be easier then
Wear.
In order to more intuitively disclose the technical scheme of the present invention, the beneficial effect of the present invention is highlighted, in conjunction with specific implementation
Exemplified by mode, the processing step and operation principle of the method for the raising flash memory programming efficiency are illustrated.It is being embodied
In mode, the processing step, it is only to enumerate that the shape of component, size, position, which are set etc., is not construed as to the technology of the present invention
The limitation of scheme.
First embodiment
Please continue to refer to Fig. 1~Fig. 6, and combine and refer to Fig. 7 (a), Fig. 8 (a)~Fig. 8 (b), shown in Fig. 8 (a)~Fig. 8 (b)
Photoetching process structural representation is increased newly to improve the first embodiment of the method for flush memory device programming efficiency.Without limitation,
In the first embodiment, the gate oxide pattern is the structure of stepped setting.It is described to carry as embodiment
The method of high flush memory device programming efficiency, including：
Perform step S1：Silicon-based substrate 10, and the oxide layer 20 to being arranged in the silicon-based substrate 10, silicon nitride are provided
Layer 30, and the progress shallow ridges of silicon-based substrate 10 are groove etched, to form shallow trench isolation；
Perform step S2：Shallow trench isolating oxide layer 40 is formed to the shallow trench isolation oxidation, and is filled, shallow ridges
Groove planarization process；
Perform step S3：Remove removing oxide layer 20 and silicon nitride layer 30；
Perform step S4：Grid oxygen oxidation is carried out to the silicon-based substrate 10, forms gate oxide 50；
Perform step S5：Active area photoetching and wet etching are carried out, to change the pattern of the gate oxide 50；
Perform step S6：Polysilicon deposit is carried out on the gate oxide 50 of the pattern change, to form suspension gate layer
60。
As those skilled in the art, it is readily appreciated that ground, in step s3, such as can go to denitrogenate completely by wet processing
SiClx layer 30.In step s 4, the gate oxide 50 can be grown by boiler tube dry-oxygen oxidation technique.In addition, in step s 5,
Change the pattern of the gate oxide 50, be by using photoresist 70, photolithography plate 80, to source 91, drain terminal 92, grid
93 active area carries out photoetching and wet etching and obtained.More specifically, in the first embodiment, to obtain stepped set
The gate oxide structure for the structure put, source are photo-etched glue 70 and covered, and drain terminal 92 develops.
Meanwhile further comprise can be by the control gate 61 that traditional handicraft is formed for the flush memory device, and it is arranged on
Grid oxygen dielectric layer 62 between the suspension gate layer 60 and control gate 61.
Second embodiment
Succinct for the ease of describing, second embodiment is compiled with first embodiment identical structure using identical numeral
Number, same process uses same steps, again not with repeating.
Please continue to refer to Fig. 1~Fig. 6, and combine and refer to Fig. 7 (b), Fig. 9 (a)~Fig. 9 (b), shown in Fig. 9 (a)~Fig. 9 (b)
Photoetching process structural representation is increased newly to improve the second embodiment of the method for flush memory device programming efficiency.Without limitation,
In this second embodiment, the gate oxide pattern is the structure in concave shape setting.It is described to carry as embodiment
The method of high flush memory device programming efficiency, including：
Perform step S1：Silicon-based substrate 10, and the oxide layer 20 to being arranged in the silicon-based substrate 10, silicon nitride are provided
Layer 30, and the progress shallow ridges of silicon-based substrate 10 are groove etched, to form shallow trench isolation；
Perform step S2：Shallow trench isolating oxide layer 40 is formed to the shallow trench isolation oxidation, and is filled, shallow ridges
Groove planarization process；
Perform step S3：Remove removing oxide layer 20 and silicon nitride layer 30；
Perform step S4：Grid oxygen oxidation is carried out to the silicon-based substrate 10, forms gate oxide 50；
Perform step S5：Active area photoetching and wet etching are carried out, to change the pattern of the gate oxide 50；
Perform step S6：Polysilicon deposit is carried out on the gate oxide 50 of the pattern change, to form suspension gate layer
60。
As those skilled in the art, it is readily appreciated that ground, in step s3, such as can go to denitrogenate completely by wet processing
SiClx layer 30.In step s 4, the gate oxide 50 can be grown by boiler tube dry-oxygen oxidation technique.In addition, in step s 5,
Change the pattern of the gate oxide 50, be by using photoresist 70, photolithography plate 80, to source 91, drain terminal 92, grid
93 active area carries out photoetching and wet etching and obtained.More specifically, in this second embodiment, set to obtain in concave shape
The gate oxide structure for the structure put, source are photo-etched glue 70 and covered, and drain terminal 92 develops.
Meanwhile further comprise can be by the control gate 61 that traditional handicraft is formed for the flush memory device, and it is arranged on
Grid oxygen dielectric layer 62 between the suspension gate layer 60 and control gate 61.
It is apparent that the method that the present invention improves flash memory programming efficiency, by carrying out active area photoetching and wet etching, to change
Become the pattern of the gate oxide 50, the part of gate oxide 50 at the edge of shallow trench isolation is removed, edge gate oxidation is thinned
The thickness of layer, in programming process, thermoelectron is easier tunnel, not only improves the electric field of shallow groove isolation edge, and then improve
Thermoelectron injects, and reduces operating voltage when programming.
In summary, the method that the present invention improves flash memory programming efficiency, by carrying out active area photoetching and wet etching, with
Change the pattern of the gate oxide, the gate oxide part at the edge of shallow trench isolation is removed, edge gate oxide is thinned
Thickness, in programming process, thermoelectron is easier tunnel, not only improve shallow groove isolation edge electric field, and then improve heat
Electron injection, and reduce operating voltage when programming.
Those skilled in the art, can be to this hair it will be appreciated that without departing from the spirit or scope of the present invention
Bright carry out various modifications and variations.Thus, if any modification or modification fall into the protection of appended claims and equivalent
In the range of when, it is believed that the present invention covers these modifications and variations.
Claims (10)
- A kind of 1. method for improving flash memory programming efficiency, it is characterised in that the method for improving flash memory programming efficiency, is to pass through Changing the gate oxide pattern at the edge of shallow trench isolation so that the gate oxide pattern is the structure of stepped setting, Or the structure in concave shape setting.
- 2. the method for flash memory programming efficiency is improved as claimed in claim 1, it is characterised in that the gate oxide is apart from described shallow The distance at the edge of trench isolations determines according to the electrology characteristic of the shallow trench isolation.
- 3. the method for flash memory programming efficiency is improved as claimed in claim 1, it is characterised in that the pattern of the gate oxide changes Become and realized by active area photoetching and wet-etching technology.
- 4. the method for flash memory programming efficiency is improved as claimed in claim 3, it is characterised in that carved by active area photoetching and wet method Erosion, the gate oxide part at the edge of shallow trench isolation is removed, the thickness of edge gate oxide is thinned.
- 5. the method for flash memory programming efficiency is improved as claimed in claim 1, it is characterised in that the raising flash memory programming efficiency Method, including：Perform step S1：Silicon-based substrate, and the oxide layer to being arranged in the silicon-based substrate, silicon nitride layer, and silicon substrate are provided Substrate progress shallow ridges is groove etched, to form shallow trench isolation；Perform step S2：To the shallow trench isolation oxidation formed shallow trench isolating oxide layer, and be filled, shallow trench it is flat Change is handled；Perform step S3：Remove removing oxide layer and silicon nitride layer；Perform step S4：Grid oxygen oxidation is carried out to the silicon-based substrate, forms gate oxide；Perform step S5：Active area photoetching and wet etching are carried out, to change the pattern of the gate oxide；Perform step S6：Polysilicon deposit is carried out on the gate oxide of the pattern change, to form suspension gate layer.
- 6. the method for flash memory programming efficiency is improved as claimed in claim 5, it is characterised in that the raising flash memory programming efficiency Method further comprises forming control gate, and forms the grid oxygen dielectric layer being arranged between the suspension gate layer and control gate.
- 7. the method for flash memory programming efficiency is improved as claimed in claim 5, it is characterised in that in step s3, pass through wet method work Skill removes silicon nitride layer completely.
- 8. the method for flash memory programming efficiency is improved as claimed in claim 5, it is characterised in that in step s 4, done by boiler tube Oxygen oxidation technology grows the gate oxide.
- 9. the method for flash memory programming efficiency is improved as claimed in claim 5, it is characterised in that in step s 5, change the grid The pattern of oxide layer, it is by using photolithography plate, photoresist, photoetching and wet is carried out to the active area with source, drain terminal, grid Method is etched and obtained.
- 10. the method for flash memory programming efficiency is improved as claimed in claim 5, it is characterised in that photoetching only develops drain terminal, source Photoresist covers.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5895240A (en) * | 1997-06-30 | 1999-04-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making stepped edge structure of an EEPROM tunneling window |
| CN1599071A (en) * | 2003-05-20 | 2005-03-23 | 三星电子株式会社 | EEPROM cell structures having non-uniform channel-dielectric thickness and methods of making the same |
| CN101399228A (en) * | 2007-09-27 | 2009-04-01 | 东部高科股份有限公司 | Semiconductor devices and method of fabricating the same |
-
2017
- 2017-11-09 CN CN201711099985.8A patent/CN107785274A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5895240A (en) * | 1997-06-30 | 1999-04-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making stepped edge structure of an EEPROM tunneling window |
| CN1599071A (en) * | 2003-05-20 | 2005-03-23 | 三星电子株式会社 | EEPROM cell structures having non-uniform channel-dielectric thickness and methods of making the same |
| CN101399228A (en) * | 2007-09-27 | 2009-04-01 | 东部高科股份有限公司 | Semiconductor devices and method of fabricating the same |
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