CN107769788A - A kind of multichannel DAC realizes circuit - Google Patents
A kind of multichannel DAC realizes circuit Download PDFInfo
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- CN107769788A CN107769788A CN201711285701.4A CN201711285701A CN107769788A CN 107769788 A CN107769788 A CN 107769788A CN 201711285701 A CN201711285701 A CN 201711285701A CN 107769788 A CN107769788 A CN 107769788A
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- dac
- fpga
- operational amplifier
- resistance
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/662—Multiplexed conversion systems
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a kind of multichannel DAC to realize circuit, including FPGA：For the generation equipment of DAC data, there is at least two data/control output end on FPGA, FPGA each data/control output end produces by the single logic circuits of FPGA, and FPGA each data/control output end is all connected with a DAC data/control signal, and FPGA carries out parallel data processing；DAC；RC low pass filters；It is single-ended to differential converter.The present invention passes through above-mentioned principle, set single-ended to differential converter, avoid because amplifier non-essential resistance resistance has fine error, each passage is unable to reach the uniformity of output signal in actual applications, the defects of crosstalk caused by resistance difference can cause larger workload when the later stage debugs and calibrates to commissioning staff, several times of the even existing DAC passages of multichannel DAC passages of the program, also can guarantee that the uniformity of output signal.
Description
Technical field
The present invention relates to electronic technology field, and in particular to a kind of multichannel DAC realizes circuit.
Background technology
In current existing 6U CPCI or CPCIe systems, majority is realized more by the way of FPGA and multichannel DAC
Road digital-to-analogue conversion, and basic ideas are connected to DAC data input pin, DAC using FPGA data output end
Output is connected to amplifier, conversion of the single-ended signal to differential signal is realized by amplifier non-essential resistance, due to amplifier non-essential resistance
There is fine error in resistance, each passage is unable to reach the uniformity of output signal in actual applications, caused by resistance difference
Crosstalk can cause larger workload when the later stage debugs and calibrates to commissioning staff, should due to having the drawback that
Circuit arrangement DAC in actual product port number can't be too many.
The content of the invention
The technical problems to be solved by the invention are increase DAC numbers of channels, and it is an object of the present invention to provide a kind of multichannel DAC is real
Existing circuit, setting is single-ended to differential converter, avoids the occurrence of because amplifier non-essential resistance resistance has fine error, in reality
Each passage is unable to reach the uniformity of output signal in the application of border, and crosstalk caused by resistance difference is debugged in the later stage and school
The defects of larger workload can be caused to commissioning staff on time, the even existing DAC passages of multichannel DAC passages of the program
Several times, it also can guarantee that the uniformity of output signal.
The present invention is achieved through the following technical solutions：
A kind of multichannel DAC realizes circuit, including
FPGA：For the generation equipment of DAC data, there are at least two data/control output end, FPGA each data/control on FPGA
Output end processed produces by the single logic circuits of FPGA, and FPGA each data/control output end is all connected with a DAC number
According to/control signal, FPGA carries out parallel data processing；
DAC：Pin is enabled with loading, including at least two DAC, each DAC include 4 digital-to-analogues
ALT-CH alternate channel, each DAC is by signal output to RC low pass filter inputs；
RC low pass filters：Identical with DAC quantity, RC low pass filters rear end is also connected with single-ended to differential signal conversion
Device；
It is single-ended to differential converter：Integrated resistor is located inside difference integrated transporting discharging, identical with DAC quantity.
This programme employs the resistance inside difference integrated transporting discharging to avoid above mentioned problem, using single-ended to differential signal turn
Parallel operation, DAC output signal are defeated by single-ended one to differential converter after the filtering of RC low pass filters
Entrance enters, and after first passing through integrated resistor, then exports two paths of signals after passing to two operational amplifiers processing below, without
It is as DAC output signal realizes single-ended signal extremely by non-essential resistance again after first passing through operational amplifier in the prior art
The conversion of differential signal, avoid the occurrence of because amplifier non-essential resistance resistance has fine error, in actual applications each passage
The uniformity of output signal is unable to reach, crosstalk caused by resistance difference can give commissioning staff when the later stage debugs and calibrates
The defects of causing larger workload.
DAC, which has, in this programme loads enabled pin, and FPGA device realizes the parallelization processing of program, each
Data/control of DAC, produced by the single logic circuits of FPGA；The single logics of FPGA are united by host computer
One control and data interaction；The data of each DAC enter line function generation by single DDS in FPGA；Make each logical
The DAC data in road can be sent simultaneously, improve the processing speed of data.This programme realizes the synchronization of multichannel DAC outputs, and DAC is defeated
Going out signal avoids the later stage caused by crosstalk from demarcating and debug the defects of difficult, and data are total between FPGA and DAC
Line connection is simple, and the uniformity of multichannel DAC output signals is good.Each DAC possesses 4 dac channels, the present invention
Possess 8 identical digital analog converters, possess 32 dac channels altogether, so allow for while 32 road signals can be entered
Row conversion, conversion speed greatly improve.Each dac channel is using modularization, Hierarchical Design, each analog channel parameter
It is consistent, facilitates commissioning staff's later stage to debug and calibrate.
Preferably, each dac channel of DAC using identical design, and carry out modularized design and
The parameter of each dac channel is consistent.Ensure the consistent of each multi-channel output signal, facilitate commissioning staff's later stage debug and
Calibration, greatly reduce the workload of debugging and calibration.
Preferably, each dac channel output of DAC is differential signal.
Preferably, each dac channel of DAC possesses identical signal condition function.
Preferably, the data of each DAC enter line function generation by single DDS in FPGA.
Preferably, the single logic circuits of FPGA are uniformly controlled and data interaction by host computer.
Preferably, the RC low pass filters include resistance R, electric capacity C and operational amplifier B, and resistance R one end is low pass filtered
Ripple device input a, resistance R other end concatenation operation amplifiers B inverting input, in operational amplifier B inverting input
On be also connected with pulling down electric capacity C, operational amplifier B in-phase input end is connected with exporting, and operational amplifier B output end is low pass
The output end b of wave filter.
Preferably, it is described single-ended to include operational amplifier B1 and operational amplifier B2, computing to differential converter and put
Big device B1 inverting input connection pull down resistor R1, operational amplifier B1 in-phase input end connection resistance R3 one end, resistance
The R3 other ends are single-ended to differential converter input a1, are also connected between operational amplifier B1 inverting input and output end
Resistance R2, operational amplifier B1 output end are single-ended to differential converter output plus terminal b1, and operational amplifier B2's is anti-phase defeated
Enter end connection resistance R4 one end, the resistance R4 other ends are single-ended to differential converter input a1, and operational amplifier B2's is anti-phase
Resistance R6, operational amplifier B2 in-phase input end connection pull down resistor R5 are also connected between input and output end, computing is put
Big device B2 output end is to be single-ended to differential converter output negative terminal.The circuit is unlike the output letter of DAC in the prior art
Conversion of the single-ended signal to differential signal is realized by non-essential resistance again after number first passing through operational amplifier, is avoided the occurrence of due to fortune
Put non-essential resistance resistance and fine error be present, each passage is unable to reach the uniformity of output signal, resistance in actual applications
The defects of crosstalk caused by difference can cause larger workload when the later stage debugs and calibrates to commissioning staff.
The present invention compared with prior art, has the following advantages and advantages：
1st, this programme of the present invention employs the resistance inside difference integrated transporting discharging to avoid above mentioned problem, using single-ended to difference letter
Number converter, DAC output signal is after the filtering of RC low pass filters, by single-ended to the one of differential converter
Individual input port enters, and after first passing through integrated resistor, then exports two paths of signals after passing to two operational amplifiers processing below,
Avoid the occurrence of because amplifier non-essential resistance resistance has fine error, each passage is unable to reach output signal in actual applications
Uniformity, crosstalk caused by resistance difference the later stage debug and calibrate when larger workload can be caused to commissioning staff
The defects of.
2nd, DAC has the enabled pin of loading in the present invention, and FPGA device realizes the parallelization processing of program, each
Data/control of DAC, produced by the single logic circuits of FPGA；The single logics of FPGA are united by host computer
One control and data interaction；The synchronization of multichannel DAC outputs is realized, DAC output signals avoid the later stage caused by crosstalk from marking
Fixed and debug the defects of difficult, data/address bus connection is simple between FPGA and DAC, multichannel DAC output signals it is consistent
Property is good.
3rd, each dac channel of DAC is designed using identical in the present invention, and is carried out modularization and set
The parameter of meter and each dac channel is consistent；Ensure the consistent of each multi-channel output signal, facilitate commissioning staff's later stage to adjust
Examination and calibration, greatly reduce the workload of debugging and calibration.
Brief description of the drawings
Accompanying drawing described herein is used for providing further understanding the embodiment of the present invention, forms one of the application
Point, do not form the restriction to the embodiment of the present invention.In the accompanying drawings：
Fig. 1 is schematic structural view of the invention;
Fig. 2 is RC low pass filter electrical schematic diagrams；
Fig. 3 is single-ended to differential conversion electrical schematic diagram.
Mark and corresponding parts title in accompanying drawing：
1-FPGA, 2-DAC converter, 3-RC low pass filters；4- is single-ended to differential converter；5- dac channels.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, with reference to embodiment and accompanying drawing, to this
Invention is described in further detail, and exemplary embodiment of the invention and its explanation are only used for explaining the present invention, do not make
For limitation of the invention.
Embodiment 1：
As Figure 1-3, the present invention realizes circuit including a kind of multichannel DAC, including
FPGA：For the generation equipment of DAC data, there are at least two data/control output end, FPGA each data/control on FPGA
Output end processed produces by the single logic circuits of FPGA, and FPGA each data/control output end is all connected with a DAC number
According to/control signal, FPGA carries out parallel data processing；
DAC：Pin is enabled with loading, including 8 DACs, each DAC include 4 digital-to-analogue conversions
Passage, possesses 32 dac channels altogether, and each DAC is by signal output to RC low pass filter inputs；
RC low pass filters：Identical with DAC quantity, RC low pass filters rear end is also connected with single-ended to differential signal conversion
Device；
It is single-ended to differential converter：Integrated resistor is located inside difference integrated transporting discharging, identical with DAC quantity.
In existing 6U CPCI or CPCIe systems, majority realizes more ways by the way of FPGA and multichannel DAC
Mould is changed, and basic ideas are connected to DAC data input pin, DAC output using FPGA data output end
Amplifier is connected to, conversion of the single-ended signal to differential signal is realized by amplifier non-essential resistance, due to amplifier non-essential resistance resistance
Fine error be present, each passage is unable to reach the uniformity of output signal, intermodulation caused by resistance difference in actual applications
Distortion can cause larger workload when the later stage debugs and calibrates to commissioning staff, existing due to having the drawback that
DAC port number and few in circuit arrangement.
This programme employs the resistance inside difference integrated transporting discharging to avoid above mentioned problem, using single-ended to differential signal turn
Parallel operation, DAC output signal are defeated by single-ended one to differential converter after the filtering of RC low pass filters
Entrance enters, and after first passing through integrated resistor, then exports two paths of signals after passing to two operational amplifiers processing below, without
It is as DAC output signal realizes single-ended signal extremely by non-essential resistance again after first passing through operational amplifier in the prior art
The conversion of differential signal, avoid the occurrence of because amplifier non-essential resistance resistance has fine error, in actual applications each passage
The uniformity of output signal is unable to reach, crosstalk caused by resistance difference can give commissioning staff when the later stage debugs and calibrates
The defects of causing larger workload.
DAC, which has, in this programme loads enabled pin, and FPGA device realizes the parallelization processing of program, each
Data/control of DAC, produced by the single logic circuits of FPGA；The single logics of FPGA are united by host computer
One control and data interaction；The data of each DAC enter line function generation by single DDS in FPGA；Make each logical
The DAC data in road can be sent simultaneously, improve the processing speed of data.This programme realizes the synchronization of multichannel DAC outputs, and DAC is defeated
Going out signal avoids the later stage caused by crosstalk from demarcating and debug the defects of difficult, and data are total between FPGA and DAC
Line connection is simple, and the uniformity of multichannel DAC output signals is good.Each DAC possesses 4 dac channels, the present invention
Possess 8 identical digital analog converters, possess 32 dac channels altogether, so allow for while 32 road signals can be entered
Row conversion, conversion speed greatly improve.Each dac channel is using modularization, Hierarchical Design, each analog channel parameter
It is consistent, facilitates commissioning staff's later stage to debug and calibrate.
Embodiment 2：
The present embodiment is preferably as follows on the basis of embodiment 1：Each dac channel of DAC uses identical
Design, and the parameter for carrying out modularized design and each dac channel is consistent.Ensure the consistent of each multi-channel output signal,
Facilitate commissioning staff's later stage to debug and calibrate, greatly reduce the workload of debugging and calibration.
Each dac channel output of DAC is differential signal.It is further ensured that each passage output letter
Number it is consistent, facilitate commissioning staff's later stage to debug and calibrate, greatly reduce debugging and calibration workload.
Each dac channel of DAC possesses identical signal condition function.Further ensure each logical
Road output signal it is consistent, facilitate commissioning staff's later stage to debug and calibrate, greatly reduce debugging and calibration workload.
The data of each DAC enter line function generation by single DDS in FPGA.It ensure that every road signal transacting
The uniformity of data.
The single logic circuits of FPGA are uniformly controlled by host computer and data interaction.Further ensure every road signal
The uniformity of processing data.
RC low pass filters include resistance R, electric capacity C and operational amplifier B, and resistance R one end is low pass filter input
A, resistance R other end concatenation operation amplifiers B inverting input, under being also connected with operational amplifier B inverting input
Electric capacity C is drawn, operational amplifier B in-phase input end is connected with output, and operational amplifier B output end is the defeated of low pass filter
Go out to hold b.
It is described it is single-ended include operational amplifier B1 and operational amplifier B2 to differential converter, operational amplifier B1's
Inverting input connects pull down resistor R1, operational amplifier B1 in-phase input end connection resistance R3 one end, the resistance R3 other ends
To be single-ended to differential converter input a1, resistance R2 is also connected between operational amplifier B1 inverting input and output end,
Operational amplifier B1 output end is to be single-ended to differential converter output plus terminal b1, operational amplifier B2 inverting input connection
Resistance R4 one end, the resistance R4 other ends to be single-ended to differential converter input a1, operational amplifier B2 inverting input and
Resistance R6, operational amplifier B2 in-phase input end connection pull down resistor R5 are also connected between output end, operational amplifier B2's
Output end is to be single-ended to differential converter output negative terminal.The circuit first passes through unlike DAC output signal in the prior art
Conversion of the single-ended signal to differential signal is realized by non-essential resistance again after operational amplifier, is avoided the occurrence of due to amplifier external electrical
There is fine error in resistance resistance, each passage is unable to reach the uniformity of output signal in actual applications, and resistance difference causes
Crosstalk the later stage debug and calibrate when can cause larger workload to commissioning staff the defects of.
Above-described embodiment, the purpose of the present invention, technical scheme and beneficial effect are carried out further
Describe in detail, should be understood that the embodiment that the foregoing is only the present invention, be not intended to limit the present invention
Protection domain, within the spirit and principles of the invention, any modification, equivalent substitution and improvements done etc., all should include
Within protection scope of the present invention.
Claims (8)
1. a kind of multichannel DAC realizes circuit, it is characterised in that including
FPGA：For the generation equipment of DAC data, there are at least two data/control output end, FPGA each data/control on FPGA
Output end processed produces by the single logic circuits of FPGA, and FPGA each data/control output end is all connected with a DAC number
According to/control signal, FPGA carries out parallel data processing；
DAC：Pin is enabled with loading, including at least two DAC, each DAC include 4 digital-to-analogues
ALT-CH alternate channel, each DAC is by signal output to RC low pass filter inputs；
RC low pass filters：Identical with DAC quantity, RC low pass filters rear end is also connected with single-ended to differential signal conversion
Device；
It is single-ended to differential converter：Integrated resistor is located inside difference integrated transporting discharging, identical with DAC quantity.
2. a kind of multichannel DAC according to claim 1 realizes circuit, it is characterised in that each digital-to-analogue of DAC
ALT-CH alternate channel is designed using identical, and the parameter for carrying out modularized design and each dac channel is consistent.
3. a kind of multichannel DAC according to claim 1 or 2 realizes circuit, it is characterised in that DAC it is each
Dac channel output is differential signal.
4. a kind of multichannel DAC according to claim 1 realizes circuit, it is characterised in that each digital-to-analogue of DAC
ALT-CH alternate channel possesses identical signal condition function.
5. a kind of multichannel DAC according to claim 1 realizes circuit, it is characterised in that the data of each DAC
Enter line function generation by single DDS in FPGA.
6. a kind of multichannel DAC according to claim 1 realizes circuit, it is characterised in that the single logic circuits of FPGA
It is uniformly controlled by host computer and data interaction.
7. a kind of multichannel DAC according to claim 1 realizes circuit, it is characterised in that the RC low pass filters bag
Resistance R, electric capacity C and operational amplifier B are included, resistance R one end is low pass filter input a, and resistance R other end concatenation operations are put
Big device B inverting input, is also connected with pulling down electric capacity C, operational amplifier B's is same on operational amplifier B inverting input
Phase input is connected with output, and operational amplifier B output end is the output end b of low pass filter.
8. a kind of multichannel DAC according to claim 1 realizes circuit, it is characterised in that described single-ended to differential signal
Converter includes operational amplifier B1 and operational amplifier B2, operational amplifier B1 inverting input connection pull down resistor R1,
Operational amplifier B1 in-phase input end connection resistance R3 one end, the resistance R3 other ends are single-ended to differential converter input
Resistance R2 is also connected between a1, operational amplifier B1 inverting input and output end, operational amplifier B1 output end is single
End to differential converter output plus terminal b1, operational amplifier B2 inverting input connects resistance R4 one end, the resistance R4 other ends
To be single-ended to differential converter input a1, resistance R6 is also connected between operational amplifier B2 inverting input and output end,
Operational amplifier B2 in-phase input end connection pull down resistor R5, operational amplifier B2 output end are single-ended to differential converter
Export negative terminal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711285701.4A CN107769788A (en) | 2017-12-07 | 2017-12-07 | A kind of multichannel DAC realizes circuit |
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| CN201711285701.4A CN107769788A (en) | 2017-12-07 | 2017-12-07 | A kind of multichannel DAC realizes circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109656307A (en) * | 2018-12-06 | 2019-04-19 | 合肥本源量子计算科技有限责任公司 | A kind of multichannel generator based on board |
| CN111082764A (en) * | 2019-12-19 | 2020-04-28 | 武汉航空仪表有限责任公司 | Single-ended input-to-differential output circuit |
| CN112729579A (en) * | 2020-12-21 | 2021-04-30 | 中国兵器装备集团自动化研究所 | Multi-channel isolated thermocouple temperature measurement system |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203133271U (en) * | 2013-03-15 | 2013-08-14 | 武汉大学 | Multi-channel coherent frequency synthesizer of high-frequency ground wave radar |
| CN103364765A (en) * | 2013-07-24 | 2013-10-23 | 中国人民解放军空军预警学院 | Digital radio frequency memory based on analogue demodulation/modulation |
| US20140002289A1 (en) * | 2012-06-27 | 2014-01-02 | Analog Devices Technology | Multi-stage string dac |
| US20140161279A1 (en) * | 2012-12-12 | 2014-06-12 | Apple Inc. | Creation of sub-sample delays in digital audio |
| CN104615030A (en) * | 2014-11-28 | 2015-05-13 | 北京航天峰光电子技术有限责任公司 | Portable function signal generator |
| CN105094014A (en) * | 2015-07-30 | 2015-11-25 | 中国科学院电子学研究所 | High-speed parallel D/A clock synchronization apparatus |
| US20160182076A1 (en) * | 2014-12-23 | 2016-06-23 | Texas Instruments Incorporated | Background Calibration for Digital-to-Analog Converters |
| CN107154805A (en) * | 2017-04-01 | 2017-09-12 | 西安电子科技大学 | A kind of programmable single DAC multichannels benchmark output circuit |
-
2017
- 2017-12-07 CN CN201711285701.4A patent/CN107769788A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140002289A1 (en) * | 2012-06-27 | 2014-01-02 | Analog Devices Technology | Multi-stage string dac |
| US20140161279A1 (en) * | 2012-12-12 | 2014-06-12 | Apple Inc. | Creation of sub-sample delays in digital audio |
| CN203133271U (en) * | 2013-03-15 | 2013-08-14 | 武汉大学 | Multi-channel coherent frequency synthesizer of high-frequency ground wave radar |
| CN103364765A (en) * | 2013-07-24 | 2013-10-23 | 中国人民解放军空军预警学院 | Digital radio frequency memory based on analogue demodulation/modulation |
| CN104615030A (en) * | 2014-11-28 | 2015-05-13 | 北京航天峰光电子技术有限责任公司 | Portable function signal generator |
| US20160182076A1 (en) * | 2014-12-23 | 2016-06-23 | Texas Instruments Incorporated | Background Calibration for Digital-to-Analog Converters |
| CN105094014A (en) * | 2015-07-30 | 2015-11-25 | 中国科学院电子学研究所 | High-speed parallel D/A clock synchronization apparatus |
| CN107154805A (en) * | 2017-04-01 | 2017-09-12 | 西安电子科技大学 | A kind of programmable single DAC multichannels benchmark output circuit |
Non-Patent Citations (5)
| Title |
|---|
| CHAU TRAN: "Dual Difference Amplifier with", 《HTTPS://WWW.ANALOG.COM/EN/ANALOG-DIALOGUE/ARTICLES/DUAL-DIFF-AMP-WITH-ON-CHIP-RESISTORS.HTML》 * |
| SANDRO HERRERA等: "多功能低功耗精密单端转差分转换器", 《HTTPS://WWW.ANALOG.COM/CN/ANALOG-DIALOGUE/ARTICLES/VERSATILE-PRECISION-SINGLE-ENDED-TO-DIFFERENTIAL-CONVERTER.HTML》 * |
| 沈尚贤: "《电子技术导论 下》", 31 May 1986 * |
| 陈国等: "一种便携多通道单端转差分模拟视频测试盒的设计实现", 《计算机光盘软件与应用》 * |
| 韩喜春等: "基于FPGA的可重构多通道DDS信号发生器", 《电测与仪表》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109656307A (en) * | 2018-12-06 | 2019-04-19 | 合肥本源量子计算科技有限责任公司 | A kind of multichannel generator based on board |
| CN111082764A (en) * | 2019-12-19 | 2020-04-28 | 武汉航空仪表有限责任公司 | Single-ended input-to-differential output circuit |
| CN112729579A (en) * | 2020-12-21 | 2021-04-30 | 中国兵器装备集团自动化研究所 | Multi-channel isolated thermocouple temperature measurement system |
| CN112729579B (en) * | 2020-12-21 | 2023-09-26 | 中国兵器装备集团自动化研究所有限公司 | Multichannel isolated thermocouple temperature measurement system |
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Application publication date: 20180306 |