CN202770959U - TMU-RMS test system - Google Patents
TMU-RMS test system Download PDFInfo
- Publication number
- CN202770959U CN202770959U CN 201220368785 CN201220368785U CN202770959U CN 202770959 U CN202770959 U CN 202770959U CN 201220368785 CN201220368785 CN 201220368785 CN 201220368785 U CN201220368785 U CN 201220368785U CN 202770959 U CN202770959 U CN 202770959U
- Authority
- CN
- China
- Prior art keywords
- port
- relay
- tmu
- control unit
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The utility model provides a TMU-RMS test system, which is suitable for the field of an integrated circuit. The TMU-RMS test system comprises an input circuit unit, a comparator circuit, a root mean square direct current converter, an analog-to-digital converter and an FPGA module. The input circuit unit comprises a first low-voltage TMU measure channel control unit, a second low-voltage TMU measure channel control unit, a third low-voltage TMU measure channel control unit, a high-voltage TMU measure channel control unit and an RMS measure channel control unit. The comparator circuit comprises a first comparator, a second comparator, a third comparator and a fourth comparator. The FPGA module comprises a time digital converter, a control and coupling unit and a data address unit. The input terminal of the root mean square direct current converter is connected with the RMS measure channel control unit, the input terminal of the analog-to-digital converter is connected with the output terminal of root mean square direct current converter, and the output terminal of the analog-to-digital converter is connected with the IO interface of the FPGA module.
Description
Technical field
The utility model belongs to integrated circuit fields, relates in particular to a kind of TMU-RMS test macro.
Background technology
The measurement of the time alternating-current parameter of integrated circuit occupies considerable status in the production test of reality; For example the slew rate of measuring operational amplifier requires to measure rise time and the fall time of its voltage; When measuring comparer, require to measure the alternating-current parameters such as its time delay; Sometimes also need to measure the parameters such as its cycle, frequency and pulse width.The measurement of these alternating-current parameters all needs a kind of TMU (time measurement unit) test macro of special use to realize.RMS (Root Mean square) is substantially measuring the AC signal amplitude.Equal to produce the required DC quantity of equal heat, the heating energy of representation signal in same load from the effective value of an AC signal of practical standpoint definition; Real effective is also referred to as root-mean-square value, its computing method be first square, more on average, evolution then.The real effective value of voltage is defined as follows:
Calculating basic process on the circuit is first square of average (integration) last evolution, also has the process of absolute value rectification when wherein beginning.
The utility model content
The purpose of this utility model is to provide a kind of TMU-RMS test macro that can measure integrated circuit (IC) chip exchange time parameter and AC signal amplitude.
The utility model provides a kind of TMU-RMS test macro, comprising: input circuit unit, comparator circuit, root mean square direct current transducer, analog to digital converter and the FPGA module that is used for controlling described input circuit unit and comparator circuit; Described input circuit unit comprises that the first low pressure TMU measures channel control unit, the second low pressure TMU measures channel control unit, the 3rd low pressure TMU measurement channel control unit, high pressure TMU measurement channel control unit and RMS and measures channel control unit; Described comparator circuit comprises: the 4th comparer of measuring the first comparer that channel control unit is connected, measuring the second comparer that channel control unit is connected, the 3rd comparer that is connected with described the 3rd low pressure TMU measurement channel control unit, be connected with described high pressure TMU measurement channel control unit with described the second low pressure TMU with described the first low pressure TMU; Described FPGA module comprises that the time-to-digit converter, control and the matching unit that are connected with described the first comparer, the second comparer, the 3rd comparer and the 4th comparer be connected the data address unit that is connected with communication bus; The input end of described root mean square direct current transducer is measured channel control unit with described RMS and is connected, the input end of described analog to digital converter is connected with the output terminal of described root mean square direct current transducer, and the output terminal of described analog to digital converter is connected with the IO interface of described FPGA module.
Further, it is identical with the circuit structure that the 3rd low pressure TMU measures channel control unit that described the first low pressure TMU measures channel control unit, the second low pressure TMU measures channel control unit, each low pressure TMU measures channel control unit and comprises the first bleeder circuit, and described the first bleeder circuit comprises: the second relay, the 3rd relay, the 4th relay, the 5th electric capacity, the 9th electric capacity, the 11 resistance and the tenth resistance; The second relay comprises six ports, and the first port connects 5V voltage, the second port connection control signal, and the 3rd port and the equal ground connection of the 4th port, five-port is as the input end of the first bleeder circuit, and the 6th port is as the output terminal of the second relay; The 3rd relay comprises six ports, the first port connects 5V voltage, the second port connection control signal, the 3rd port and the equal ground connection of the 4th port, five-port is connected with the output terminal of the second relay as the input end of the 3rd relay, and the 6th port is as the output terminal of the 3rd relay; The 4th relay comprises six ports, and the first port connects 5V voltage, the second port connection control signal, and the 3rd port and the equal ground connection of the 4th port, five-port is as the input end of the 4th relay, and the 6th port is as the output terminal of the 4th relay; The tenth resistance and the 11 resistance are connected in series between the input end and ground of the 3rd relay, and the end that is connected in series of the tenth resistance and the 11 resistance is connected with the input end of the 4th relay; The 5th electric capacity and the tenth resistance are connected in parallel, and the 9th electric capacity and the 11 resistance are connected in parallel; The output terminal of the 3rd relay is connected rear output terminal as the first bleeder circuit with the output terminal of the 4th relay.
Further, described the first comparer, the second comparer, the 3rd comparer are identical with the structure of the 4th comparer, and each comparer comprises: AD96687 ultrahigh-speed comparator chip, MC100EPT25 high-speed level conversion chip and peripheral circuit thereof.
Further, described comparer also comprises: the digital to analog converter that is used for setting the comparative voltage threshold value; Described digital to analog converter is that model is the chip of DAC7724.
Further, described high pressure TMU measures channel control unit and comprises the second bleeder circuit, and described the second bleeder circuit comprises the 5th relay, the 24 electric capacity, the 27 resistance, the 23 electric capacity, the 28 electric capacity, the 5th diode that is connected in series and the 6th diode, driver element and a plurality of potential-divider networks unit; Described the 5th relay comprises five ports, and the first port is as the input end of described the second bleeder circuit, and the second port is as the output terminal of the 5th relay, and the 3rd port connects 5V voltage, and the 4th port connects K1, five-port ground connection; One end of the 27 resistance is connected to the output terminal of the 5th relay, and the other end of the 27 resistance is connected to the end that is connected in series of the 5th diode and the 6th diode, and the 24 electric capacity and the 27 resistance are connected in parallel; A plurality of potential-divider networks unit is connected in parallel respectively between the other end and ground of described the 27 resistance; Described driver element comprises eight ports, the first port is unsettled not to be connect, the 3rd port is connected to the end that is connected in series of the 5th diode and the 6th diode, the 4th port connects-15V voltage, the 7th port connects+15V voltage, and the second port, five-port and the 8th port link together, and the 6th port is as the output terminal of described the second bleeder circuit, the 23 electric capacity is connected between the 7th port and the ground, and the 28 electric capacity is connected between the 4th port and the ground.
Further, described potential-divider network unit comprises the 6th relay, the 28 resistance and the 29 electric capacity; Described the 6th relay comprises five ports, and the first port is connected to the other end of the 27 resistance by the 28 resistance, the second port ground connection, and the 3rd port connects 5V voltage, the 4th port connection control signal, five-port ground connection; The 29 electric capacity and the 28 resistance are connected in parallel.
Further, described RMS measures channel control unit and comprises the 3rd bleeder circuit, described the 3rd bleeder circuit comprises the first relay, described the first relay comprises six ports, the first port connects 5V voltage, and the second port connects control signal, the 3rd port and the equal ground connection of the 4th port, five-port connects the RMS test signal as the input end of described the 3rd bleeder circuit, and the 6th port is as the output terminal of described the 3rd bleeder circuit.
Further, described root mean square direct current transducer comprises conversion chip and the peripheral circuit thereof of AD637.
Further, described analog to digital converter comprises AD976 modulus conversion chip and peripheral circuit thereof.
The TMU-RMS test macro that the utility model provides can be measured integrated circuit (IC) chip exchange time parameter and AC signal amplitude; In the production test of reality, be extremely important.
Description of drawings
Fig. 1 is the modular structure schematic diagram of the TMU-RMS test macro that provides of the utility model;
Fig. 2 is the circuit block diagram of the TMU-RMS test macro that provides of the utility model;
Fig. 3 is the physical circuit figure that the low pressure TMU that provides of the utility model measures bleeder circuit in the channel circuit;
Fig. 4 is the physical circuit figure of the comparer that provides of the utility model;
Fig. 5 is the physical circuit figure of the comparator voltage Threshold circuit that provides of the utility model;
Fig. 6 is the physical circuit figure that the high pressure TMU that provides of the utility model measures passage;
Fig. 7 is the physical circuit figure of the RMS passage that provides of the utility model;
Fig. 8 is the physical circuit figure of the root mean square direct current transducer that provides of the utility model;
Fig. 9 is the physical circuit figure of the analog to digital converter that provides of the utility model.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.
Fig. 1 shows the modular structure of the TMU-RMS test macro that the utility model provides, and for convenience of explanation, only shows the part relevant with the utility model.
The TMU-RMS test macro comprises: input circuit unit 1, comparator circuit 2, root mean square direct current transducer 3, analog to digital converter 4 and the FPGA module 5 that is used for control inputs circuit unit 1 and comparator circuit 2; Wherein input circuit unit 1 comprises that the first low pressure TMU measures channel control unit 11, the second low pressure TMU measures channel control unit 12, the 3rd low pressure TMU measurement channel control unit 13, high pressure TMU measurement channel control unit 14 and RMS and measures channel control unit 15; Comparator circuit 2 comprises: the 4th comparer 24 of measuring the first comparer 21 that channel control unit 11 is connected, measuring the second comparer 22 that channel control unit 12 is connected, the 3rd comparer 23 that is connected with the 3rd low pressure TMU measurement channel control unit 13, be connected with high pressure TMU measurement channel control unit 14 with the second low pressure TMU with the first low pressure TMU; FPGA module 5 comprises the data address unit 53 that the time-to-digit converter 51, control and the matching unit that are connected with the first comparer 21, the second comparer 22, the 3rd comparer 23 and the 4th comparer 24 are connected and are connected with communication bus 6; The input end of root mean square direct current transducer 3 is measured channel control unit 15 with RMS and is connected, and the input end of analog to digital converter 4 is connected with the output terminal of root mean square direct current transducer 3, and the output terminal of analog to digital converter 4 is connected with the IO interface of FPGA module 5.
TMU-RMS test macro provided by the invention is the TMU-RMS test macro that designs for time measurement, and this system can realize measuring the rising edge, negative edge, cycle, pulse width of input waveform etc.; Major function is divided into A, B, C, D, R five parts; A, B, C are that low pressure TMU measures passage; D is that high pressure TMU measures passage; R is that RMS measures passage.
Fig. 2 shows the circuit block diagram of TMU-RMS test macro; The measured signal source enters from the input interface on the left side; The final measurement data communication device is crossed the right BUS to be sent.Whole system is divided up and down two parts of M and N, and their functions are identical, respectively by the FPGA(processor) independent control.Every part comprises two groups of TMU-RMS measuring units (X by name and Y).Each unit is comprised of TMU part (A, B, C, D) and RMS part (R).
In the utility model, low pressure TMU measures passage A, and B, C all can provide ± two input voltage ranges of 2.5V-± 10V, and these three hardware circuit design of measuring passage are identical.It is identical with the circuit structure that the 3rd low pressure TMU measures channel control unit 13 that wherein the first low pressure TMU measures channel control unit 11, the second low pressure TMU measures channel control unit 12, each low pressure TMU measures channel control unit and comprises the first bleeder circuit, as shown in Figure 3, the first bleeder circuit comprises: the second relay K 2, the 3rd relay K 3, the 4th relay K 4, the 5th capacitor C 5, the 9th capacitor C 9, the 11 resistance R 11 and the tenth resistance R 10; Wherein the second relay K 2 comprises 6 ports, the first port one connects 5V voltage, the second port 2 connection control signal K2, the 3rd port 3 and the 4th port 4 equal ground connection, five-port 5 is as the input end IN of the first bleeder circuit, and the 6th port 6 is as the output terminal of the second relay K 2; The 3rd relay K 3 comprises 6 ports, the first port one connects 5V voltage, the second port 2 connection control signal K3, the 3rd port 3 and the 4th port 4 equal ground connection, five-port 5 is connected with the output terminal of the second relay K 2 as the input end of the 3rd relay K 3, and the 6th port 6 is as the output terminal of the 3rd relay K 3; The 4th relay K 4 comprises 6 ports, the first port one connects 5V voltage, the second port 2 connection control signal K4, the 3rd port 3 and the 4th port 4 equal ground connection, five-port 5 is as the input end of the 4th relay K 4, and the 6th port 6 is as the output terminal of the 4th relay K 4; The tenth resistance R 10 and the 11 resistance R 11 are connected in series between the input end and ground of the 3rd relay K 3, and the end that is connected in series of the tenth resistance R 10 and the 11 resistance R 11 is connected with the input end of the 4th relay K 4; The 5th capacitor C 5 and the tenth resistance R 10 are connected in parallel, and the 9th capacitor C 9 and the 11 resistance R 11 are connected in parallel; The output terminal of the 3rd relay K 3 is connected rear output terminal OUT as the first bleeder circuit with the output terminal of the 4th relay K 4.
The principle of work of the first bleeder circuit is as follows: the second relay K 2 is when opening, input signal; The 3rd relay K 3 is opened and the 4th relay K 4 when closing, the voltage of input ± 2.5V.The 3rd relay K 3 is closed and the 4th relay K 4 when opening, and through the 1-4 dividing potential drop of the tenth resistance R 10 and the 11 resistance R 11, is input in the next stage comparator circuit and goes.
In the utility model, the first comparer 21, the second comparer 22, the 3rd comparer 23 are identical with the structure of the 4th comparer 24, and each comparer comprises: ultrahigh-speed comparator U7, level standard conversion chip U37, level standard conversion chip U38 and peripheral circuit thereof; Concrete circuit structure as shown in Figure 4.
Wherein, can to select model be AD96687 ultrahigh-speed comparator chip to comparer; It has two passages; Input voltage is ± 2.5V that limiting voltage is ± 5V to protect input.Only be 2.5ns through the time-delay of comparer, and two interchannel comparers only have the time-delay residual quantity of 50ps.What this comparer adopted is the ECL logic.So need to carry out level conversion, select MC100EPT25 high-speed level conversion chip, time-delay only is 1.1ns.Two negative input ends of comparer (INVERTING INPUT) connect respectively two voltage thresholds (VL and VH), two positive input terminals (NONINVERTING INPUT) connect measured signal (INPUT) simultaneously, measured signal voltage is above output logic signal behind the threshold voltage, through sending into the IO mouth of FPGA after the level conversion.Each TMU measures passage and uses a comparer.This comparer is binary channels.In each passage, it (is VL ≠ VH), can measure rising edge-negative edge time that comparer is set different compare thresholds.As to A channel, set VL=0.5V, VH=2.2V.Only set a threshold value (VL or VH), then can measuring period and pulsewidth.Two signals are inputted respectively in two passages, set identical compare threshold, then can measure the delay of two signals.As to A and B passage, the comparer of two passages is established VL=0V simultaneously.Therefore, this when requiring circuit design in these two passages the path delay of signal be identical.
Comparer also comprises for the digital to analog converter of setting the comparative voltage threshold value; As shown in Figure 5, can to adopt model be the comparative voltage Threshold that the chip of DAC7724 is realized comparer to digital to analog converter; Wherein DAC7724 is 12 DAC; Be output as ± 5V four tunnel outputs; Every two-way is given and is sent into a binary channels comparer; Per like this two TMU passages share a DAC.
In the utility model, high pressure TMU measures channel control unit 14 and comprises the second bleeder circuit, as shown in Figure 6, the second bleeder circuit comprises the 5th relay K 5, the 24 capacitor C 24, the 27 resistance R 27, the 5th diode D5 that is connected in series and the 6th diode D6, driver element BUF634 and a plurality of potential-divider networks unit; The 5th relay K 5 comprises 5 ports, and the first port one is as the input end IN of the second bleeder circuit, and the second port 2 is as the output terminal of the 5th relay K 5, and the 3rd port P1 connects 5V voltage, the 4th port connection control signal K1, five-port ground connection; One end of the 27 resistance R 27 is connected to the output terminal of the 5th relay K 5, the other end of the 27 resistance R 27 is connected to the end that is connected in series of the 5th diode D5 and the 6th diode D6, the 24 capacitor C 24 and the 27 resistance R 27 are connected in parallel, and a plurality of potential-divider networks unit is connected in parallel respectively between the other end and ground of the 27 resistance R 27; Driver element BUF634 comprises 8 ports, the first port one is unsettled not to be connect, the 3rd port 3 is connected to the end that is connected in series of the 5th diode D5 and the 6th diode D6, the 4th port 4 connects-15V voltage, the 7th port 7 connects+15V voltage, and the second port 2, five-port 5 and the 8th port 8 link together, and the 6th port 6 is as the output terminal OUT of the second bleeder circuit, the 23 capacitor C 23 is connected between the 7th port 7 and the ground, and the 28 capacitor C 28 is connected between the 4th port 4 and the ground.
Fig. 6 shows the physical circuit of three potential-divider network unit, and wherein the first potential-divider network unit comprises the 6th relay K 6, the 28 resistance R 28 and the 29 capacitor C 29; The 6th relay K 6 comprises 5 ports, and the first port one is connected to the other end of the 27 resistance R 27 by the 28 resistance R 28, the second port 2 ground connection, and the 3rd port P1 connects 5V voltage, the 4th port P2 connection control signal K2, five-port G ground connection; The 29 capacitor C 29 and the 28 resistance R 28 are connected in parallel.The second potential-divider network unit comprises relay K 7, resistance R 29 and capacitor C 30; Relay K 7 comprises 5 ports, and the first port one is connected to the other end of the 27 resistance R 27 by resistance R 29, the second port 2 ground connection, and the 3rd port P1 connects 5V voltage, the 4th port P2 connection control signal K3, five-port G ground connection; Capacitor C 30 is connected in parallel with resistance R 29.The 3rd potential-divider network unit comprises relay K 8, resistance R 30 and capacitor C 31; Relay K 8 comprises 5 ports, and the first port one is connected to the other end of the 27 resistance R 27 by resistance R 30, the second port 2 ground connection, and the 3rd port P1 connects 5V voltage, the 4th port P2 connection control signal K4, five-port G ground connection; Capacitor C 31 is connected in parallel with resistance R 30.
In the utility model, the principle of work of the second bleeder circuit is as follows: relay K 6, relay K 7, relay K 8 and resistance capacitance thereof form potential-divider network, difference closed K6, K7, K8 relay, thus realize that circuit divides compression functions, be divided into three gears of 5V-100V-300V.Wherein, passage D is exclusively used in and measures high-pressure low frequency signal cycle and frequency, is controlled by the high voltage relay array, is divided into three gears of 5V-100V-300V.The difference of high-pressure passage and low-pressure passage is that resistor voltage divider network is different.After will inputting the measured signal dividing potential drop, its driving force diminishes, and has therefore increased one-level high-speed driving BUF634 herein to improve the driving force of measured signal.To be sent in the comparer again, compare sampled data.
In the utility model, RMS measures channel control unit 15 and comprises the 3rd bleeder circuit, as shown in Figure 7, the 3rd bleeder circuit comprises that the first relay K 1, the first relay K 1 comprises 6 ports, and the first port one connects 5V voltage, the second port 2 meets K1, the 3rd port 3 and the 4th port 4 equal ground connection, five-port 5 connects the RMS test signal as the input end of the 3rd bleeder circuit, and the 6th port 6 is as the output terminal of the 3rd bleeder circuit.RMS (Root Mean square) is substantially measuring the AC signal amplitude.From the practical standpoint definition be: the real effective of an AC signal equals to produce the required DC quantity of equal heat, the heating energy of representation signal in same load.Effective value is also referred to as root-mean-square value, its computing method be first square, more on average, evolution then.The real effective value of voltage is defined as follows:
Calculating basic process on the circuit is first square of average (integration) last evolution, also has the process of absolute value rectification when wherein beginning.
In the utility model, the physical circuit of root mean square direct current transducer 3 comprises RMS-to-DC conversion chip U5 and peripheral circuit thereof as shown in Figure 8; Wherein can to adopt model be the conversion chip of AD637 to RMS-to-DC conversion chip U5; Physical circuit as shown in Figure 8; AD637 sends the d. c. voltage signal of measuring-signal conversion into the next stage circuit.Wherein, each TMU-RMS test macro is furnished with a RMS passage, and so-called RMS i.e. " root-mean-square value (Root Mean Square) ", the i.e. effective value of AC signal.Here select the AD637 chip to realize measurement to the RMS parameter.A D637 is a high precision RMS-to-DC conversion chip that is applicable to any complicated wave form.
In the utility model, analog to digital converter 4 physical circuits comprise modulus conversion chip U6 and peripheral circuit thereof as shown in Figure 9; It is the conversion chip of AD976 that modulus conversion chip U6 can adopt model.Wherein, AD976 is 16 ADC, and AD976 sends FPGA to after being converted into digital signal, thereby realizes the measurement to the RMS parameter.
The TMU-RMS test macro that the utility model provides has been realized the measurement function to integrated circuit (IC) chip exchange time parameter and AC signal amplitude; In the production test of reality, be extremely important.
The above only is preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of within spirit of the present utility model and principle, doing, be equal to and replace and improvement etc., all should be included within the protection domain of the present utility model.
Claims (9)
1. a TMU-RMS test macro is characterized in that, comprising: input circuit unit, comparator circuit, root mean square direct current transducer, analog to digital converter and the FPGA module that is used for controlling described input circuit unit and comparator circuit;
Described input circuit unit comprises that the first low pressure TMU measures channel control unit, the second low pressure TMU measures channel control unit, the 3rd low pressure TMU measurement channel control unit, high pressure TMU measurement channel control unit and RMS and measures channel control unit;
Described comparator circuit comprises: the 4th comparer of measuring the first comparer that channel control unit is connected, measuring the second comparer that channel control unit is connected, the 3rd comparer that is connected with described the 3rd low pressure TMU measurement channel control unit, be connected with described high pressure TMU measurement channel control unit with described the second low pressure TMU with described the first low pressure TMU;
Described FPGA module comprises that the time-to-digit converter, control and the matching unit that are connected with described the first comparer, the second comparer, the 3rd comparer and the 4th comparer be connected the data address unit that is connected with communication bus;
The input end of described root mean square direct current transducer is measured channel control unit with described RMS and is connected, the input end of described analog to digital converter is connected with the output terminal of described root mean square direct current transducer, and the output terminal of described analog to digital converter is connected with the IO interface of described FPGA module.
2. test macro as claimed in claim 1, it is characterized in that, it is identical with the circuit structure that the 3rd low pressure TMU measures channel control unit that described the first low pressure TMU measures channel control unit, the second low pressure TMU measures channel control unit, each low pressure TMU measures channel control unit and comprises the first bleeder circuit, and described the first bleeder circuit comprises: the second relay, the 3rd relay, the 4th relay, the 5th electric capacity, the 9th electric capacity, the 11 resistance and the tenth resistance;
The second relay comprises six ports, and the first port connects 5V voltage, the second port connection control signal, and the 3rd port and the equal ground connection of the 4th port, five-port is as the input end of the first bleeder circuit, and the 6th port is as the output terminal of the second relay;
The 3rd relay comprises six ports, the first port connects 5V voltage, the second port connection control signal, the 3rd port and the equal ground connection of the 4th port, five-port is connected with the output terminal of the second relay as the input end of the 3rd relay, and the 6th port is as the output terminal of the 3rd relay;
The 4th relay comprises six ports, and the first port connects 5V voltage, the second port connection control signal, and the 3rd port and the equal ground connection of the 4th port, five-port is as the input end of the 4th relay, and the 6th port is as the output terminal of the 4th relay;
The tenth resistance and the 11 resistance are connected in series between the input end and ground of the 3rd relay, and the end that is connected in series of the tenth resistance and the 11 resistance is connected with the input end of the 4th relay; The 5th electric capacity and the tenth resistance are connected in parallel, and the 9th electric capacity and the 11 resistance are connected in parallel; The output terminal of the 3rd relay is connected rear output terminal as the first bleeder circuit with the output terminal of the 4th relay.
3. test macro as claimed in claim 1, it is characterized in that, described the first comparer, the second comparer, the 3rd comparer are identical with the structure of the 4th comparer, and each comparer comprises: AD96687 ultrahigh-speed comparator chip, MC100EPT25 high-speed level conversion chip and peripheral circuit thereof.
4. test macro as claimed in claim 1 is characterized in that, described comparer also comprises: the digital to analog converter that is used for setting the comparative voltage threshold value; Described digital to analog converter is that model is the chip of DAC7724.
5. test macro as claimed in claim 1, it is characterized in that, described high pressure TMU measures channel control unit and comprises the second bleeder circuit, and described the second bleeder circuit comprises the 5th relay, the 24 electric capacity, the 27 resistance, the 23 electric capacity, the 28 electric capacity, the 5th diode that is connected in series and the 6th diode, driver element and a plurality of potential-divider networks unit;
Described the 5th relay comprises five ports, and the first port is as the input end of described the second bleeder circuit, and the second port is as the output terminal of the 5th relay, and the 3rd port connects 5V voltage, the 4th port connection control signal, five-port ground connection;
One end of the 27 resistance is connected to the output terminal of the 5th relay, and the other end of the 27 resistance is connected to the end that is connected in series of the 5th diode and the 6th diode, and the 24 electric capacity and the 27 resistance are connected in parallel;
A plurality of potential-divider networks unit is connected in parallel respectively between the other end and ground of described the 27 resistance;
Described driver element comprises eight ports, the first port is unsettled not to be connect, the 3rd port is connected to the end that is connected in series of the 5th diode and the 6th diode, the 4th port connects-15V voltage, the 7th port connects+15V voltage, and the second port, five-port and the 8th port link together, and the 6th port is as the output terminal of described the second bleeder circuit, the 23 electric capacity is connected between the 7th port and the ground, and the 28 electric capacity is connected between the 4th port and the ground.
6. test macro as claimed in claim 5 is characterized in that, described potential-divider network unit comprises the 6th relay, the 28 resistance and the 29 electric capacity;
Described the 6th relay comprises five ports, and the first port is connected to the other end of the 27 resistance by the 28 resistance, the second port ground connection, and the 3rd port connects 5V voltage, the 4th port connection control signal, five-port ground connection; The 29 electric capacity and the 28 resistance are connected in parallel.
7. test macro as claimed in claim 1, it is characterized in that, described RMS measures channel control unit and comprises the 3rd bleeder circuit, described the 3rd bleeder circuit comprises the first relay, and described the first relay comprises six ports, and the first port connects 5V voltage, the second port connects control signal, the 3rd port and the equal ground connection of the 4th port, five-port connects the RMS test signal as the input end of described the 3rd bleeder circuit, and the 6th port is as the output terminal of described the 3rd bleeder circuit.
8. test macro as claimed in claim 1 is characterized in that, described root mean square direct current transducer comprises conversion chip and the peripheral circuit thereof of AD637.
9. test macro as claimed in claim 1 is characterized in that, described analog to digital converter comprises AD976 modulus conversion chip and peripheral circuit thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220368785 CN202770959U (en) | 2012-07-27 | 2012-07-27 | TMU-RMS test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220368785 CN202770959U (en) | 2012-07-27 | 2012-07-27 | TMU-RMS test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202770959U true CN202770959U (en) | 2013-03-06 |
Family
ID=47777523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220368785 Expired - Fee Related CN202770959U (en) | 2012-07-27 | 2012-07-27 | TMU-RMS test system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202770959U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115183897A (en) * | 2022-09-09 | 2022-10-14 | 之江实验室 | Temperature measuring system and method based on high-frequency alternating current signals |
-
2012
- 2012-07-27 CN CN 201220368785 patent/CN202770959U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115183897A (en) * | 2022-09-09 | 2022-10-14 | 之江实验室 | Temperature measuring system and method based on high-frequency alternating current signals |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN204013486U (en) | The circuit of device address is set with toggle switch | |
| CN106535412B (en) | The digital simulation light adjusting circuit that a kind of port shares | |
| CN103499733B (en) | A kind of high-accuracy voltage testing circuit and method | |
| CN104034928A (en) | Multi-path signal source based on PCI and FPGA | |
| CN104660246A (en) | Receiver, differential receiver and analog front end circuit for high-speed serial interface | |
| CN101615901B (en) | Photoelectric isolation pulse shunting method and device thereof | |
| CN205049678U (en) | Short circuit testing arrangement is opened to camera module | |
| CN205506896U (en) | Oscilloscope circuit | |
| CN202770959U (en) | TMU-RMS test system | |
| CN102466750A (en) | Circuit and method for measuring alternating current of digital universal meter | |
| CN203881815U (en) | Simple high-precision DC electronic load | |
| CN206805286U (en) | A kind of device of DCS system simulations amount signal acquisition browsing real-time data | |
| CN204283625U (en) | Gas turbine rotary speed conditioning module | |
| CN106707847B (en) | A kind of Mixed design semaphore intelligent detection device | |
| CN108020727A (en) | A kind of capacitance-voltage conversion circuit | |
| CN105846809B (en) | A kind of buffer circuit and buffer chip | |
| CN103091597A (en) | Leakage switch calibrator | |
| CN205880047U (en) | System for realize multiloop voltage and many loop current synchronous sampling | |
| CN103532551B (en) | high speed tri-state ADC | |
| CN107329879A (en) | Voltage monitoring circuit and voltage monitoring method | |
| CN206489254U (en) | A kind of test circuit of isolated amplifier gain accuracy | |
| CN204498108U (en) | Port status Acquisition Circuit | |
| CN206601601U (en) | A kind of multichannel analog amount independence output device | |
| CN203708216U (en) | Sine wave generation circuit and audio shield | |
| CN205279897U (en) | A alternating current -direct current unit test device of gathering and editing for rocket measurement system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130306 Termination date: 20130727 |