CN112564708B - Analog-to-digital conversion circuit - Google Patents
Analog-to-digital conversion circuit Download PDFInfo
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- CN112564708B CN112564708B CN202011540096.2A CN202011540096A CN112564708B CN 112564708 B CN112564708 B CN 112564708B CN 202011540096 A CN202011540096 A CN 202011540096A CN 112564708 B CN112564708 B CN 112564708B
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- JPKJQBJPBRLVTM-OSLIGDBKSA-N (2s)-2-amino-n-[(2s,3r)-3-hydroxy-1-[[(2s)-1-[[(2s)-1-[[(2s)-1-[[(2r)-1-(1h-indol-3-yl)-3-oxopropan-2-yl]amino]-1-oxo-3-phenylpropan-2-yl]amino]-1-oxo-3-phenylpropan-2-yl]amino]-1-oxo-3-phenylpropan-2-yl]amino]-1-oxobutan-2-yl]-6-iminohexanamide Chemical compound C([C@H](NC(=O)[C@@H](NC(=O)[C@@H](N)CCCC=N)[C@H](O)C)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)N[C@H](CC=1C2=CC=CC=C2NC=1)C=O)C1=CC=CC=C1 JPKJQBJPBRLVTM-OSLIGDBKSA-N 0.000 description 7
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
- H03M1/186—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedforward mode, i.e. by determining the range to be selected directly from the input signal
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Abstract
The invention discloses an analog-to-digital conversion circuit which comprises a feedforward Sigma-Delta analog-to-digital conversion module, a buffer module, a first chopping unit and a second chopping unit; the first chopping unit is used for carrying out chopping processing on the first offset voltage generated by the buffer module and the second offset voltage generated by the sampling capacitor assembly and outputting the first offset voltage and the second offset voltage to the auxiliary integrator; the second chopper unit is used for carrying out chopper processing on the third offset voltage generated by the integrating capacitor component and outputting the third offset voltage to the auxiliary integrator. According to the invention, the chopper unit and the corresponding control logic are arranged in the analog-to-digital conversion circuit, the offset voltage caused by each part of the circuit including the high-order feedforward Sigma-Delta analog-to-digital conversion module is subjected to chopper treatment, and the offset voltage in the analog-to-digital conversion circuit is output to a relatively high-frequency position of the circuit so as to eliminate the offset voltage through subsequent treatment, so that the performance of the analog-to-digital conversion circuit is optimized.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to an analog-to-digital conversion circuit for carrying out chopper processing on a high-order feedforward Sigma-Delta module.
Background
With the development of the integrated circuit industry, an Analog-to-Digital Conversion (Analog-to-digital converter) ADC is used as a bridge for converting Analog signals and digital signals, and the performance of the ADC directly determines the quality of subsequent digital processing, so that the ADC has a wide application field and extremely high importance. Sigma-Delta analog-to-digital converters are the most widely used converters in the speech band and high resolution precision measurement fields, which can utilize oversampling and noise shaping techniques to achieve higher accuracy with lower analog circuit complexity. The current Sigma-Delta analog-to-digital conversion circuit mainly comprises a feedback structure and a feedforward structure. Although the feedback structure can obtain a better signal transfer function, a larger voltage amplitude range of the integrator is also needed, which means that the power consumption can be increased when the transconductance operational amplifier in each level of integrator realizes high voltage slew rate and large swing; conversely, the feedforward structure greatly reduces the voltage amplitude range of the integrator, thereby reducing the requirement of transconductance operational amplifier in each stage of integrator. Therefore, the feedforward structure is more beneficial to realizing low power consumption, and the Sigma-Delta analog-to-digital converter with high-order feedforward is also adopted in the field of low power consumption. Referring to fig. 1, a typical high-order feed-forward Sigma-Delta analog-to-digital conversion circuit includes an input stage, a buffer stage, a feed-forward Sigma-Delta analog-to-digital conversion stage, and a comparator output stage. Wherein the input stage comprises an LNA (Low Noise Amplifier, low-noise amplifier); the feedforward Sigma-Delta analog-to-digital conversion stage consists of an n-stage integrator.
The offset voltage refers to that when the voltages at the two input terminals of the operational amplifier are both 0V, the output terminal voltage should theoretically be equal to 0V, and if the voltage at the output terminal exists, the voltage is called offset voltage.
In the analog-to-digital conversion circuit, offset voltage is caused by process mismatch due to a low noise amplifier, a buffer integrator, an integrator capacitor and the like, and finally the offset voltage of the whole system is accumulated step by step to influence the overall performance of the circuit.
Disclosure of Invention
The invention aims to overcome the performance defect caused by offset voltage of a high-order feedforward Sigma-Delta analog-to-digital conversion circuit in the prior art, and provides an analog-to-digital conversion circuit.
The invention solves the technical problems by the following technical scheme:
the invention provides an analog-to-digital conversion circuit which comprises a feedforward Sigma-Delta analog-to-digital conversion module, a buffer module, a first chopping unit and a second chopping unit; the feedforward Sigma-Delta analog-to-digital conversion module comprises a main integrator and a secondary integrator; the main integrator comprises a sampling capacitance component and an integrating capacitance component;
The first chopping unit is respectively and electrically connected with the buffer module and the auxiliary integrator; the second chopper unit is electrically connected with the integrating capacitor assembly; the main integrator is electrically connected with the auxiliary integrator;
The first chopping unit is used for carrying out chopping modulation and chopping demodulation on the first offset voltage generated by the buffer module and the second offset voltage generated by the sampling capacitor assembly, and outputting the first offset voltage and the second offset voltage to the secondary integrator; the second chopper unit is used for carrying out chopper modulation and chopper demodulation on the third offset voltage generated by the integrating capacitor assembly and outputting the third offset voltage to the auxiliary integrator.
Preferably, the analog-to-digital conversion circuit further comprises an input module; the first chopping unit comprises a first chopping module, a second chopping module, a third chopping module and a sixth chopping module;
the input end of the first chopper module is electrically connected with the output end of the input module; the output end of the first chopper module is electrically connected with the input end of the buffer module;
The input end of the second chopper module is electrically connected with the output end of the buffer module; the output end of the second chopper module is electrically connected with the output end of the feedforward Sigma-Delta analog-to-digital conversion module;
the input end of the third chopper module is a reference voltage, and the output end of the third chopper module is electrically connected with the output end of the sampling capacitor assembly;
the input end of the sixth chopper module is electrically connected with the output end of the main integrator, and the output end of the sixth chopper module is electrically connected with the input end of the auxiliary integrator;
The first chopper module, the second chopper module and the third chopper module are used in cooperation, chopper modulation processing is carried out on the first offset voltage and the second offset voltage, and the first offset voltage and the second offset voltage after chopper modulation processing are output to the sixth chopper module;
The sixth chopper module is used for performing chopper demodulation processing on the first offset voltage and the second offset voltage, and outputting the first offset voltage and the second offset voltage after the chopper demodulation processing to the output end of the main integrator.
Preferably, the method is characterized in that,
The first chopping module further comprises a first chopping switch, a second chopping switch, a third chopping switch and a fourth chopping switch;
the input end of the first chopper switch is electrically connected with the positive phase end of the output end of the input module, and the output end of the first chopper switch is electrically connected with the negative phase end of the input end of the buffer module;
The input end of the second chopper switch is electrically connected with the positive phase end of the output end of the input module, and the output end of the second chopper switch is electrically connected with the positive phase end of the input end of the buffer module;
the input end of the third chopper switch is electrically connected with the negative phase end of the output end of the input module, and the output end of the third chopper switch is electrically connected with the negative phase end of the input end of the buffer module;
the input end of the fourth chopper switch is electrically connected with the negative phase end of the output end of the input module, and the output end of the fourth chopper switch is electrically connected with the positive phase end of the input end of the buffer module.
Preferably, the method is characterized in that,
The second chopping module further comprises a fifth chopping switch, a sixth chopping switch, a seventh chopping switch and an eighth chopping switch;
The input end of the fifth chopper switch is electrically connected with the positive phase end of the output end of the buffer module, and the output end of the fifth chopper switch is electrically connected with the negative phase end of the output end of the feedforward Sigma-Delta analog-to-digital conversion module;
the input end of the sixth chopper switch is electrically connected with the positive phase end of the output end of the buffer module, and the output end of the sixth chopper switch is electrically connected with the positive phase end of the output end of the feedforward Sigma-Delta analog-to-digital conversion module;
The input end of the seventh chopper switch is electrically connected with the negative phase end of the output end of the buffer module, and the output end of the seventh chopper switch is electrically connected with the negative phase end of the output end of the feedforward Sigma-Delta analog-to-digital conversion module;
The input end of the eighth chopper switch is electrically connected with the negative phase end of the output end of the buffer module, and the output end of the eighth chopper switch is electrically connected with the positive phase end of the output end of the feedforward Sigma-Delta analog-digital conversion module.
Preferably, the third chopping module comprises a ninth chopping switch, a tenth chopping switch, an eleventh chopping switch and a twelfth chopping switch;
The input end of the ninth chopper switch is electrically connected with a reference voltage, and the output end of the ninth chopper switch is electrically connected with the positive phase end of the output end of the sampling capacitor assembly;
The input end of the tenth chopper switch is electrically connected with a reference voltage, and the output end of the tenth chopper switch is electrically connected with the positive phase end of the output end of the sampling capacitor assembly;
The input end of the eleventh chopping switch is electrically connected with a reference voltage, and the output end of the eleventh chopping switch is electrically connected with the negative phase end of the output end of the sampling capacitor assembly;
The input end of the twelfth chopping switch is electrically connected with the reference voltage, and the output end of the twelfth chopping switch is electrically connected with the negative phase end of the output end of the sampling capacitor assembly.
Preferably, the sixth chopper module comprises a twenty-first chopper switch, a twenty-second chopper switch, a twenty-third chopper switch and a twenty-fourth chopper switch;
The input end of the twenty-first chopper switch is electrically connected with the positive phase end of the output end of the main integrator, and the output end of the twenty-first chopper switch is electrically connected with the negative phase end of the input end of the auxiliary integrator;
The input end of the twenty-second chopper switch is electrically connected with the positive phase end of the output end of the main integrator, and the output end of the twenty-second chopper switch is electrically connected with the positive phase end of the input end of the auxiliary integrator;
the input end of the twenty-third chopper switch is electrically connected with the negative phase end of the output end of the main integrator, and the output end of the twenty-third chopper switch is electrically connected with the negative phase end of the input end of the auxiliary integrator;
the input end of the twenty-fourth chopper switch is electrically connected with the negative phase end of the output end of the main integrator, and the output end is electrically connected with the positive phase end of the input end of the auxiliary integrator.
Preferably, the second chopping unit comprises a fourth chopping module and a fifth chopping module;
the input end of the fourth chopper module is electrically connected with the output end of the capacitor component, and the output end of the fourth chopper module is electrically connected with the input end of the integrating capacitor component;
the input end of the fifth chopper module is electrically connected with the output end of the integrating capacitor unit, and the output end of the fifth chopper module is electrically connected with the auxiliary integrator;
The fourth chopper module is used for carrying out chopper modulation on the third offset voltage and outputting the third offset voltage subjected to chopper modulation to the fifth chopper module; the fifth chopper module is used for carrying out chopper demodulation processing on the third offset voltage and outputting the third offset voltage subjected to chopper demodulation processing to the auxiliary integrator.
Preferably, the fourth chopper module comprises a thirteenth chopper switch, a fourteenth chopper switch, a fifteenth chopper switch and a sixteenth chopper switch;
the input end of the thirteenth chopper switch is electrically connected with the positive phase end of the output end of the sampling capacitor assembly, and the output end of the thirteenth chopper switch is electrically connected with the negative phase end of the input end of the integrating capacitor assembly;
the input end of the fourteenth chopper switch is electrically connected with the positive phase end of the output end of the sampling capacitor assembly, and the output end of the fourteenth chopper switch is electrically connected with the positive phase end of the input end of the integrating capacitor assembly;
The input end of the fifteenth chopper switch is electrically connected with the negative phase end of the output end of the sampling capacitor assembly, and the output end of the fifteenth chopper switch is electrically connected with the negative phase end of the input end of the integrating capacitor assembly;
The input end of the sixteenth chopper switch is electrically connected with the negative phase end of the output end of the sampling capacitor assembly, and the output end of the sixteenth chopper switch is electrically connected with the positive phase end of the input end of the integrating capacitor assembly.
Preferably, the fifth chopping module comprises a seventeenth chopping switch, an eighteenth chopping switch, a nineteenth chopping switch and a twentieth chopping switch;
The input end of the seventeenth chopper switch is electrically connected with the positive phase end of the output end of the integrating capacitor component, and the output end of the seventeenth chopper switch is electrically connected with the negative phase end of the output end of the main integrator;
The input end of the eighteenth chopper switch is electrically connected with the positive phase end of the output end of the integrating capacitor component, and the output end of the eighteenth chopper switch is electrically connected with the positive phase end of the output end of the main integrator;
The input end of the nineteenth chopping switch is electrically connected with the negative phase end of the output end of the integrating capacitor component, and the output end of the nineteenth chopping switch is electrically connected with the negative phase end of the output end of the main integrator;
the input end of the twentieth chopper switch is electrically connected with the negative phase end of the output end of the integrating capacitor component, and the output end is electrically connected with the positive phase end of the output end of the main integrator.
Preferably, the analog-to-digital conversion circuit further comprises a clock control signal module, wherein the clock control signal module is used for generating a first clock signal and a second clock signal which are inverted and are not overlapped; the first clock signal is used for controlling the working phase of the sampling capacitor assembly, and the second clock signal is used for controlling the working phase of the integrating capacitor assembly;
And/or the number of the groups of groups,
The analog-to-digital conversion circuit further comprises a voltage interface module, wherein the voltage interface module is respectively and electrically connected with the first chopping unit and the feedforward Sigma-Delta analog-to-digital conversion module, and is used for inputting a common-mode voltage to the first chopping unit and the feedforward Sigma-Delta analog-to-digital conversion module;
And/or the number of the groups of groups,
The analog-to-digital conversion circuit also comprises an output module, wherein the output module is electrically connected with the feedforward Sigma-Delta analog-to-digital conversion module and is used for outputting the modulated and demodulated signal to a low-pass filter.
The invention has the positive progress effects that: according to the invention, the chopper unit and the corresponding control logic are arranged in the analog-to-digital conversion circuit, the offset voltage caused by each part of the circuit including the high-order feedforward Sigma-Delta analog-to-digital conversion module is subjected to chopper treatment, and the offset voltage in the analog-to-digital conversion circuit is output to a relatively high-frequency position of the circuit so as to eliminate the offset voltage through subsequent treatment, so that the performance of the analog-to-digital conversion circuit is optimized.
Drawings
Fig. 1 is a circuit diagram of an analog-to-digital conversion circuit according to a preferred embodiment of the invention.
Fig. 2 is a schematic block diagram of an analog-to-digital conversion circuit according to a preferred embodiment of the invention.
Reference numerals illustrate:
1. A first chopper unit;
2. a second chopper unit;
3. A sampling capacitor assembly;
4. An integrating capacitor assembly;
5. Buffer module
6. An input module;
7. An output module;
9. Clock control signal module
10. A feedforward Sigma-Delta analog-to-digital conversion module;
11. a first chopper module;
12. A second chopper module;
13. a third chopper module;
14. a fourth chopper module;
15. a fifth chopper module;
16. a sixth chopper module;
Detailed Description
The invention is further illustrated by means of the following examples, which are not intended to limit the scope of the invention.
As shown in fig. 1-2, the analog-to-digital conversion circuit of the present embodiment includes a first chopper unit 1, a second chopper unit 2, a buffer module 5, and a feedforward Sigma-Delta analog-to-digital conversion module 10; the feedforward Sigma-Delta analog-to-digital conversion module 10 comprises a main integrator and a secondary integrator; the main integrator comprises a sampling capacitor assembly 3, an integrating capacitor assembly 4 and an operational amplifier OTA, and the sub-integrator can be provided with 1 to a plurality (INTEG 2 stands for sub-integrator) as shown in fig. 1.
As shown in fig. 1, since the offset voltage in the whole analog-to-digital conversion circuit is mainly brought by the buffer module 5, the first-stage integrator and the sampling capacitor C1 and the integrating capacitor C2 of the first-stage integrator, 2 chopper units are arranged in the circuit for the offset voltage of the three modules, and a total of 6 groups of chopper modules (CHOP 1-CHOP 6) are arranged, and the offset voltage of the high-order feedforward Sigma-Delta analog-to-digital conversion circuit is processed through a certain logic control.
The first chopping unit 1 is electrically connected with the buffer module 5 and the secondary integrator respectively; the second chopper unit 2 is electrically connected with the integrating capacitor component; the primary integrator is electrically connected to the secondary integrator.
The first chopping unit 1 is used for carrying out chopping modulation and chopping demodulation on a first offset voltage generated by the buffer module 5 and a second offset voltage generated by the sampling capacitor assembly, and outputting the first offset voltage and the second offset voltage to the secondary integrator; the second chopper unit 2 is used for performing chopper modulation and chopper demodulation on the third offset voltage generated by the integrating capacitor component, and outputting the third offset voltage to the auxiliary integrator.
The analog-to-digital conversion circuit comprises an input module 6; the first chopping unit 1 comprises a first chopping module 11, a second chopping module 12, a third chopping module 13 and a sixth chopping module 16;
The input end of the first chopper module 11 is electrically connected with the output end of the input module; the output end of the first chopper module 11 is electrically connected with the input end of the buffer module 5;
The input end of the second chopper module 12 is electrically connected with the output end of the buffer module 5; the output end of the second chopper module 12 is electrically connected with the output end of the feedforward Sigma-Delta analog-digital conversion module 10;
The input end of the third chopper module 13 is a reference voltage, and the output end of the third chopper module 13 is electrically connected with the output end of the sampling capacitor assembly 3;
The input end of the sixth chopper module 16 is electrically connected with the output end of the main integrator, and the output end of the sixth chopper module 16 is electrically connected with the input end of the auxiliary integrator;
The first chopper module 11, the second chopper module 12 and the third chopper module 13 are used in cooperation, perform chopper modulation on the first offset voltage and the second offset voltage, and output the first offset voltage and the second offset voltage after chopper modulation to the sixth chopper module 16; the sixth chopper module 16 is configured to perform chopper demodulation processing on the first offset voltage and the second offset voltage, and output the first offset voltage and the second offset voltage after the chopper demodulation processing to an output terminal of the main integrator.
As shown in fig. 1, the first chopper module 11 sequentially includes, from top to bottom, a first chopper switch, a second chopper switch, a third chopper switch, and a fourth chopper switch, wherein an input end of the first chopper switch is electrically connected with a positive phase end of an output end of the input module 6, and an output end of the first chopper switch is electrically connected with a negative phase end of an input end of the buffer module 5; the input end of the second chopper switch is electrically connected with the positive phase end of the output end of the input module, and the output end of the second chopper switch is electrically connected with the positive phase end of the input end of the buffer module 5; the input end of the third chopper switch is electrically connected with the negative phase end of the output end of the input module, and the output end of the third chopper switch is electrically connected with the negative phase end of the input end of the buffer module 5; the input end of the fourth chopper switch is electrically connected with the negative phase end of the output end of the input module 6, and the output end is electrically connected with the positive phase end of the input end of the buffer module 5.
The second chopper module 12 includes, in order from top to bottom, a fifth chopper switch, a sixth chopper switch, a seventh chopper switch, and an eighth chopper switch. The input end of the fifth chopper switch is electrically connected with the positive phase end of the output end of the buffer module 5, and the output end is electrically connected with the negative phase end of the output end of the feedforward Sigma-Delta analog-to-digital conversion module 10 through a capacitor C3; the input end of the sixth chopper switch is electrically connected with the positive phase end of the output end of the buffer module 5, and the output end is electrically connected with the positive phase end of the output end of the feedforward Sigma-Delta analog-digital conversion module 10 through a capacitor C3; the input end of the seventh chopper switch is electrically connected with the negative phase end of the output end of the buffer module 5, and the output end is electrically connected with the negative phase end of the output end of the feedforward Sigma-Delta analog-to-digital conversion module 10 through a capacitor C3; the input end of the eighth chopper switch is electrically connected with the negative phase end of the output end of the buffer module 5, and the output end is electrically connected with the positive phase end of the output end of the feedforward Sigma-Delta analog-digital conversion module 10 through a capacitor C3.
The third chopping module 13 comprises a ninth chopping switch, a tenth chopping switch, an eleventh chopping switch and a twelfth chopping switch from top to bottom in sequence; the input end of the ninth chopper switch is electrically connected with the reference voltage VREFN, and the output end of the ninth chopper switch is electrically connected with the positive phase end of the output end of the sampling capacitor assembly 3; the input end of the tenth chopper switch is electrically connected with the reference voltage VREFN, and the output end is electrically connected with the positive phase end of the output end of the sampling capacitor assembly 3; the input end of the eleventh chopper switch is electrically connected with the reference voltage VREFN, and the output end of the eleventh chopper switch is electrically connected with the negative phase end of the output end of the sampling capacitor assembly 3; the twelfth chopper switch has an input terminal electrically connected to the reference voltage VREFN and an output terminal electrically connected to the negative phase terminal of the output terminal of the sampling capacitance assembly 3.
The sixth chopper module 16 includes, in order from top to bottom, a twenty-first chopper switch, a twenty-second chopper switch, a twenty-third chopper switch, and a twenty-fourth chopper switch; the input end of the twenty-first chopper switch is electrically connected with the positive phase end of the output end of the main integrator, and the output end is electrically connected with the negative phase end of the input end of the auxiliary integrator; the input end of the twenty-second chopper switch is electrically connected with the positive phase end of the output end of the main integrator, and the output end is electrically connected with the positive phase end of the input end of the auxiliary integrator; the input end of the twenty-third chopper switch is electrically connected with the negative phase end of the output end of the main integrator, and the output end of the twenty-third chopper switch is electrically connected with the negative phase end of the input end of the auxiliary integrator; the input end of the twenty-fourth chopper switch is electrically connected with the negative phase end of the output end of the main integrator, and the output end is electrically connected with the positive phase end of the input end of the auxiliary integrator.
In the analog-to-digital conversion circuit, the second chopper unit 2 includes a fourth chopper module 14 and a fifth chopper module 15. The input end of the fourth chopper module 14 is electrically connected with the output end of the capacitor assembly, and the output end is electrically connected with the input end of the integrating capacitor assembly; the input end of the fifth chopper module 15 is electrically connected with the output end of the integrating capacitor unit, and the output end is electrically connected with the auxiliary integrator; the fourth chopper module 14 is configured to perform chopper modulation on the third offset voltage, and output the chopper-modulated third offset voltage to the fifth chopper module 15; the fifth chopper module 15 is configured to perform chopper demodulation processing on the third offset voltage, and output the chopper-demodulated third offset voltage to the secondary integrator.
The fourth chopper module 14 includes, in order from top to bottom, a thirteenth chopper switch, a fourteenth chopper switch, a fifteenth chopper switch, and a sixteenth chopper switch. The input end of the thirteenth chopper switch is electrically connected with the positive phase end of the output end of the sampling capacitor assembly 3, and the output end is electrically connected with the negative phase end of the input end of the integrating capacitor assembly 4; the input end of the fourteenth chopper switch is electrically connected with the positive phase end of the output end of the sampling capacitor assembly 3, and the output end is electrically connected with the positive phase end of the input end of the integrating capacitor assembly 4; the input end of the fifteenth chopper switch is electrically connected with the negative phase end of the output end of the sampling capacitor assembly 3, and the output end is electrically connected with the negative phase end of the input end of the integrating capacitor assembly 4; the sixteenth chopper switch has an input terminal electrically connected to the negative phase terminal of the output terminal of the sampling capacitance component 3, and an output terminal electrically connected to the positive phase terminal of the input terminal of the integration capacitance component 4. The fifth chopper module 15 includes a seventeenth chopper switch, an eighteenth chopper switch, a nineteenth chopper switch, and a twentieth chopper switch; the input end of the seventeenth chopper switch is electrically connected with the positive phase end of the output end of the integrating capacitor component 4, and the output end is electrically connected with the negative phase end of the output end of the main integrator; the input end of the eighteenth chopper switch is electrically connected with the positive phase end of the output end of the integrating capacitor component 4, and the output end is electrically connected with the positive phase end of the output end of the main integrator; an input end of the nineteenth chopper switch is electrically connected with a negative phase end of an output end of the integrating capacitor component 4, and an output end of the nineteenth chopper switch is electrically connected with a negative phase end of an output end of the main integrator; the input end of the twentieth chopper switch is electrically connected with the negative phase end of the output end of the integrating capacitor assembly 4, and the output end is electrically connected with the positive phase end of the output end of the main integrator.
The analog-to-digital conversion circuit of the present embodiment includes an input module 6 and an output module 7. Specifically, the input module 6 is configured to introduce an input signal, where the input module 6 includes a positive phase input signal INP and a negative phase input signal INN, and further includes a low noise amplifier LNA (Low Noise Amplifier), and an output end of the low noise amplifier LNA is connected to the first chopper module 11. The output module 7 is configured to output the chopped signal for cancellation in a subsequent circuit by a low-pass filter, and the output module 7 includes a comparator module COMP, a positive-phase output signal OUTP, and a negative-phase output signal OUTN.
The analog-to-digital conversion circuit of the embodiment further comprises a clock control signal module 9, wherein the clock control signal module is used for generating a first clock signal CLK1 and a second clock signal CLK2 which are inverted and not overlapped as a main clock signal of the analog-to-digital conversion circuit; the first clock signal CLK1 is used to control the operating phase of the sampling capacitor assembly, and the second clock signal CLK2 is used to control the operating phase of the integrating capacitor assembly.
CLK2D is the delayed signal of CLK1 and CLK2, respectively. CHP1, CHP2 are a pair of inverted chopping control signals, the frequency of the CHP1, CHP2 signals being an integer multiple of the frequency of the CLK1, CLK2, CLK1D, CLK D signals. A1 and B1 are obtained by mixing CLK1D with CHP1 and CHP2 phases, respectively, A2 is obtained by mixing the result of exclusive-or between OUTP and CHP1 signals, the result of exclusive-or between OUTN and CHP2 signals, and the signal of CLK2D, and B2 is an inverted signal of A2.
Specifically, referring to fig. 1, for the first chopping unit 1, four chopping switches of the first chopping module 11 are controlled by clock signals CHP1, CHP2, respectively; the four chopper switches of the second chopper module 12 are respectively controlled by clock signals A1 and B1; the four chopper switches of the third chopper module 13 are respectively controlled by clock signals A2 and B2; the four chopper switches of the sixth chopper module 16 are controlled by clock signals A1 and B1 respectively; the four chopper switches of the fourth chopper module 14 are controlled by clock signals CHP1, CHP2, respectively; the four chopper switches of the fifth chopper module 15 are controlled by clock signals CHP1, CHP2, respectively; the positive phase end and the negative phase end of the analog-to-digital conversion circuit are controlled by a clock signal CLK1D at the output end of the buffer module 5; the positive phase end and the negative phase end of the analog-to-digital conversion circuit are controlled by a clock signal CLK2D at the input end of the fourth chopper module 14; the positive phase end and the negative phase end of the analog-digital conversion circuit are controlled by the signal CLK1 at the input end and the control end of the comparator of the output module 7.
The analog-to-digital conversion circuit further comprises a voltage interface module for inputting voltages to the first chopping unit 1, the feedforward Sigma-Delta analog-to-digital conversion module 10 and the output module 7, respectively. Specifically, the voltage interface module inputs a common-mode voltage VCM controlled by the clock signal CLK2D at both the positive phase terminal and the negative phase terminal of the output terminal of the second chopper module 12; the positive phase reference voltage VREFN, the negative phase reference voltage VREFP, the positive phase reference voltage VREFN and the negative phase reference voltage VREFP controlled by the clock signals A2, B2, A2 are respectively input to the ninth chopper switch, tenth chopper switch, eleventh chopper switch and twelfth chopper switch of the third chopper module 13. The common mode voltage VCM controlled by the clock signal CLK1 is input to both the positive phase end and the negative phase end of the output end of the capacitor assembly; the common mode voltage VCM controlled by the clock signal CLK2 is input to both the positive and negative phase terminals of the input terminal of the comparator COMP.
The analog-to-digital conversion circuit in the embodiment utilizes the chopping technology to respectively carry the offset voltages generated by different modules in the system to high frequency on the premise of not affecting the high-order feedforward Sigma-Delta analog-to-digital conversion function in the whole circuit, thereby effectively reducing the offset voltage of the whole system.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.
Claims (9)
1. The analog-to-digital conversion circuit is characterized by comprising a feedforward Sigma-Delta analog-to-digital conversion module, a buffer module, a first chopping unit and a second chopping unit; the feedforward Sigma-Delta analog-to-digital conversion module comprises a main integrator and a secondary integrator; the main integrator comprises a sampling capacitance component and an integrating capacitance component;
The first chopping unit is respectively and electrically connected with the buffer module and the auxiliary integrator; the second chopper unit is electrically connected with the integrating capacitor assembly; the main integrator is electrically connected with the auxiliary integrator;
The first chopping unit is used for carrying out chopping modulation and chopping demodulation on the first offset voltage generated by the buffer module and the second offset voltage generated by the sampling capacitor assembly, and outputting the first offset voltage and the second offset voltage to the secondary integrator; the second chopper unit is used for carrying out chopper modulation and chopper demodulation on the third offset voltage generated by the integrating capacitor assembly and outputting the third offset voltage to the auxiliary integrator;
The analog-to-digital conversion circuit also comprises an input module; the first chopping unit comprises a first chopping module, a second chopping module, a third chopping module and a sixth chopping module;
the input end of the first chopper module is electrically connected with the output end of the input module; the output end of the first chopper module is electrically connected with the input end of the buffer module;
The input end of the second chopper module is electrically connected with the output end of the buffer module; the output end of the second chopper module is electrically connected with the output end of the feedforward Sigma-Delta analog-to-digital conversion module;
the input end of the third chopper module is a reference voltage, and the output end of the third chopper module is electrically connected with the output end of the sampling capacitor assembly;
the input end of the sixth chopper module is electrically connected with the output end of the main integrator, and the output end of the sixth chopper module is electrically connected with the input end of the auxiliary integrator;
The first chopper module, the second chopper module and the third chopper module are used in cooperation, chopper modulation processing is carried out on the first offset voltage and the second offset voltage, and the first offset voltage and the second offset voltage after chopper modulation processing are output to the sixth chopper module;
The sixth chopper module is used for performing chopper demodulation processing on the first offset voltage and the second offset voltage, and outputting the first offset voltage and the second offset voltage after the chopper demodulation processing to the output end of the main integrator.
2. The analog-to-digital conversion circuit of claim 1, wherein,
The first chopping module further comprises a first chopping switch, a second chopping switch, a third chopping switch and a fourth chopping switch;
the input end of the first chopper switch is electrically connected with the positive phase end of the output end of the input module, and the output end of the first chopper switch is electrically connected with the negative phase end of the input end of the buffer module;
The input end of the second chopper switch is electrically connected with the positive phase end of the output end of the input module, and the output end of the second chopper switch is electrically connected with the positive phase end of the input end of the buffer module;
the input end of the third chopper switch is electrically connected with the negative phase end of the output end of the input module, and the output end of the third chopper switch is electrically connected with the negative phase end of the input end of the buffer module;
the input end of the fourth chopper switch is electrically connected with the negative phase end of the output end of the input module, and the output end of the fourth chopper switch is electrically connected with the positive phase end of the input end of the buffer module.
3. The analog-to-digital conversion circuit of claim 1, wherein,
The second chopping module further comprises a fifth chopping switch, a sixth chopping switch, a seventh chopping switch and an eighth chopping switch;
The input end of the fifth chopper switch is electrically connected with the positive phase end of the output end of the buffer module, and the output end of the fifth chopper switch is electrically connected with the negative phase end of the output end of the feedforward Sigma-Delta analog-to-digital conversion module;
the input end of the sixth chopper switch is electrically connected with the positive phase end of the output end of the buffer module, and the output end of the sixth chopper switch is electrically connected with the positive phase end of the output end of the feedforward Sigma-Delta analog-to-digital conversion module;
The input end of the seventh chopper switch is electrically connected with the negative phase end of the output end of the buffer module, and the output end of the seventh chopper switch is electrically connected with the negative phase end of the output end of the feedforward Sigma-Delta analog-to-digital conversion module;
The input end of the eighth chopper switch is electrically connected with the negative phase end of the output end of the buffer module, and the output end of the eighth chopper switch is electrically connected with the positive phase end of the output end of the feedforward Sigma-Delta analog-digital conversion module.
4. The analog-to-digital conversion circuit of claim 1, wherein,
The third chopping module comprises a ninth chopping switch, a tenth chopping switch, an eleventh chopping switch and a twelfth chopping switch;
The input end of the ninth chopper switch is electrically connected with a reference voltage, and the output end of the ninth chopper switch is electrically connected with the positive phase end of the output end of the sampling capacitor assembly;
The input end of the tenth chopper switch is electrically connected with a reference voltage, and the output end of the tenth chopper switch is electrically connected with the positive phase end of the output end of the sampling capacitor assembly;
The input end of the eleventh chopping switch is electrically connected with a reference voltage, and the output end of the eleventh chopping switch is electrically connected with the negative phase end of the output end of the sampling capacitor assembly;
The input end of the twelfth chopping switch is electrically connected with the reference voltage, and the output end of the twelfth chopping switch is electrically connected with the negative phase end of the output end of the sampling capacitor assembly.
5. The analog-to-digital conversion circuit of claim 1, wherein,
The sixth chopping module comprises a twenty-first chopping switch, a twenty-second chopping switch, a twenty-third chopping switch and a twenty-fourth chopping switch;
The input end of the twenty-first chopper switch is electrically connected with the positive phase end of the output end of the main integrator, and the output end of the twenty-first chopper switch is electrically connected with the negative phase end of the input end of the auxiliary integrator;
The input end of the twenty-second chopper switch is electrically connected with the positive phase end of the output end of the main integrator, and the output end of the twenty-second chopper switch is electrically connected with the positive phase end of the input end of the auxiliary integrator;
the input end of the twenty-third chopper switch is electrically connected with the negative phase end of the output end of the main integrator, and the output end of the twenty-third chopper switch is electrically connected with the negative phase end of the input end of the auxiliary integrator;
the input end of the twenty-fourth chopper switch is electrically connected with the negative phase end of the output end of the main integrator, and the output end is electrically connected with the positive phase end of the input end of the auxiliary integrator.
6. The analog-to-digital conversion circuit of claim 1, wherein the second chopping unit comprises a fourth chopping module and a fifth chopping module;
The input end of the fourth chopper module is electrically connected with the output end of the sampling capacitor assembly, and the output end of the fourth chopper module is electrically connected with the input end of the integrating capacitor assembly;
The input end of the fifth chopper module is electrically connected with the output end of the integrating capacitor assembly, and the output end of the fifth chopper module is electrically connected with the auxiliary integrator;
The fourth chopper module is used for carrying out chopper modulation on the third offset voltage and outputting the third offset voltage subjected to chopper modulation to the fifth chopper module; the fifth chopper module is used for carrying out chopper demodulation processing on the third offset voltage and outputting the third offset voltage subjected to chopper demodulation processing to the auxiliary integrator.
7. The analog-to-digital conversion circuit of claim 6, wherein,
The fourth chopping module comprises a thirteenth chopping switch, a fourteenth chopping switch, a fifteenth chopping switch and a sixteenth chopping switch;
the input end of the thirteenth chopper switch is electrically connected with the positive phase end of the output end of the sampling capacitor assembly, and the output end of the thirteenth chopper switch is electrically connected with the negative phase end of the input end of the integrating capacitor assembly;
the input end of the fourteenth chopper switch is electrically connected with the positive phase end of the output end of the sampling capacitor assembly, and the output end of the fourteenth chopper switch is electrically connected with the positive phase end of the input end of the integrating capacitor assembly;
The input end of the fifteenth chopper switch is electrically connected with the negative phase end of the output end of the sampling capacitor assembly, and the output end of the fifteenth chopper switch is electrically connected with the negative phase end of the input end of the integrating capacitor assembly;
The input end of the sixteenth chopper switch is electrically connected with the negative phase end of the output end of the sampling capacitor assembly, and the output end of the sixteenth chopper switch is electrically connected with the positive phase end of the input end of the integrating capacitor assembly.
8. The analog-to-digital conversion circuit of claim 6, wherein,
The fifth chopping module comprises a seventeenth chopping switch, an eighteenth chopping switch, a nineteenth chopping switch and a twentieth chopping switch;
The input end of the seventeenth chopper switch is electrically connected with the positive phase end of the output end of the integrating capacitor component, and the output end of the seventeenth chopper switch is electrically connected with the negative phase end of the output end of the main integrator;
The input end of the eighteenth chopper switch is electrically connected with the positive phase end of the output end of the integrating capacitor component, and the output end of the eighteenth chopper switch is electrically connected with the positive phase end of the output end of the main integrator;
The input end of the nineteenth chopping switch is electrically connected with the negative phase end of the output end of the integrating capacitor component, and the output end of the nineteenth chopping switch is electrically connected with the negative phase end of the output end of the main integrator;
the input end of the twentieth chopper switch is electrically connected with the negative phase end of the output end of the integrating capacitor component, and the output end is electrically connected with the positive phase end of the output end of the main integrator.
9. The analog-to-digital conversion circuit of claim 1, further comprising a clock control signal module for generating first and second clock signals that are non-overlapping in phase opposition; the first clock signal is used for controlling the working phase of the sampling capacitor assembly, and the second clock signal is used for controlling the working phase of the integrating capacitor assembly;
And/or the number of the groups of groups,
The analog-to-digital conversion circuit further comprises a voltage interface module, wherein the voltage interface module is respectively and electrically connected with the first chopping unit and the feedforward Sigma-Delta analog-to-digital conversion module, and is used for inputting a common-mode voltage to the first chopping unit and the feedforward Sigma-Delta analog-to-digital conversion module;
And/or the number of the groups of groups,
The analog-to-digital conversion circuit also comprises an output module, wherein the output module is electrically connected with the feedforward Sigma-Delta analog-to-digital conversion module and is used for outputting the modulated and demodulated signal to a low-pass filter.
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