CN107768310B - 一种阵列基板的制作方法、阵列基板及指纹识别器件 - Google Patents

一种阵列基板的制作方法、阵列基板及指纹识别器件 Download PDF

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CN107768310B
CN107768310B CN201710984474.8A CN201710984474A CN107768310B CN 107768310 B CN107768310 B CN 107768310B CN 201710984474 A CN201710984474 A CN 201710984474A CN 107768310 B CN107768310 B CN 107768310B
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CN107768310A (zh
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邸云萍
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BOE Technology Group Co Ltd
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Abstract

本发明公开了一种阵列基板的制作方法、阵列基板及指纹识别器件,该阵列基板的制作方法,包括:在衬底基板上形成一层多晶硅层,对多晶硅层进行构图,多晶硅层的图案在衬底基板上的正投影位于多个目标区域内;采用第一掺杂工艺,向对应于PIN型二极管的第一子区域,以及P型晶体管的第一子区域和第二子区域内的多晶硅层掺P型离子;采用第二掺杂工艺,向对应于PIN型二极管的第二子区域,以及N型晶体管的第一子区域和第二子区域内的多晶硅层掺N型离子。本发明实施例提供的制作方法,实现了将晶体管的工艺制程与PIN型二极管的工艺制程集成到一起,从而简化阵列基板的工艺流程,降低成本。

Description

一种阵列基板的制作方法、阵列基板及指纹识别器件
技术领域
本发明涉及传感器技术领域,尤指一种阵列基板的制作方法、阵列基板及指纹识别器件。
背景技术
指纹是人体与生俱来独一无二并可与他人相区别的不变特征。它由指端皮肤表面上的一系列脊和谷组成。这些脊和谷的组成细节通常包括脊的分叉、脊的末端、拱形、帐篷式的拱形、左旋、右旋、螺旋或双旋等细节,决定了指纹图案的唯一性。由之发展起来的指纹识别技术是较早被用作为个人身份验证的技术,根据指纹采集、输入的方式不同,目前广泛应用并被熟知的有:光学成像、热敏传感器、人体远红外传感器等。
目前,超声波指纹识别尚属于一个新技术领域,相比电容式指纹识别器件,超声波指纹识别性能更优:可防水防汗、传感器大面积化、识别假指纹、支持更厚封装层。此外,超声波还可进行脉搏、血压等其他功能识别。超声波指纹识别产品需要将CMOS晶体管器件与PIN型二极管器件集成,现有成熟工艺技术是在晶圆硅基底上通过半导体制程来实现的,但现有技术中CMOS晶体管器件的工艺制程与PIN型二极管器件的工艺制程是分开的,导致制作超声波指纹识别器件的工艺流程非常复杂,工艺成本高。
发明内容
本发明实施例提供了一种阵列基板的制作方法、阵列基板及指纹识别器件,用以解决现有技术中存在的制作超声波指纹识别器件的工艺流程非常复杂,工艺成本高的问题。
第一方面,本发明实施例提供了一种阵列基板的制作方法,所述阵列基板,包括多个目标区域组,每个所述目标区域组至少包括两个不同的目标区域;每一个所述目标区域为PIN型二极管或P型晶体管或N型晶体管,且每一个所述目标区域分为第一子区域,第二子区域,以及位于所述第一子区域和所述第二子区域之间的第三子区域;
所述阵列基板的制作方法,包括:
在衬底基板上形成一层多晶硅层,对所述多晶硅层进行构图,所述多晶硅层的图案在所述衬底基板上的正投影位于多个所述目标区域内;
针对P型晶体管,采用第一掺杂工艺,向对应于所述PIN型二极管的所述第一子区域,以及所述P型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺P型离子;
针对N型晶体管,采用第二掺杂工艺,向对应于所述PIN型二极管的所述第二子区域,以及所述N型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺N型离子。
在一种可能的实现方式中,在本发明实施例提供的上述制作方法中,所述晶体管包括P型晶体管和N型晶体管;
所述采用第一掺杂工艺,向对应于所述PIN型二极管的所述第一子区域,以及所述P型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺P型离子,包括:
在所述多晶硅层之上形成一层金属层,对所述金属层进行第一次构图后,得到的所述金属层的图形覆盖所述N型晶体管对应的所述目标区域,所述P型晶体管对应的所述第三子区域,以及所述PIN型二极管对应的所述第二子区域和所述第三子区域;
以第一次构图后的所述金属层为遮挡,向所述多晶硅层掺P型离子。
在一种可能的实现方式中,在本发明实施例提供的上述制作方法中,所述采用第二掺杂工艺,向对应于所述PIN型二极管的所述第二子区域,以及所述N型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺N型离子,包括:
对所述金属层进行第二次构图后,得到的所述金属层的图形覆盖所述N型晶体管对应的所述第三子区域的中间区域,所述P型晶体管对应的所述第三子区域,以及所述PIN型二极管对应的所述第二子区域和所述第三子区域;
形成第一光刻胶层,对所述第一光刻胶层进行第一次构图后,得到的所述第一光刻胶层的图形覆盖所述N型晶体管对应的所述第三子区域,所述P型晶体管的对应的所述目标区域,以及所述PIN型二极管对应的所述目标区域;
以第一次构图后的所述第一光刻胶层为遮挡,向所述多晶硅层掺N型离子。
在一种可能的实现方式中,在本发明实施例提供的上述制作方法中,所述采用第二掺杂工艺,向对应于所述PIN型二极管的所述第二子区域,以及所述N型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺N型离子,还包括:
对所述第一光刻胶层进行第二次构图,得到的所述第一光刻胶层的图形覆盖所述N型晶体管对应的所述第三子区域的中间区域,所述P型晶体管的对应的所述目标区域,以及所述PIN型二极管对应的所述目标区域;
以第二次构图后的所述第一光刻胶层为遮挡,向所述多晶硅层掺杂,以形成所述N型晶体管的轻掺杂漏区。
在一种可能的实现方式中,在本发明实施例提供的上述制作方法中,所述采用第二掺杂工艺,向对应于所述PIN型二极管的所述第二子区域,以及所述N型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺N型离子,还包括:
对所述金属层进行第三次构图后,得到的所述金属层的图形覆盖所述N型晶体管对应的所述第三子区域的中间区域,所述P型晶体管对应的所述第三子区域,以及所述PIN型二极管对应的所述第三子区域;
形成第二光刻胶层,对所述第二光刻胶层进行第一次构图后,得到的所述第二光刻胶层的图形覆盖所述N型晶体管对应的所述目标区域,所述P型晶体管的对应的所述目标区域,以及所述PIN型二极管对应的所述第一子区域和所述第三子区域靠近所述第一子区域的部分区域;
以所述第一次构图后的所述第二光刻胶层为遮挡,向所述多晶硅层掺N型离子。
在一种可能的实现方式中,在本发明实施例提供的上述制作方法中,所述以所述第一次构图后的所述第二光刻胶层为遮挡,向所述多晶硅层掺N型离子之后,还包括:
对所述第二光刻胶层进行第二次构图后,得到的所述第二光刻胶层的图形覆盖所述N型晶体管对应的所述目标区域,所述P型晶体管的对应的所述目标区域,以及所述PIN型二极管对应的所述第一子区域和所述第三子区域靠近所述第一子区域的部分区域;
以第二次构图后的所述第二光刻胶层为遮挡,向所述多晶硅层掺杂,以形成所述PIN型二极管的轻掺杂漏区。
在一种可能的实现方式中,在本发明实施例提供的上述制作方法中,所述采用第二掺杂工艺,向对应于所述PIN型二极管的所述第二子区域,以及所述N型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺N型离子,包括:
对所述金属层进行第二次构图后,得到的所述金属层的图形覆盖所述N型晶体管对应的所述第三子区域的中间区域,所述P型晶体管对应的所述第三子区域,以及所述PIN型二极管对应的所述第三子区域靠近所述第一子区域的部分区域;
形成第一光刻胶层,对所述第一光刻胶层进行第一次构图后,得到的所述第一光刻胶层的图形覆盖所述N型晶体管对应的所述第三子区域,所述P型晶体管的对应的所述目标区域,以及所述PIN型二极管对应的所述第一子区域和所述第三子区域;
以第一次构图后的所述第一光刻胶层为遮挡,向所述多晶硅层掺N型离子。
在一种可能的实现方式中,在本发明实施例提供的上述制作方法中,所述以第一次构图后的所述第一光刻胶层为遮挡,向所述多晶硅层掺N型离子之后,还包括:
对所述第一光刻胶层进行第二次构图后,得到的所述第一光刻胶层的图形覆盖所述N型晶体管对应的所述第三子区域的中间区域,所述P型晶体管的对应的所述目标区域,以及所述PIN型二极管对应的所述第一子区域和所述第三子区域靠近第一子区域的部分区域;
以第二次构图后的所述第一光刻胶层为遮挡,向所述多晶硅层掺杂,以形成所述PIN型二极管的轻掺杂漏区。
第二方面,本发明实施例还提供了一种阵列基板,所述阵列基板采用上述制作方法制作而成。
第三方面,本发明实施例还提供了一种指纹识别器件,包括:上述阵列基板。
本发明有益效果如下:
本发明实施例提供的阵列基板的制作方法、阵列基板及指纹识别器件,该阵列基板的制作方法,包括:在衬底基板上形成一层多晶硅层,对多晶硅层进行构图,多晶硅层的图案在衬底基板上的正投影位于多个目标区域内;采用第一掺杂工艺,向对应于PIN型二极管的第一子区域,以及P型晶体管的第一子区域和第二子区域内的多晶硅层掺P型离子;采用第二掺杂工艺,向对应于PIN型二极管的第二子区域,以及N型晶体管的第一子区域和第二子区域内的多晶硅层掺N型离子。本发明实施例提供的制作方法,实现了将晶体管的工艺制程与PIN型二极管的工艺制程集成到一起,从而简化阵列基板的工艺流程,降低成本。
附图说明
图1为本发明实施例中阵列基板的区域划分示意图;
图2为本发明实施例提供的阵列基板的制作方法的流程图之一;
图3a~图3o,图4a以及图4b为本发明实施例中上述阵列基板的制作方法中的结构示意图;
图5为本发明实施例提供的阵列基板的制作方法的流程图之二;
图6为本发明实施例提供的阵列基板的制作方法的流程图之三;
图7为本发明实施例提供的阵列基板的制作方法的流程图之四;
图8为本发明实施例提供的阵列基板的制作方法的流程图之五;
图9为本发明实施例提供的阵列基板的制作方法的流程图之六。
具体实施方式
针对现有技术中存在的制作超声波指纹识别器件的工艺流程非常复杂,工艺成本高的问题,本发明实施例提供了一种阵列基板的制作方法、阵列基板及指纹识别器件。
下面结合附图,对本发明实施例提供的阵列基板的制作方法、阵列基板及指纹识别器件的具体实施方式进行详细地说明。附图中各膜层的厚度和形状不反映真实比例,目的只是示意说明本发明内容。
第一方面,本发明实施例提供了一种阵列基板的制作方法,如图1所示,该阵列基板,包括多个目标区域组,每个目标区域组至少包括两个不同的目标区域A;每一个目标区域A为PIN型二极管或P型晶体管或N型晶体管,且每一个目标区域A分为第一子区域a,第二子区域b,以及位于第一子区域a和第二子区域b之间的第三子区域c;
应该说明的是,图1中以该阵列基板包括三个目标区域A,目标区域A为方形,且并排设置为例进行示意,在实际应用中,该阵列基板上可以包括更多个目标区域A,且该目标区域A的形状和分布可以根据实际需要来设置,此次不对目标区域的大小,形状,分布以及数量进行限定。为了更清晰明了的示意阵列基板的结构,在后续的附图中对于同一个目标区域,均以左侧的子区域为第一子区域,右侧的子区域为第二子区域,以及中间的子区域为第三子区域为例,因此,在后续附图中,不对目标子区域以及各子区域进行标号。
如图2所示,本发明实施例提供的上述阵列基板的制作方法,包括:
S11、在衬底基板上形成一层多晶硅层,对多晶硅层进行构图,多晶硅层的图案在衬底基板上的正投影位于多个目标区域内;
S12、采用第一掺杂工艺,向对应于PIN型二极管的第一子区域,以及P型晶体管(即PMOS晶体管)的第一子区域和第二子区域内的多晶硅层掺P型离子;
S13、采用第二掺杂工艺,向对应于PIN型二极管的第二子区域,以及N型晶体管(即NMOS晶体管)的第一子区域和第二子区域内的多晶硅层掺N型离子;在实际应用中,步骤S12和步骤S13的顺序可以互换。
本发明实施例提供的制作方法,可以通过第一掺杂工艺实现PIN型二极管和P型晶体管的P型离子掺杂,可以通过第二掺杂工艺实现PIN型二极管和N型晶体管的N型离子掺杂,从而实现了将晶体管的工艺制程与PIN型二极管的工艺制程集成到一起,从而简化阵列基板的工艺流程,降低成本。
在实际应用中,晶体管可以分为P型晶体管和N型晶体管两种,本发明实施例中将晶体管与PIN型二极管集成于同一阵列基板中,包括以下几种情况:
情况一:该阵列基板包括PIN型二极管和P型晶体管两种器件,在工艺过程中,采用第一掺杂工艺,同时向PIN型二极管的第一子区域,以及P型晶体管的第一子区域和第二子区域中的多晶硅层掺P型离子;即采用同一工艺向PIN型二极管与P型晶体管掺P型离子;
情况二:该阵列基板包括PIN型二极管和N型晶体管两种器件,在工艺过程中,采用第二掺杂工艺,同时向PIN型二极管的第二子区域,以及N型晶体管的第一子区域和第二子区域中的多晶硅层掺N型离子;即采用同一工艺向PIN型二极管与N型晶体管掺N型离子;
情况三:该阵列基板包括PIN型二极管,P型晶体管和N型晶体管三种器件,此时存在三种PIN型二极管和晶体管的工艺集成方式,方式一:采用同一工艺向PIN型二极管与P型晶体管掺P型离子,以及采用两次掺杂工艺向PIN型二极管与N型晶体管掺N型离子;方式二:采用同一工艺向PIN型二极管与N型晶体管掺N型离子,以及采用两次掺杂工艺向PIN型二极管与P型晶体管掺P型离子;方式三:采用同一工艺向PIN型二极管与P型晶体管掺P型离子,以及采用同一工艺向PIN型二极管与N型晶体管掺N型离子。
因此,本发明实施例提供的阵列基板的制作方法可以适用于多种PIN型二极管与晶体管的集成方案中,在本发明实施中,以情况三为例进行详细说明,对于情况一和情况二,只需对情况三的工艺流程稍作变化即可得到,例如对于情况一,可以将情况三中各工艺步骤中使用的掩膜版进行修改,将掩膜版上对应于N型晶体管的位置处遮住,其他工艺步骤可以相同,情况二的修改方式与情况一类似,此次不再赘述。
以下结合附图,对本发明实施例的最优实施方式(即上述晶体管包括P型晶体管和N型晶体管)进行详细说明:
在具体实施时,在上述步骤S11之前,如图5所示,还可以包括:
S101、在衬底基板201上沉积一层非晶硅(a-Si)层202,如图3a所示;
S102、采用激光退火工艺对上述非晶硅层进行晶化处理,得到如图3b所示的多晶硅层203;
S103、对多晶硅层203进行图案化,得到如图3c所示的结构,在实际应用中,步骤S102与步骤S103的顺序可以互换,即可以先对多晶硅层203进行图案化,再对多晶硅层203进行激光退火工艺。图3c中以第一个目标区域用来形成N型晶体管(即图中的NMOS TFT),第二个目标区域用来形成P型晶体管(即图中的PMOS TFT)以及第三个目标区域用来形成PIN型二极管(即图中的PIN)为例进行示意,在实际应用中,可以根据实际需要设置N型晶体管,P型晶体管以及PIN型二极管的数量和位置,此处不做限定;
S104、对N型晶体管和PMOS晶体管的沟道区域进行轻掺杂,以及对PIN型二极管的中间区域进行轻掺杂形成PIN型二极管的I区;具体地,如图3d所示,采用第三光刻胶层204将N型晶体管对应的目标区域遮住,对多晶硅层203进行轻掺杂,即对P型晶体管和PIN型二极管进行轻掺杂,以使P型晶体管形成具有特定阈值电压的沟道区域,以及PIN型二极管形成I区;如图3e所示,采用第四光刻胶层205将P型晶体管和PIN型二极管对应的目标区域遮住,对多晶硅层203进行轻掺杂,即对N型晶体管进行轻掺杂,以使NOMS晶体管形成具有特定阈值电压的沟道区域;应该说明的是,由于S104中的掺杂浓度较低,在1011~1012cm-3,而且后续还要对第一子区域和第三子区域进行重掺杂,因此,步骤S104中,无需对各目标区域中的第一子区域和第三子区域进行遮挡;
S105、在多晶硅层之上形成栅极绝缘层206,如图3f所示,以绝缘多晶硅层与后续形成的金属层(即栅极层),应该说明的是,上述步骤S104中进行轻掺杂时,离子可以穿过绝缘层,因此上述步骤S104与上述步骤S105的顺序可以互换。
具体地,如图6所示,上述步骤S12可以包括:
S121、在多晶硅层203之上形成一层金属层207(即栅极层),对金属层207进行第一次构图后,如图3g所示,得到的金属层207的图形覆盖N型晶体管对应的目标区域,P型晶体管对应的第三子区域,以及PIN型二极管对应的第二子区域和第三子区域;即对金属层207进行第一次构图后,只有P型晶体管对应的第一子区域和第二子区域,以及PIN型二极管的第一子区域没有被金属层207遮挡,也就是将要进行P型离子掺杂的区域没有被金属层207遮挡;
S122、同样参照图3g,以第一次构图后的金属层207为遮挡,向多晶硅层203掺P型离子,例如可以掺浓度约为1013~1015cm-3的硼离子。
本发明实施例中,采用同一工艺向P型晶体管和PIN型二极管中掺P型离子,在满足P型晶体管和PIN型二极管的特性参数的基础上,可以减少工艺步骤,节约工艺成本。
本发明实施例提供了两种掺杂N型离子,以及轻掺杂漏区(Lightly Doped Drain,LDD)掺杂的实现方式,以下结合附图进行详细说明;
实现方式一:
具体地,如图7所示,上述步骤S13可以包括:
S131、如图3h所示,对金属层207进行第二次构图后,得到的金属层207的图形覆盖N型晶体管对应的第三子区域的中间区域,P型晶体管对应的第三子区域,以及PIN型二极管对应的第二子区域和第三子区域;即对金属层207进行第二次构图后,只有N型晶体管对应的第一子区域和第二子区域,以及第三子区域的边缘区域没有被金属层207的图形遮挡,也就是只有N型晶体管中将要掺N型离子的区域以及将要进行LDD掺杂的区域没有被金属层207遮挡。应该说明的是,上述第三子区域的中间区域,可以指第三子区域除与第一子区域接触的区域,以及与第二子区域接触的区域以外的大部分区域;步骤S131中不完全遮挡N型晶体管对应的第三子区域是为了后续在第三子区域和第一子区域,以及第三子区域和第二子区域之间的位置形成LDD轻掺杂区,以降低漏电流;
S132、同样参照图3h,形成第一光刻胶层208,对第一光刻胶层208进行第一次构图后,得到的第一光刻胶层208的图形覆盖N型晶体管对应的第三子区域,P型晶体管的对应的目标区域,以及PIN型二极管对应的目标区域;即第一次构图后的第一光刻胶层208的图形,覆盖了除N型晶体管对应的第一子区域和第二子区域外的区域,也就是说只有N型晶体管中将要掺杂N型离子的区域没有被第一光刻胶层208遮挡;
S133、参照图3h,以第一次构图后的第一光刻胶层208为遮挡,向多晶硅层掺N型离子,例如可以掺一定浓度的磷离子。
进一步地,如图7所示,上述步骤S133之后,上述步骤S13还可以包括:
S134、如图3i所示,对第一光刻胶层208进行第二次构图,得到的第一光刻胶层208的图形覆盖N型晶体管对应的第三子区域的中间区域,P型晶体管的对应的目标区域,以及PIN型二极管对应的目标区域;即第二次构图后的第一光刻胶层208遮挡了除N型晶体管的第一子区域,第二子区域,以及第三子区域的边缘区域以外的区域,也就是说只有N型晶体管中掺杂N型离子的区域以及将要进行LDD掺杂的区域没有被遮挡;
S135、同样参照图3i,以第二次构图后的第一光刻胶层208为遮挡,向多晶硅层203掺杂,以形成N型晶体管的轻掺杂漏区。
本发明实施例中,LDD轻掺杂区位于重掺杂区(掺N型离子或P型离子的区域)与沟道区域之间,起到过渡区的作用,可以起到降低漏电流的作用。
更进一步地,同样参照图7,上述步骤S135之后,上述步骤S13还可以包括:
S136、如图3j所示,对金属层207进行第三次构图后,得到的金属层207的图形覆盖N型晶体管对应的第三子区域的中间区域,P型晶体管对应的第三子区域,以及PIN型二极管对应的第三子区域靠近第一子区域的部分区域;在本发明实施例中,上述第三子区域的中间区域,可以指第三子区域除与第一子区域接触的区域,以及与第二子区域接触的区域以外的大部分区域,第三子区域靠近第一子区域的部分区域,可以指第三子区域处与第二子区域接触的区域外的大部分区域。第三次构图后的金属层207的图形仅遮挡了晶体管的沟道区域和PIN型二极管的I区,需要进行N型离子掺杂的区域以及LDD轻掺杂的区域都没有被金属层207遮挡。
S137、参照图3j,形成第二光刻胶层209,对第二光刻胶层209进行第一次构图后,得到的第二光刻胶层209的图形覆盖N型晶体管对应的目标区域,P型晶体管的对应的目标区域,以及PIN型二极管对应的第一子区域和第三子区域;即第一次构图后的第二光刻胶层209遮挡了除PIN型二极管对应的第二子区域以外的区域,即只有PIN型二极管中将要进行N型掺杂的区域没有被金属层207遮挡;
S138、同样参照图3j,以第一次构图后的第二光刻胶层209为遮挡,向多晶硅层掺N型离子。
在本发明实施例中的实现方式一中,对N型晶体管掺N型离子,与对PIN型二极管掺N离子不在同一工艺形成,从而可以单独控制掺入PIN型二极管中N型离子的浓度,使PIN型二极管的工艺参数更加灵活。本发明实施例中优选为向P型晶体管中掺P型离子,与向PIN型二极管中掺P型离子采用同一工艺,对N型晶体管掺N型离子,与对PIN型二极管掺N离子采用不同的工艺形成,使由于在工艺过程中,掺N型离子需要考虑有源层的宽度和栅极的宽度,及掺N型离子的工艺比掺P型离子的工艺复杂。
在实际应用中,上述步骤S138之后,还可以包括(图中未示出):
S14、如图3k所示,对第二光刻胶层209进行第二次构图后,得到的第二光刻胶层209的图形覆盖N型晶体管对应的目标区域,P型晶体管的对应的目标区域,以及PIN型二极管对应的第一子区域和第三子区域靠近第一子区域的部分区域;即第二次构图后的第二光刻胶层209覆盖了除PIN型二极管对应的第二子区域和第三子区域靠近第二子区域的边缘区域以外的区域,也就是只有PIN型二极管中掺杂N型离子的区域,以及将要进行LDD轻掺杂的区域没有被遮挡;
S15、同样参照图3k,以第二次构图后的第二光刻胶层209为遮挡,向多晶硅层203掺杂,以形成PIN型二极管的轻掺杂漏区。
实现方式二:
具体地,上述步骤S13,如图8所示,可以包括:
S131′、如图4a所示,对金属层207进行第二次构图后,得到的金属层207的图形覆盖N型晶体管对应的第三子区域的中间区域,P型晶体管对应的第三子区域,以及PIN型二极管对应的第三子区域靠近第一子区域的部分区域;即第二次构图后的金属层207的图形仅遮挡了晶体管的沟道区域和PIN型二极管的I区,需要进行N型离子掺杂的区域以及LDD轻掺杂的区域都没有被金属层207遮挡;
S132′、参照图4a,形成第一光刻胶层208,对第一光刻胶层208进行第一次构图后,得到的第一光刻胶层208的图形覆盖N型晶体管对应的第三子区域,P型晶体管的对应的目标区域,以及PIN型二极管对应的第一子区域和第三子区域;即第一次构图后的第一光刻胶层208遮挡了晶体管的沟道区域,PIN型二极管的I区,掺杂P离子的区域,以及LDD轻掺杂的区域,也就是说只有将要进行N型离子掺杂的区域没有被遮挡;
S133′、同样参照图4a,以第一次构图后的第一光刻胶层208为遮挡,向多晶硅层掺N型离子。
实现方式二中,采用同一工艺完成了阵列基板上所有区域中N型离子的掺杂,减少了工艺步骤以及掩膜版的数量,降低了工艺成本。
进一步地,在上述步骤S133′之后,如图8所示,还可以包括:
S14′、如图4b所示,对第一光刻胶层208进行第二次构图后,得到的第一光刻胶层208的图形覆盖N型晶体管对应的第三子区域的中间区域,P型晶体管的对应的目标区域,以及PIN型二极管对应的第一子区域和第三子区域靠近第一子区域的部分区域;即第二次构图后的第一光刻胶层208遮挡了晶体管的沟道区域,PIN型二极管的I区,以及掺杂P离子的区域,也就是说,只有掺杂N型离子的区域,以及将要进行LDD掺杂的区域没有被遮挡;
S15′、同样参照图4b,以第二次构图后的第一光刻胶层208为遮挡,向多晶硅层掺杂,以形成PIN型二极管的轻掺杂漏区。
在实际应用中,由于掺杂N型离子的区域为重掺杂,向该区域内再掺入LDD轻掺杂不会对掺杂N型离子的区域产生影响。此外,还可以先对LDD轻掺杂的区域和掺N型离子的区域进行LDD轻掺杂,然后将LDD轻掺杂的区域遮挡,再进行N离子掺杂,此处不对LDD轻掺杂和N型离子掺杂的顺序进行限定。
实现方式二中,采用同一工艺完成了阵列基板上所有区域中LDD轻掺杂,进一步减少了工艺步骤以及掩膜版的数量,降低了工艺成本。
进一步地,本发明实施例提供的上述制作方法中,对N型晶体管,P型晶体管以及PIN型二极管掺杂之后,如图9所示,还可以包括以下步骤:
S16、如图3l所示,在金属层207之上形成一层层间绝缘层210(ILD),并对层间绝缘层210以及栅极绝缘层206进行构图,将掺杂P型离子的区域和掺杂N型离子的区域露出来,即露出晶体管的源极导电区和漏极导电区,以及PIN型二极管的P区和N区;
S17、如图3m所示,在层间绝缘层210之上,采用金属材料形成一层源漏金属层211,并对源漏金属层211进行构图,以形成晶体管的源极(S)和漏极(D),以及PIN型二极管的第一电极(T)和第二电极(W);
S18、如图3n所示,在源漏金属层211之上形成一层平坦层212,并对平坦层212进行构图,露出晶体管的源极(S)和漏极(D),以及PIN型二极管的第一电极(T)和第二电极(W);
S19、如图3o所示,在平坦层212之上,形成一层电极层213,并对电极层213进行构图,以形成分别连接晶体管的源极(S)和漏极(D),以及PIN型二极管的第一电极(T)和第二电极(W)的电极,具体地,电极层可以采用透明的金属氧化物导电材料,例如氧化铟锡(Indium tin oxide,ITO),也可以采用其他材料,此处不做限定。
基于同一发明构思,本发明实施例还提供了一种阵列基板,该阵列基板采用上述制作方法制作而成。由于该阵列基板解决问题的原理与上述阵列基板的制作方法相似,因此该阵列基板的实施可以参见上述阵列基板的制作方法的实施,重复之处不再赘述。
基于同一发明构思,本发明实施例还提供了一种指纹识别器件,包括上述阵列基板。由于该指纹识别器件解决问题的原理与上述阵列基板相似,因此该指纹识别器件的实施可以参见上述阵列基板的实施,重复之处不再赘述。
此外,上述阵列基板也可以应用于显示装置中,例如可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明实施例提供的阵列基板的制作方法、阵列基板及指纹识别器件,通过与第一掺杂工艺或第二掺杂工艺采用同一工艺,向对应于晶体管的第一子区域和第二子区域内的多晶硅层进行掺杂,从而实现了将晶体管的工艺制程与PIN型二极管的工艺制程集成到一起,从而简化阵列基板的工艺流程,降低成本。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。

Claims (6)

1.一种阵列基板的制作方法,其特征在于,所述阵列基板,包括多个目标区域组,每个所述目标区域组至少包括两个不同的目标区域;每一个所述目标区域为PIN型二极管或P型晶体管或N型晶体管,且每一个所述目标区域分为第一子区域,第二子区域,以及位于所述第一子区域和所述第二子区域之间的第三子区域;
所述阵列基板的制作方法,包括:
在衬底基板上形成一层多晶硅层,对所述多晶硅层进行构图,所述多晶硅层的图案在所述衬底基板上的正投影位于多个所述目标区域内;
采用第一掺杂工艺,向对应于所述PIN型二极管的所述第一子区域,以及所述P型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺P型离子;
采用第二掺杂工艺,向对应于所述PIN型二极管的所述第二子区域,以及所述N型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺N型离子;
所述晶体管包括P型晶体管和N型晶体管;
所述采用第一掺杂工艺,向对应于所述PIN型二极管的所述第一子区域,以及所述P型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺P型离子,包括:
在所述多晶硅层之上形成一层金属层,对所述金属层进行第一次构图后,得到的所述金属层的图形覆盖所述N型晶体管对应的所述目标区域,所述P型晶体管对应的所述第三子区域,以及所述PIN型二极管对应的所述第二子区域和所述第三子区域;
以第一次构图后的所述金属层为遮挡,向所述多晶硅层掺P型离子;
所述采用第二掺杂工艺,向对应于所述PIN型二极管的所述第二子区域,以及所述N型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺N型离子,包括:
对所述金属层进行第二次构图后,得到的所述金属层的图形覆盖所述N型晶体管对应的所述第三子区域的中间区域,所述P型晶体管对应的所述第三子区域,以及所述PIN型二极管对应的所述第二子区域和所述第三子区域;
形成第一光刻胶层,对所述第一光刻胶层进行第一次构图后,得到的所述第一光刻胶层的图形覆盖所述N型晶体管对应的所述第三子区域,所述P型晶体管的对应的所述目标区域,以及所述PIN型二极管对应的所述目标区域;
以第一次构图后的所述第一光刻胶层为遮挡,向所述多晶硅层掺N型离子;
对所述第一光刻胶层进行第二次构图,得到的所述第一光刻胶层的图形覆盖所述N型晶体管对应的所述第三子区域的中间区域,所述P型晶体管的对应的所述目标区域,以及所述PIN型二极管对应的所述目标区域;
以第二次构图后的所述第一光刻胶层为遮挡,向所述多晶硅层掺杂,以形成所述N型晶体管的轻掺杂漏区。
2.如权利要求1所述的制作方法,其特征在于,所述采用第二掺杂工艺,向对应于所述PIN型二极管的所述第二子区域,以及所述N型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺N型离子,还包括:
对所述金属层进行第三次构图后,得到的所述金属层的图形覆盖所述N型晶体管对应的所述第三子区域的中间区域,所述P型晶体管对应的所述第三子区域,以及所述PIN型二极管对应的所述第三子区域;
形成第二光刻胶层,对所述第二光刻胶层进行第一次构图后,得到的所述第二光刻胶层的图形覆盖所述N型晶体管对应的所述目标区域,所述P型晶体管的对应的所述目标区域,以及所述PIN型二极管对应的所述第一子区域和所述第三子区域靠近所述第一子区域的部分区域;
以所述第一次构图后的所述第二光刻胶层为遮挡,向所述多晶硅层掺N型离子。
3.如权利要求2所述的制作方法,其特征在于,所述以所述第一次构图后的所述第二光刻胶层为遮挡,向所述多晶硅层掺N型离子之后,还包括:
对所述第二光刻胶层进行第二次构图后,得到的所述第二光刻胶层的图形覆盖所述N型晶体管对应的所述目标区域,所述P型晶体管的对应的所述目标区域,以及所述PIN型二极管对应的所述第一子区域和所述第三子区域靠近所述第一子区域的部分区域;
以第二次构图后的所述第二光刻胶层为遮挡,向所述多晶硅层掺杂,以形成所述PIN型二极管的轻掺杂漏区。
4.一种阵列基板的制作方法,其特征在于,所述阵列基板,包括多个目标区域组,每个所述目标区域组至少包括两个不同的目标区域;每一个所述目标区域为PIN型二极管或P型晶体管或N型晶体管,且每一个所述目标区域分为第一子区域,第二子区域,以及位于所述第一子区域和所述第二子区域之间的第三子区域;
所述阵列基板的制作方法,包括:
在衬底基板上形成一层多晶硅层,对所述多晶硅层进行构图,所述多晶硅层的图案在所述衬底基板上的正投影位于多个所述目标区域内;
采用第一掺杂工艺,向对应于所述PIN型二极管的所述第一子区域,以及所述P型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺P型离子;
采用第二掺杂工艺,向对应于所述PIN型二极管的所述第二子区域,以及所述N型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺N型离子;
所述晶体管包括P型晶体管和N型晶体管;
所述采用第一掺杂工艺,向对应于所述PIN型二极管的所述第一子区域,以及所述P型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺P型离子,包括:
在所述多晶硅层之上形成一层金属层,对所述金属层进行第一次构图后,得到的所述金属层的图形覆盖所述N型晶体管对应的所述目标区域,所述P型晶体管对应的所述第三子区域,以及所述PIN型二极管对应的所述第二子区域和所述第三子区域;
以第一次构图后的所述金属层为遮挡,向所述多晶硅层掺P型离子;
所述采用第二掺杂工艺,向对应于所述PIN型二极管的所述第二子区域,以及所述N型晶体管的所述第一子区域和所述第二子区域内的所述多晶硅层掺N型离子,包括:
对所述金属层进行第二次构图后,得到的所述金属层的图形覆盖所述N型晶体管对应的所述第三子区域的中间区域,所述P型晶体管对应的所述第三子区域,以及所述PIN型二极管对应的所述第三子区域靠近所述第一子区域的部分区域;
形成第一光刻胶层,对所述第一光刻胶层进行第一次构图后,得到的所述第一光刻胶层的图形覆盖所述N型晶体管对应的所述第三子区域,所述P型晶体管的对应的所述目标区域,以及所述PIN型二极管对应的所述第一子区域和所述第三子区域;
以第一次构图后的所述第一光刻胶层为遮挡,向所述多晶硅层掺N型离子;
对所述第一光刻胶层进行第二次构图后,得到的所述第一光刻胶层的图形覆盖所述N型晶体管对应的所述第三子区域的中间区域,所述P型晶体管的对应的所述目标区域,以及所述PIN型二极管对应的所述第一子区域和所述第三子区域靠近第一子区域的部分区域;
以第二次构图后的所述第一光刻胶层为遮挡,向所述多晶硅层掺杂,以形成所述PIN型二极管的轻掺杂漏区。
5.一种阵列基板,其特征在于,所述阵列基板采用如权利要求1~3任一项所述的制作方法制作而成;或,
所述阵列基板采用如权利要求4所述的制作方法制作而成。
6.一种指纹识别器件,其特征在于,包括:如权利要求5所述的阵列基板。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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CN102197485A (zh) * 2008-10-23 2011-09-21 夏普株式会社 半导体装置及其制造方法以及显示装置
CN102473792A (zh) * 2009-08-19 2012-05-23 夏普株式会社 光传感器、半导体器件和液晶面板
CN105633095A (zh) * 2016-01-04 2016-06-01 京东方科技集团股份有限公司 一种阵列基板及显示面板

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US6936895B2 (en) * 2003-10-09 2005-08-30 Chartered Semiconductor Manufacturing Ltd. ESD protection device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102197485A (zh) * 2008-10-23 2011-09-21 夏普株式会社 半导体装置及其制造方法以及显示装置
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CN102097488A (zh) * 2009-11-20 2011-06-15 株式会社半导体能源研究所 半导体装置和显示装置
CN105633095A (zh) * 2016-01-04 2016-06-01 京东方科技集团股份有限公司 一种阵列基板及显示面板

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