CN107748805A - A kind of one-wire interface technology for ICD - Google Patents
A kind of one-wire interface technology for ICD Download PDFInfo
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- CN107748805A CN107748805A CN201710797447.XA CN201710797447A CN107748805A CN 107748805 A CN107748805 A CN 107748805A CN 201710797447 A CN201710797447 A CN 201710797447A CN 107748805 A CN107748805 A CN 107748805A
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- G—PHYSICS
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
Abstract
The invention discloses a kind of one-wire interface technology for ICD, the technology is realized by hardware components and flexible glue part, hardware components are realized by microprocessor, microprocessor has CS SWD interfaces, after microprocessor carries out signal codec by Digital Logic, then serioparallel exchange is carried out, obtain parallel control bus, after finally merging with microprocessor bus, pass through CS SWD Interface Controllers MCU On-Chip peripheral.Software section then carries out signal codec by bottom most software function, then passes to upper strata using the byte information after conversion as function parameter, and is delivered to PC ends eventually through usb protocol.
Description
Technical field
The invention belongs to technical field of integrated circuits, more particularly to a kind of interfacing of sheet sand covered.
Background technology
It is real as embedded system among MCU kernels based on sheet sand covered module (In-Circuit Debug, ICD)
When artificial debugging core technology.And the most important technology modules of ICD technologies, exactly debug port communication technology.
MCU debugging technique at present, mainly there is two big technology of ICE (In-Circuit Emulation) and ICD.Compare
ICE technologies, it is sheet sand covered the characteristics of ICD technology maximums, i.e., single-step debug, real-time is directly carried out on real MCU
Height, the result of commissioning test are substantially identical with final operation result.External microcontroller manufacturer, the MSP430 such as TI is serial,
ARM Cortex series etc., there is the debugging patented technology of oneself.General debugging technique and processor cores are integral, are
The important branch of field of microprocessors.Processor, debugger (emulator) and compiler are three big keys of embedded system
Property technology.In 8 MCU fields, the domestic processor cores due to never having independent development, patented technology is debugged accordingly
It is and very deficient.
As patent application 201410728172.0 disclose it is a kind of applied to avionics field towards ICD
ARINC429 bus signals emulation testing components.The present invention defines one group of baseband signal class libraries for meeting ARINC429 standards, structure
The master pattern of ARINC429 bus signals is built, after user's typing ICD information, generation emulation signal configuration file, is used
The file of XML format preserves ARINC429 bus signals profile datas；ARINC429 buses read signal configuration file
Configuration information, corresponding ARINC429 signals control is loaded, at ARINC429 bus signals simulation datas interface, arrange parameter
Engineering value, by parameter engineering value Automatic solution it is ARINC429 source code values according to the configuration information of signal configuration file, by number
ARINC429 Labcard driver layer interfaces, driving instrument output emulation signal are sent to according to packing.However, the patent application is still
Traditional bus marco pattern is needed, although can ensure the transmission rate of data, occupancy resource is more, and efficiency is low.
The content of the invention
Based on this, therefore the present invention primary mesh be to provide a kind of one-wire interface technology for ICD, the technology is only
Needing an order wire to realize the encoding and decoding of debugging control information, in the case where can guarantee that message transmission rate, greatly subtracting
The occupancy of pin resource is lacked.
It is to provide a kind of one-wire interface technology for ICD, the technology is using self-defined another mesh of the present invention
Master slave mode single-wire-protocol, slave is realized by hardware logic at chip processor end, and in debugging probe device CS-
Main frame is realized in Link, and realizes simplicity, cost is cheap.
To achieve the above object, the technical scheme is that：
(abbreviation CS-SWD, English are meant that Chipsea Single Wire to a kind of one-wire interface technology for ICD
Debug), it is characterised in that the technology realizes that hardware components are realized by microprocessor by hardware components and flexible glue part,
After there is microprocessor (MCU) CS-SWD interfaces, microprocessor to carry out signal codec by Digital Logic, then gone here and there simultaneously
Conversion, obtains parallel control bus, after finally merging with microprocessor bus, by outer on CS-SWD Interface Controllers MCU piece
If.Therefore, can be from by CS-SWD interfaces, the IDE at PC ends can be to obtain any letter inside MCU in real time
Breath.Software section then carries out signal codec by bottom most software function, then joins the byte information after conversion as function
Number passes to upper strata, and is delivered to PC ends eventually through usb protocol.
The present invention uses a kind of single-wire communication protocol.General MCU pin resource is all more nervous, and debugging pin is general
It is multiplexed normal pins.Debugging mouth is more, it is meant that in debugging process, more normal pins can not use user.Therefore,
This patent proposes single-wire communication protocol, reduces multiplexing to greatest extent.
Further, the CS-SWD interfaces defer to CS-SWD agreements, and CS-SWD agreements are always divided into three layers：Symbol layer, lead to
Believe layer, layer order, wherein：
Symbol layer：Define the basic format of symbol；
Communication layers：Define the underlying transport form once to communicate；
Layer order：Define the complete transmission form under different command field.
Further, the symbol is used as communication symbol using NRZ.NRZ is the conventional code in single line communication
First form, by the different pulse signal of dutycycle, 0 and 1 are represented respectively.
Further, CS-SWD symbol formats include the symbol of emitter and the symbol of receiver, wherein：
The symbol width of emitter is 22Ts, in the waveform that symbol is 1,0 level of 2 Ts clock pulses, and then 20
1 level of individual clock cycle；In the waveform that symbol is 0, the 1 of 0 level, then 2 clock cycle of 20 Ts clock pulses
Level；
After receiver receives symbol, it will be decoded：
1：Detect and be less than or equal to 8 continuous low levels；
0：Detect and be more than or equal to 9 continuous low levels.
Further, CS-SWD communication formats include a basic CS-SWD transmission, comprising command frame command phase and data segment,
Among order end and data, also comprising answer code and wait (Turn Round, TNR) is turned to.
Further, the form of the command frame command phase and data segment is as follows：
Command forms：
Head：0
Order：b2-b0
Even-odd check：Pb,
ack:ACK=1, NACK=0；
Data forms：
Head：0
Order：b7-b0
Even-odd check：Pb,
ack:ACK=1, NACK=0；
Adjustable length TNR regions for some time behind each pb and ack, in the area segments, CS-SWD is total
Line is released.
In actual applications, CS-Link debugging probe can not possibly connect more MCU simultaneously and be debugged, therefore point-to-point
Communication be enough, it is secondly easy in order to ensure to realize, take master slave mode.
Further, for Host Write, primary module is after pb is distributed, and into TNR, waits the ack positions of slave module,
And slave module during this period of time perform write etc. it is to be operated, after the completion of send ack positions；If performing Host Read next time,
Then the TNR behind ack still needs wait to run through, and otherwise slave module is ready immediately after 1 position time.
For Host Read, slave module, into TNR, discharges bus after pb is sent completely；Primary module is in this period
It is interior to complete to receive and verify evaluation work, and ack is sent to slave module；If continue to read next time, the TNR after ack needs
Wait is run through, and otherwise both sides terminate to communicate.
The communication period the problem of, primary module can be logical to reset by sending the low level of 128 HSI clock cycle
Letter, if slave module detects that SWIM pins drag down more than 64 HIS clock cycle, will reset state machine.
Further, the primary module enters line function point when CS-SWD softwares are realized according to the layering of CS-SWD agreements
Layer.Wherein
1)send_nz：Send NRZ meta-function；
2)recv_nz：Receive NRZ meta-function；
3)__nop()：System idle instruction function, realize that symbol adjusts by the function；
4)bwrite：Byte sends function, performs the function and realizes and a byte transmission；
5)bread：Byte receiver function, perform the function and realize that a byte receives；
6)swrite：Write order function, perform the function and realize a write order transmission；
7)sread：Read command function, perform the function and realize that a read command is transmitted；
8)srst：Reset command function, perform the function and realize a reset command transmission.
Send_nz functions are judged symbol value using symbol value as input parameter in function body；If 1,
Then increase multiple _ _ nop () delays after output 0, then increase multiple _ _ nop () delays after exporting 1.
Recv_nz functions wait symbol trailing edge moment point always using symbol value as output parameter in function body；
If trailing edge produces, 0 level is counted, the symbol value for judging to receive according to count value.
CS-SWD slave modules realize that it mainly includes circuits below module using Digital Logic：
2) sample counter：After receiving new symbol every time, input symbols information SWI will be sampled；
2) symbol pulses：After each symbol terminates, a symbol pulses ps will be produced；
3) state machine：Which symbol instruction current transmission is in；
4) symbol decoder：Input symbols are decoded, obtain the value of symbol；
5) communications reset：Symbol is monitored, when meeting communications reset condition, resetted immediately；
6) shift register：Symbol is shifted, obtains communication word segment value；
7) parity calculations：Real-time parity calculations are carried out to symbol；
8) NHL registers：Represent N in command format H L register；
9) byte counter：To directly counting for transmission；
10) command state machine：Which field instruction current transmission is in；
11) DB buses produce：Generate parallel DB buses；
12) SRST is produced：SRST orders are parsed, generate SRST reset signals.
The one-wire interface technology for ICD that the present invention is realized, there are succinct Interface design, stable communication protocols
View design and supporting software and hardware realize demonstration, it is transported extensively in Chipsea CSR8 series kernels
With.Actual measurement traffic rate can reach 700Kbps so that IDE can quickly obtain Debugging message.
Brief description of the drawings
Fig. 1 is the CS-SWD system architecture diagrams that the present invention is implemented.
Fig. 2 is the CS-SWD symbol layer format charts that the present invention is implemented.
Fig. 3 is the CS-SWD communication format figures that the present invention is implemented.
Fig. 4 is the CS-SWD slave circuit structure diagrams that the present invention is implemented.
Fig. 5 is the circuit diagram of institute's implementation coding circuit of the present invention.
Fig. 6 is the circuit diagram of institute's implementation decoding circuit of the present invention.
Fig. 7 is that the present invention implements CS-SWD driving interface schematic diagrames.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, below in conjunction with drawings and Examples,
The present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only explaining this hair
It is bright, it is not intended to limit the present invention.
Shown in Figure 1, (abbreviation CS-SWD, English contain the one-wire interface technology for ICD realized for the present invention
Justice is Chipsea Single Wire Debug), the technology includes hardware components and software section, and wherein hardware components pass through
MCU is realized, includes ICD controllers and hardware transceiver in MCU, MCU has CS-SWD interfaces, and microprocessor passes through numeral
After logic carries out signal codec, then serioparallel exchange is carried out, obtain parallel control bus, finally merge with microprocessor bus
Afterwards, CS-SWD Interface Controllers MCU On-Chip peripheral is passed through.Therefore, can be from passing through CS-SWD interfaces, the Integrated Development at PC ends
Environment can be to obtain any information inside MCU in real time.Software section then has a software transceiver, compatible USB agreements and
ICD agreements, signal codec is carried out to bottom function by software transceiver, then using the byte information after conversion as function
Parameter passes to upper strata, and is delivered to PC ends eventually through usb protocol.
The present invention uses a kind of single-wire communication protocol.General MCU pin resource is all more nervous, and debugging pin is general
It is multiplexed normal pins.Debugging mouth is more, it is meant that in debugging process, more normal pins can not use user.Therefore,
This patent proposes single-wire communication protocol, reduces multiplexing to greatest extent.
CS-SWD symbol formats are as shown in Fig. 2 wherein：
The symbol format of emitter is：
1 level of 0 level of 2 Ts clock pulses, then 20 clock cycle.
1 level of 0 level of 20 Ts clock pulses, then 2 clock cycle.
After receiver receives symbol, it will be decoded：
1：Detect and be less than or equal to 8 continuous low levels.
0：Detect and be more than or equal to 9 continuous low levels.
CS-SWD communication formats include command frame command phase and data segment as shown in figure 3, a basic CS-SWD transmission.Ordering
Make among end and data, also comprising answer code and turn to wait (Turn Round, TNR).
Command forms：
Head：0
Order：b2-b0
Even-odd check：pb.
ack:ACK=1, NACK=0；
Data forms：
Head：0
Order：b7-b0
Even-odd check：pb.
ack:ACK=1, NACK=0；
Adjustable length TNR regions for some time behind each pb and ack.In the area segments, CS-SWD is total
Line is released.
For Host Write, main frame is after pb is distributed, and into TNR, waits the ack positions of slave.And slave is at this section
Interior execution write etc. it is to be operated, after the completion of send ack positions.If the TNR behind execution Host Read, ack is still next time
Wait is needed to run through, otherwise slave is ready immediately after 1 position time.
For Host Read, slave, into TNR, discharges bus after pb is sent completely.Main frame is during this period of time complete
Into reception and verification evaluation work, and ack is sent to slave.If continue to read next time, TNR needs after ack etc. continue
Complete, otherwise both sides terminate to communicate.
The communication period the problem of, main frame can pass through the low level reflex bit walk for sending 128 HSI clock cycle.
If slave detects that SWIM pins drag down more than 64 HIS clock cycle, state machine will be resetted.
CS-SWD slave modules are realized using Digital Logic.As shown in figure 4, it mainly includes circuits below module：
1) sample counter：After receiving new symbol every time, input symbols information SWI will be sampled.Sampling week
Phase is Ts.Which sampled point instruction current symbol is in.
2) symbol pulses：After each symbol terminates, a symbol pulses ps will be produced.
3) state machine：Which symbol instruction current transmission is in.
4) symbol decoder：Input symbols are decoded, obtain the value of symbol.
5) communications reset：Symbol is monitored, when meeting communications reset condition, resetted immediately.
6) shift register：Symbol is shifted, obtains communication word segment value.
7) parity calculations：Real-time parity calculations are carried out to symbol.
8) NHL registers：Represent N in command format H L register.
9) byte counter：To directly counting for transmission.
10) command state machine：Which field instruction current transmission is in.
11) DB buses produce：Generate parallel DB buses.
12) SRST is produced：SRST orders are parsed, generate SRST reset signals.
Symbolic encoder：Symbol is encoded.
Fig. 5 show the circuit diagram for coding circuit.
1) when needing to export TNR states, the direct control register outputs 1 of swo_set.
2) when needing output symbol, symbol counter can count to symbol sample clock.When counting wants 2, root
Judge whether output 1 according to symbol value swo_bit.
3) it is fixed output 1 when cell count overflows.
Fig. 6 show the circuit diagram for decoding circuit.
1) when sample counter is equal to 8, the set signal sample_thi_flag_set for judging that symbol is 1 is produced.
2) after symbol terminates, swi_r symbol values are exported.
As shown in fig. 7, CS-SWD primary modules：CS-SWD carries out letter when software is realized, according to the layering of CS-SWD agreements
Number layering.
1)send_nz：Send NRZ meta-function.
2)recv_nz：Receive NRZ meta-function.
3)__nop()：System idle instruction function.Realize that symbol adjusts by the function.
4)bwrite：Byte sends function, performs the function and realizes and a byte transmission.
5)bread：Byte receiver function, perform the function and realize that a byte receives.
6)swrite：Write order function, perform the function and realize a write order transmission.
7)sread：Read command function, perform the function and realize that a read command is transmitted.
8)srst：Reset command function, perform the function and realize a reset command transmission.
Send_nz functions are judged symbol value using symbol value as input parameter in function body.If 1,
Then increase multiple _ _ nop () delays after output 0, then increase multiple _ _ nop () delays after exporting 1.
Recv_nz functions wait symbol trailing edge moment point always using symbol value as output parameter in function body.
If trailing edge produces, 0 level is counted.The symbol value for judging to receive according to count value.
The one-wire interface technology for ICD that the present invention is realized, there are succinct Interface design, stable communication protocols
View design and supporting software and hardware realize demonstration, it is transported extensively in Chipsea CSR8 series kernels
With.Actual measurement traffic rate can reachBps so that IDE can quickly obtain Debugging message.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement made within refreshing and principle etc., should be included in the scope of the protection.
Claims (10)
1. a kind of one-wire interface technology for ICD, it is characterised in that the technology realized by hardware components and flexible glue part, firmly
Part part realizes that microprocessor has CS-SWD interfaces by microprocessor, and microprocessor carries out signal volume by Digital Logic
After decoding, then serioparallel exchange is carried out, obtain parallel control bus, after finally merging with microprocessor bus, connect by CS-SWD
Mouth control MCU On-Chip peripheral；Software section then carries out signal codec by bottom most software function, then by the byte after conversion
Information passes to upper strata as function parameter, and is delivered to PC ends eventually through usb protocol.
2. it is used for ICD one-wire interface technology as claimed in claim 1, it is characterised in that the CS-SWD interfaces defer to CS-
SWD agreements, CS-SWD agreements are always divided into three layers：Symbol layer, communication layers, layer order, wherein：
Symbol layer：Define the basic format of symbol；
Communication layers：Define the underlying transport form once to communicate；
Layer order：Define the complete transmission form under different command field.
3. it is used for ICD one-wire interface technology as claimed in claim 2, it is characterised in that the symbol is made using NRZ
For the symbol that communicates.NRZ is the conventional symbol format in single line communication, by the different pulse signal of dutycycle, generation respectively
Table 0 and 1.
4. it is used for ICD one-wire interface technology as claimed in claim 3, it is characterised in that CS-SWD symbol formats include transmitting
The symbol of machine and the symbol of receiver, wherein：
The symbol width of emitter is 22Ts, symbol be 1 waveform in, 0 level of 2 Ts clock pulses, then 20 when
1 level in clock cycle；In the waveform that symbol is 0,1 level of 0 level of 20 Ts clock pulses, then 2 clock cycle；
After receiver receives symbol, it will be decoded：
1：Detect and be less than or equal to 8 continuous low levels；
0：Detect and be more than or equal to 9 continuous low levels.
5. it is used for ICD one-wire interface technology as claimed in claim 4, it is characterised in that CS-SWD communication formats include one
Basic CS-SWD transmission, comprising command frame command phase and data segment, among order end and data, also comprising answer code and turn to wait
(Turn Round, TNR).
6. it is used for ICD one-wire interface technology as claimed in claim 5, it is characterised in that the lattice of the command frame command phase and data segment
Formula is as follows：
Command forms：
Head：0
Order：b2-b0
Even-odd check：Pb,
ack:ACK=1, NACK=0；
Data forms：
Head：0
Order：b7-b0
Even-odd check：Pb,
ack:ACK=1, NACK=0；
Adjustable length TNR regions for some time behind each pb and ack, in the area segments, CS-SWD bus quilts
Release.
7. it is used for ICD one-wire interface technology as claimed in claim 6, it is characterised in that CS-Link debugging probes take master
Slave pattern.
8. it is used for ICD one-wire interface technology as claimed in claim 1, it is characterised in that for Host Write, primary module
After pb is distributed, into TNR, the ack positions of slave module are waited, and slave module during this period of time performs and writes etc. to be operated, completes
Ack positions are sent afterwards；Still wait is needed to run through if performing the TNR behind Host Read, ack next time, otherwise from mould
Block is ready immediately after 1 position time；
For Host Read, slave module, into TNR, discharges bus after pb is sent completely；Primary module is during this period of time complete
Into reception and verification evaluation work, and ack is sent to slave module；If continue to read next time, the TNR after ack needs to wait
Run through, otherwise both sides terminate to communicate.
9. it is used for ICD one-wire interface technology as claimed in claim 8, it is characterised in that the primary module is in CS-SWD softwares
When realizing, line function layering is entered according to the layering of CS-SWD agreements, wherein
1)send_nz：Send NRZ meta-function；
2)recv_nz：Receive NRZ meta-function；
3)__nop()：System idle instruction function, realize that symbol adjusts by the function；
4)bwrite：Byte sends function, performs the function and realizes and a byte transmission；
5)bread：Byte receiver function, perform the function and realize that a byte receives；
6)swrite：Write order function, perform the function and realize a write order transmission；
7)sread：Read command function, perform the function and realize that a read command is transmitted；
8)srst：Reset command function, perform the function and realize a reset command transmission.
10. it is used for ICD one-wire interface technology as claimed in claim 9, it is characterised in that CS-SWD slave modules use numeral
Logic realization, it mainly includes circuits below module：
1) sample counter：After receiving new symbol every time, input symbols information SWI will be sampled；
2) symbol pulses：After each symbol terminates, a symbol pulses ps will be produced；
3) state machine：Which symbol instruction current transmission is in；
4) symbol decoder：Input symbols are decoded, obtain the value of symbol；
5) communications reset：Symbol is monitored, when meeting communications reset condition, resetted immediately；
6) shift register：Symbol is shifted, obtains communication word segment value；
7) parity calculations：Real-time parity calculations are carried out to symbol；
8) NHL registers：Represent N in command format H L register；
9) byte counter：To directly counting for transmission；
10) command state machine：Which field instruction current transmission is in；
11) DB buses produce：Generate parallel DB buses；
12) SRST is produced：SRST orders are parsed, generate SRST reset signals.
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