CN106598194A - Communication method of single line bus system - Google Patents
Communication method of single line bus system Download PDFInfo
- Publication number
- CN106598194A CN106598194A CN201510672277.3A CN201510672277A CN106598194A CN 106598194 A CN106598194 A CN 106598194A CN 201510672277 A CN201510672277 A CN 201510672277A CN 106598194 A CN106598194 A CN 106598194A
- Authority
- CN
- China
- Prior art keywords
- bus system
- wire bus
- communication means
- data
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Small-Scale Networks (AREA)
Abstract
The present invention belongs to the field of buses, and discloses a communication method of a single line bus system. The single line bus system comprises at least one master device and at least one slave device. The master device and the slave device communicate with each other by using a single line bus. A slave device determines whether the single line bus is at a first level with lasting time greater than or equal to a preset duration, if yes, the slave device determines whether the master device sends a startup signal, if yes, a clock of the single line bus system is switched to a high frequency clock from a low frequency clock. Through adoption of the communication method of the single line bus system, the low frequency clock is adopted in a waiting phase of communication of the single line bus system, so that less electricity is wasted.
Description
Technical field
The present invention relates to bus field, more particularly to a kind of communication means of single-wire bus system.
Background technology
Traditional communications bus is all made up of multi-thread, and such as I2C, C2, USB, UART respectively has two
Line, is more made up of tetra- lines of SPI, I2S, and on processor of single chip computer, every line all has to occupancy one
Individual I/O port, multi-thread communication make the area of chip just become big, cause the great wasting of resources, so that chip
Cost increase.
In order to solve the multi-thread waste for causing, usually using the communication mode of single line, communication interface reaches people
Most save, saved general purpose data port resource.
The defect of prior art is：On existing single-wire bus system after electricity, in single-wire bus system communication
Loitering phase adopts high frequency clock, causes the waste of power consumption.
The content of the invention
The invention provides a kind of communication means of single-wire bus system, it is intended to solve existing design in list
The loitering phase of line bus system communication causes the technical problem of the waste of power consumption using high frequency clock.
The present invention is achieved in that a kind of communication means of single-wire bus system, wherein single-wire bus system
Including at least one main device and at least one from device, the main device and it is described from device by single line it is total
Line is communicated, it is characterised in that the communication means of the single-wire bus system includes：
A. it is described to judge whether the single bus are more than or equal to preset duration in the persistent period from equipment
The first level, if so, then execution step B；
B. it is described to judge whether the main device sends open signal from equipment, if so, then execution step C；
C. the clock of the single-wire bus system is switched to into high frequency clock by low-frequency clock.
The beneficial effect brought of technical scheme that the present invention is provided is：
Knowable to the invention described above, as wherein single-wire bus system includes at least one main device and at least one
It is individual to be communicated by single bus from device, main device and from device；Whether single bus are judged from equipment
Be the first level more than or equal to preset duration in the persistent period, if so, then main device is judged from equipment
Whether open signal is sent, when the clock of single-wire bus system being switched to high frequency by low-frequency clock then if so,
Clock；It is thereby achieved that the loitering phase in single-wire bus system communication adopts low-frequency clock, power consumption is reduced
The waste of amount.
Description of the drawings
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, below will be to institute in embodiment description
The accompanying drawing that needs are used is briefly described, it should be apparent that, drawings in the following description are only the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work,
Can be with according to these other accompanying drawings of accompanying drawings acquisition.
Fig. 1 is a kind of flow chart of the communication means of single-wire bus system provided in an embodiment of the present invention；
Fig. 2 is open signal sequential chart；
Fig. 3 is that single-wire bus system opens sequential chart；
1 high level and 1 low level pulse sequence diagram when Fig. 4 is high frequency clock；
1 high level and 1 low level pulse sequence diagram when Fig. 5 is low-frequency clock；
Fig. 6 is another kind of flow chart of the communication means of single-wire bus system provided in an embodiment of the present invention；
Fig. 7 is read data frame structure chart；
Fig. 8 is write data frame structure chart.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to the present invention
Embodiment is described in further detail.
The embodiment of the present invention provides the flow process of the communication means of single-wire bus system, referring to Fig. 1, single bus system
The communication means of system includes：
101：Judge whether single bus are more than or equal to the first of preset duration in the persistent period from equipment
Level, if so, then execution step 102.
102：Judge whether main device sends open signal from equipment, if so, then execution step 103.
In being embodied as, open signal sequential can include pulse and 4 frequencies of 4 frequencies for 0.5kHz
For the pulse of 1kHz, as shown in Figure 2.
103：The clock of single-wire bus system is switched to into high frequency clock by low-frequency clock.
For example, when the first level is low level, the unlatching sequential chart of single-wire bus system as shown in figure 3,
At stage (1), the low level of the level of single bus, at stage (2), the level of single bus
For open signal, at the end of the stage (2), the clock of single-wire bus system is switched to by low-frequency clock
High frequency clock.
In all steps of Fig. 1, single-wire bus system is by judging high level pulse and low level pulse
Continuous number is to determine data as high level or low level.
Wherein, when the clock of single-wire bus system is high frequency clock, single-wire bus system is by judging high electricity
The continuous number of flat pulse and low level pulse is to determine data as high level or low level is specially：
When continuously there is 2 low level pulses and 8 high level pulses, then data are judged as 1 high electricity
It is flat.
When continuously there is 8 pulses lows and 2 pulse high levels, then data are judged as 1 low electricity
It is flat.
Now, 1 high level and 1 low level pulse train are as shown in Figure 4.
Wherein, when the clock of single-wire bus system is low-frequency clock, single-wire bus system is by judging high electricity
The continuous number of flat pulse and low level pulse is to determine data as high level or low level is specially：
When continuously there is 2 low level pulses and 20 high level pulses, then data are judged as 1 high electricity
It is flat；
When continuously there is 20 pulses lows and 2 pulse high levels, then data are judged as 1 low electricity
It is flat.
Now, 1 high level and 1 low level pulse train are as shown in Figure 5.
Alternatively, as shown in fig. 6, also including step 104-1 to 107-1 after step 103：
104-1：Judge whether main device sends reading control word from equipment, if so, execution step 105-1, if
It is no, execution step 106-1；
105-1：Single-wire bus system enters read operation pattern, sends read data frame to main device from device.
In being embodied as, as shown in fig. 7, read data frame can include reading bytes field, read address field
With reading data field.Wherein, the content of reading bytes field is the byte number for needing to read, and reads address field
Content is the address read, and the content for reading data field is the data come of reading back.
106-1：Judge whether main device sends from equipment and write control word, if so, execution step 107-1.
107-1：Single-wire bus system enters write operation pattern, and main device sends write data frame to from device.
In being embodied as, as shown in figure 8, write data frame can include write verse number field, write address field
With write data field.Wherein, the content of write verse number field is the byte number for needing to write, write address field
Content is the address write, and the content for writing data field is the data for needing write.
Alternatively, as shown in fig. 6, step 104-2 to 105-2 can also be included after step 103：
104-2：Judge whether main device sends reset control word from equipment, if so, execution step 105-2；
105-2：Single-wire bus system enters reset mode, and single bus are used as general-purpose data line.
Alternatively, as shown in fig. 6, step 100 can also be included before step 101：
100：Judge whether depositor is preset value from equipment, if so, execution step 101.
To sum up, the embodiment of the present invention includes at least one main device and at least one by wherein single-wire bus system
It is individual to be communicated by single bus from device, main device and from device；Whether single bus are judged from equipment
Be the first level more than or equal to preset duration in the persistent period, if so, then main device is judged from equipment
Whether open signal is sent, when the clock of single-wire bus system being switched to high frequency by low-frequency clock then if so,
Clock；It is thereby achieved that the loitering phase in single-wire bus system communication adopts low-frequency clock, power consumption is reduced
The waste of amount.
The embodiments of the present invention are for illustration only, do not represent the quality of embodiment.
One of ordinary skill in the art will appreciate that realizing that all or part of step of above-described embodiment can pass through
Hardware is completing, it is also possible to instruct the hardware of correlation to complete by program, described program can be stored in
In a kind of computer-readable recording medium, storage medium mentioned above can be read only memory, disk or
CD etc..
Presently preferred embodiments of the present invention is the foregoing is only, it is not to limit the present invention, all the present invention's
Within spirit and principle, any modification, equivalent substitution and improvements made etc. should be included in the present invention's
Within protection domain.
Claims (10)
1. a kind of communication means of single-wire bus system, wherein single-wire bus system include at least one main device
With at least one from device, the main device and it is described communicated from device by single bus, its feature
It is that the communication means of the single-wire bus system includes：
A. it is described to judge whether the single bus are more than or equal to preset duration in the persistent period from equipment
The first level, if so, then execution step B；
B. it is described to judge whether the main device sends open signal from equipment, if so, then execution step C；
C. the clock of the single-wire bus system is switched to into high frequency clock by low-frequency clock.
2. the communication means of single-wire bus system as claimed in claim 1, it is characterised in that the unlatching
Signal sequence includes the pulse of the pulse that 4 frequencies are 0.5kHz and 4 frequencies for 1kHz.
3. the communication means of single-wire bus system as claimed in claim 1, it is characterised in that the single line
Bus system by judging the continuous number of high level pulse and low level pulse determining data as high level or
Low level.
4. the communication means of single-wire bus system as claimed in claim 3, it is characterised in that when the list
When the clock of line bus system is high frequency clock, the single-wire bus system is by judging high level pulse and low
The continuous number of level pulse is to determine data as high level or low level is specially：
When continuously there is 2 low level pulses and 8 high level pulses, then data are judged as 1 high electricity
It is flat；
When continuously there is 8 pulses lows and 2 pulse high levels, then data are judged as 1 low electricity
It is flat.
5. the communication means of single-wire bus system as claimed in claim 3, it is characterised in that when the list
When the clock of line bus system is low-frequency clock, the single-wire bus system is by judging high level pulse and low
The continuous number of level pulse is to determine data as high level or low level is specially：
When continuously there is 2 low level pulses and 20 high level pulses, then data are judged as 1 high electricity
It is flat；
When continuously there is 20 pulses lows and 2 pulse high levels, then data are judged as 1 low electricity
It is flat.
6. the communication means of single-wire bus system as claimed in claim 1, it is characterised in that step C
It is further comprising the steps of afterwards：
D. it is described to judge whether the main device sends reading control word from equipment, if so, execution step E, if it is not,
Execution step F；
E. the single-wire bus system enters read operation pattern, described to send read data frame to the master from device
Device；
F. it is described to judge whether the main device sends from equipment and write control word, if so, execution step G；
G. the single-wire bus system enters write operation pattern, the main device send write data frame to it is described from
Device.
7. the communication means of single-wire bus system as claimed in claim 6, it is characterised in that the reading
Include reading bytes field, read address field and read data field according to frame.
8. the communication means of single-wire bus system as claimed in claim 6, it is characterised in that described to write number
Include write verse number field, write address field according to frame and write data field.
9. the communication means of single-wire bus system as claimed in claim 1, it is characterised in that step A
It is before further comprising the steps of：
H. it is described to judge whether depositor is preset value from equipment, if so, execution step A.
10. the communication means of single-wire bus system as claimed in claim 1, it is characterised in that the step
It is further comprising the steps of after C：
I. it is described to judge whether the main device sends reset control word from equipment, if so, execution step J；
J. the single-wire bus system enters reset mode, and the single bus are used as general-purpose data line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510672277.3A CN106598194A (en) | 2015-10-15 | 2015-10-15 | Communication method of single line bus system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510672277.3A CN106598194A (en) | 2015-10-15 | 2015-10-15 | Communication method of single line bus system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106598194A true CN106598194A (en) | 2017-04-26 |
Family
ID=58555353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510672277.3A Pending CN106598194A (en) | 2015-10-15 | 2015-10-15 | Communication method of single line bus system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106598194A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107220198A (en) * | 2017-06-22 | 2017-09-29 | 深圳天珑无线科技有限公司 | Communication terminal and mongline two-way communication system |
| CN107402897A (en) * | 2017-07-04 | 2017-11-28 | 厦门芯阳科技股份有限公司 | A kind of method of two single-chip I/O mouth single line communications |
| CN107748805A (en) * | 2017-09-06 | 2018-03-02 | 芯海科技（深圳）股份有限公司 | A kind of one-wire interface technology for ICD |
| CN111486918A (en) * | 2020-06-15 | 2020-08-04 | 泉州慧霁科技有限公司 | Water consumption number acquisition method of intelligent electronic induction water meter |
| CN115657567A (en) * | 2022-11-14 | 2023-01-31 | 上海海栎创科技股份有限公司 | Method and control system for transmitting control signal by single pin |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6333939B1 (en) * | 1998-08-14 | 2001-12-25 | Qualcomm Incorporated | Synchronization of a low power oscillator with a reference oscillator in a wireless communication device utilizing slotted paging |
| CN1639672A (en) * | 2002-03-28 | 2005-07-13 | 高级模拟技术有限公司 | Single wire serial interface |
| CN102591834A (en) * | 2010-12-02 | 2012-07-18 | 捷讯研究有限公司 | Single wire bus system |
| CN103389956A (en) * | 2012-05-09 | 2013-11-13 | 国际商业机器公司 | Method and circuit used for dynamically optimizing bus frequency of inter-integrated circuit bus |
| CN104184796A (en) * | 2014-07-22 | 2014-12-03 | 惠州市德赛西威汽车电子有限公司 | Signal isolation method and device based on LIN bus |
-
2015
- 2015-10-15 CN CN201510672277.3A patent/CN106598194A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6333939B1 (en) * | 1998-08-14 | 2001-12-25 | Qualcomm Incorporated | Synchronization of a low power oscillator with a reference oscillator in a wireless communication device utilizing slotted paging |
| CN1639672A (en) * | 2002-03-28 | 2005-07-13 | 高级模拟技术有限公司 | Single wire serial interface |
| CN102591834A (en) * | 2010-12-02 | 2012-07-18 | 捷讯研究有限公司 | Single wire bus system |
| CN103389956A (en) * | 2012-05-09 | 2013-11-13 | 国际商业机器公司 | Method and circuit used for dynamically optimizing bus frequency of inter-integrated circuit bus |
| CN104184796A (en) * | 2014-07-22 | 2014-12-03 | 惠州市德赛西威汽车电子有限公司 | Signal isolation method and device based on LIN bus |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107220198A (en) * | 2017-06-22 | 2017-09-29 | 深圳天珑无线科技有限公司 | Communication terminal and mongline two-way communication system |
| CN107402897A (en) * | 2017-07-04 | 2017-11-28 | 厦门芯阳科技股份有限公司 | A kind of method of two single-chip I/O mouth single line communications |
| CN107748805A (en) * | 2017-09-06 | 2018-03-02 | 芯海科技（深圳）股份有限公司 | A kind of one-wire interface technology for ICD |
| CN107748805B (en) * | 2017-09-06 | 2022-05-06 | 合肥市芯海电子科技有限公司 | Single-wire interface method for on-chip debugging |
| CN111486918A (en) * | 2020-06-15 | 2020-08-04 | 泉州慧霁科技有限公司 | Water consumption number acquisition method of intelligent electronic induction water meter |
| CN115657567A (en) * | 2022-11-14 | 2023-01-31 | 上海海栎创科技股份有限公司 | Method and control system for transmitting control signal by single pin |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI420293B (en) | Method, system, and apparatus for coordinated link power management | |
| CN106598194A (en) | Communication method of single line bus system | |
| CN104579885B (en) | The protocol converter of cpci bus and isa bus and conversion method | |
| CN107957885B (en) | PCIE link equipment standby and recovery method based on Feiteng platform | |
| CN103678178B (en) | A kind of power down process method and system of storage system | |
| CN103077132B (en) | A kind of cache handles method and protocol processor high-speed cache control module | |
| CN111124975A (en) | PCIe device dynamic power consumption saving method and low-power consumption PCIe device | |
| CN104345869A (en) | SDIO device, system and method for controlling same | |
| CN109324991A (en) | A kind of hot plug device of PCIE device, method, medium and system | |
| US20180088652A1 (en) | Platform communication protocol | |
| KR20070056724A (en) | Controller for controlling output of clock signal and system having the same | |
| CN102117193B (en) | Method for implementing pre-read FIFO and pre-read FIFO | |
| US7353300B2 (en) | Apparatus to improve the firmware efficiency for a multiframe serial interface | |
| CN102929381A (en) | Electronic system and power management system thereof | |
| CN105718396B (en) | A kind of I of big data master transmissions2C bus units and its means of communication | |
| CN103399832A (en) | Ordering method of out-of-order return data between buses | |
| TW200844756A (en) | Methods and systems for centralized link power management control (CLMC) | |
| CN116893991B (en) | Storage module conversion interface under AXI protocol and conversion method thereof | |
| CN103777894A (en) | Method and device for eliminating read-write conflict of memorizer | |
| CN110865959A (en) | Method and circuit for waking up I2C equipment | |
| CN102708079B (en) | Be applied to the method and system of the control data transmission of microcontroller | |
| CN108170470A (en) | SOC system step-by-step write devices | |
| CN102722457B (en) | Bus interface conversion method and bus bridging device | |
| CN105573947A (en) | APB (Advanced Peripheral Bus) based SD/MMC (Secure Digital/ MultiMedia Card) control method | |
| CN207424866U (en) | A kind of data communication system between kernel based on heterogeneous multi-nucleus processor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 518000 Shenzhen Nanshan District, Guangdong Province, Guangdong Province, Yuehai Street High-tech Zone Community Science and Technology South Road 18 Shenzhen Bay Science and Technology Eco-Park 12 Skirt Building 732 Applicant after: Shenzhen Bojuxing Microelectronics Technology Co., Ltd. Address before: 518000 Shenzhen City, Nanshan District Province, a new high tech park, No. 1,, new materials, building D, room four, building Applicant before: Shenzhen Bojuxing Industrial Development Co., Ltd. |
|
| CB02 | Change of applicant information | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170426 |
|
| RJ01 | Rejection of invention patent application after publication |