CN109324991A - A kind of hot plug device of PCIE device, method, medium and system - Google Patents
A kind of hot plug device of PCIE device, method, medium and system Download PDFInfo
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- CN109324991A CN109324991A CN201811109611.4A CN201811109611A CN109324991A CN 109324991 A CN109324991 A CN 109324991A CN 201811109611 A CN201811109611 A CN 201811109611A CN 109324991 A CN109324991 A CN 109324991A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4081—Live connection to bus, e.g. hot-plugging
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
The invention discloses a kind of hot plug device of PCIE device, method, medium and system, the step of this method includes: that the target memory resource of host assignment is obtained and occupied with the identity of PCIE device in BIOS start-up course；After BIOS starting, when detecting that PCIE interface accesses new PCIE device, the correspondence of host Yu new PCIE device is established, and provide target memory resource to new PCIE device；When detecting PCIE interface and existing PCIE device disconnects, existing PCIE device is initiated using target memory resource receiving host I O access.This method ensure that the overall work stability of PCIE device Yu the constituted system of host.In addition, the present invention also provides the hot plug system of a kind of hot plug device for realizing PCIE device, computer readable storage medium and PCIE device, beneficial effect is same as above.
Description
Technical field
The present invention relates to data communication field, more particularly to a kind of hot plug device of PCIE device, method, medium and
System.
Background technique
Under big data and the technical background of cloud computing, readwrite performance is increasingly prominent for the importance of data processing.
By taking solid state hard disk as an example, with the rapid development of SSD (solid state hard disk) technology, the performance of SSD constantly rises violently, and dodges in SSD bottom
The bandwidth deposited is higher and higher, and delay when accessing flash media is lower and lower, for reading and writing data performance that SSD is substantially improved
Speech, AHCI bus protocol or SATA bus protocol commonly used by interface are no longer satisfied the high-performance of current SSD, low prolong
When demand, since the channel of PCIE bus protocol has the characteristic of low delay and parallel communications, current SSD is usual
It is established using the interface based on PCIE bus protocol and is connect with host, is i.e. SSD is connect as PCIE device with host, is promoted with this
Readwrite performance of the host to data in SSD.
When the host for being connected with PCIE device carries out BIOS starting, can first be distributed in the host each with PCIE device
The corresponding memory source of a logic unit, and then host can be carried out based on pre-assigned memory source to PCIE device IO
(input/output) operation.But it is current due to that may be fully allocated to the memory source of host in BIOS start-up course
PCIE device, therefore terminate in BIOS starting, new PCIE device is inserted into when host is in running order, it may can not because of host
New memory source is distributed for the PCIE device again, and causes new PCIE device can not be in host side normal use, Jin Er
Host side generates exception information；In addition, when in the I O process, disconnected between PCIE device and host PCIE device and host it
Between connection will lead in host and be released for the memory source of PCIE device distribution, since that this can not be accessed is interior for host
Resource is deposited, therefore can not continue I O access being sent to memory source, host side is eventually led to and generates exception information.Above in master
Under machine is in running order, PCIE device and the constituted system of host are difficult to ensure for the hot plug operations of PCIE device
Overall stability.
It can be seen that the hot plug device and method of a kind of PCIE device are provided, with opposite guarantee PCIE device and host
The overall stability of constituted system is those skilled in the art's urgent problem to be solved.
Summary of the invention
The object of the present invention is to provide a kind of hot plug device of PCIE device, method, medium and systems, with opposite guarantee
The overall stability of PCIE device and the constituted system of host.
In order to solve the above technical problems, the present invention provides a kind of hot plug device of PCIE device, comprising:
Connect with host, for occupying the target memory resource of host assignment with the identity of PCIE device, and in insertion or
When extracting PCIE device, the FPGA device of target memory resource is provided to PCIE device or host；
It is connect with FPGA device, for inserting or pull out the PCIE interface of PCIE device.
In addition, the present invention also provides a kind of hot-plug method of PCIE device, applied to aforementioned disclosed PCIE device
Hot plug device, comprising:
In BIOS start-up course, FPGA device is obtained with the identity of PCIE device and occupies the target memory of host assignment
Resource；
After BIOS starting, when detecting that PCIE interface accesses new PCIE device, establishes host and set with new PCIE
Standby correspondence, and target memory resource is provided to new PCIE device；
When detecting that PCIE interface and existing PCIE device disconnect, using target memory resource receiving host to
The I O access for thering is PCIE device to initiate.
Preferably, after BIOS starts, when detecting that PCIE interface accesses new PCIE device, host and new is established
The correspondence of PCIE device, and provide target memory resource to new PCIE device and specifically include:
After BIOS starting, when detecting the signal in place of new PCIE device, host and new PCIE device are established
Correspondence；
The interrupt processing application of PCIE device is rescaned to host initiation, and establishes target memory resource and is set with new PCIE
Standby subordinate relation, to be identified by host and use new PCIE device.
Preferably, it when detecting that PCIE interface and existing PCIE device disconnect, is received using target memory resource
The I O access that host initiates existing PCIE device specifically includes:
When the signal in place for detecting existing PCIE device disconnects, it is corresponding that the existing PCIE device of change is initiated to host
The interrupt processing application of memory source, and establish the subordinate relation of target memory resource Yu existing PCIE device；
The I O access that existing PCIE device is initiated using target memory resource receiving host.
Preferably, PCIE device is specially PCIE SSD.
Preferably, PCIE SSD is specially NVME SSD.
Preferably, target memory resource specifically includes BUS resource, DEVICE resource, FUNCTION ID resource and MMIO
Space resources.
Preferably, PCIE interface is specially U.2 specification interface.
In addition, being stored with meter on computer readable storage medium the present invention also provides a kind of computer readable storage medium
Calculation machine program, when computer program is executed by processor the step of the realization such as hot-plug method of above-mentioned PCIE device.
In addition, the present invention also provides a kind of hot plug system of PCIE device, the hot plug device including PCIE device.
The hot plug device of PCIE device provided by the present invention, including what is connect with host, for PCIE device
Identity occupies the target memory resource that host is distributed, and when inserting or pull out PCIE device, mentions to PCIE device or host
It is connect for the FPGA device of target memory resource, and with FPGA device, for inserting or pull out the PCIE interface of PCIE device.
On the basis of the topological structure of the hot plug device of above-mentioned PCIE device, the hot plug side of PCIE device provided by the present invention
Method is, using FPGA device as PCIE device, to obtain in the start-up course of host B IOS and occupy the target by host assignment
Memory source, and then when the PCIE interface of FPGA device accesses new PCIE device, the target memory resource occupied in advance is mentioned
New PCIE device is supplied to use；When the PCIE interface of FPGA device and existing PCIE device disconnect, i.e., existing PCIE is set
When standby original memory source is released, is received by target memory resource and the IO that existing PCIE device is initiated is visited by host
It asks.Due to this method first pass through in advance FPGA device obtained with the identity of PCIE device and occupy host assignment target memory money
Source, therefore when there is hot plug situation during the host work, can using the target memory resource shared by FPGA device as
Standby resources ensure the normal work of host to support being normally carried out for the host work in every after hot plug, ensure that
The overall work stability of PCIE device and the constituted system of host.In addition, a kind of PCIE device of realizing of the present invention offer
The computer readable storage medium of hot plug and the hot plug system of PCIE device, beneficial effect are same as above.
Detailed description of the invention
In order to illustrate the embodiments of the present invention more clearly, attached drawing needed in the embodiment will be done simply below
It introduces, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ordinary skill people
For member, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of structure chart of the hot plug device of PCIE device provided in an embodiment of the present invention；
Fig. 2 is a kind of flow chart of the hot-plug method of PCIE device provided in an embodiment of the present invention；
Fig. 3 is the flow chart of the hot-plug method of another PCIE device provided in an embodiment of the present invention；
Fig. 4 is the flow chart of the hot-plug method of another PCIE device provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, rather than whole embodiments.Based on this
Embodiment in invention, those of ordinary skill in the art are without making creative work, obtained every other
Embodiment belongs to the scope of the present invention.
Core of the invention is to provide the hot plug device and method of a kind of PCIE device, with opposite guarantee PCIE device with
The overall stability of the constituted system of host.It is inserted in addition, another core of the invention is to provide a kind of heat for realizing PCIE device
The hot plug system of the computer readable storage medium pulled out and PCIE device.
In order to enable those skilled in the art to better understand the solution of the present invention, with reference to the accompanying drawings and detailed description
The present invention is described in further detail.
Embodiment one
Fig. 1 is a kind of structure chart of the hot plug device of PCIE device provided in an embodiment of the present invention.The embodiment of the present invention
The hot plug device 10 of the PCIE device of offer, comprising:
It connect with host 11, for occupying the target memory resource of host assignment with the identity of PCIE device, and is being inserted into
Or when extracting PCIE device, the FPGA device 12 of target memory resource is provided to PCIE device or host 11；
It is connect with FPGA device 12, for inserting or pull out the PCIE interface 13 of PCIE device.
It should be noted that the host in the present apparatus refers to that computer removes the main machine other than IO (input and output) equipment
Body portion generally includes CPU, memory, hard disk, CD-ROM drive, power supply and other input and output controller and interface.Due to FPGA
Equipment be the target memory resource of host assignment is occupied with the identity of PCIE device, therefore between host and FPGA device be with
The connection that PCIE standard carries out.Host in the present apparatus is mainly the PCIE device progress for passing through the processing logic interfacing of CPU and entering
Scanning, and then corresponding memory source is distributed to each PCIE device that scanning obtains, memory source herein is PCIE device
A series of general designation of required logical spaces when being interacted with the normal IO of host, due to having between different PCIE devices
Certain otherness is not specifically limited the logical space for specifically including in memory source herein.
In addition, the PCIE interface of connection PCIE device is provided in FPGA device, since FPGA device is with good
Scalability, therefore PCIE interface quantity is not limited only to 1, can set according to the actual situation, when PCIE device insertion or
When extracting PCIE interface, FPGA device can determine the PCIE device of the PCIE interface according to the level signal of PCIE interface
Connection.
FPGA device in the present apparatus is the connection relationship established with the identity of PCIE device and host, since FPGA is set
Standby flexible in programming with higher, is the program by being stored in RAM to control the working condition of FPGA device, Yong Huke
Corresponding program is write with the logic function according to FPGA device, therefore FPGA device can simulate the work of PCIE device and patrol
Volume, and communicated as PCIE device with host, on this basis, it also can be set and individually execute logic, be used for basis
Interactive mode between the connection control host of the PCIE device of PCIE interface and the PCIE device.
In addition, the work-based logic of FPGA device simulation PCIE device and being communicated with host with the identity of PCIE device
Specific implementation is that identical with PCIE device logic module is created in FPGA device, and matching in each logic module
Immobilized substance is written between emptying in (i.e. standard register).
The hot plug device of PCIE device provided by the present invention, including what is connect with host, for PCIE device
Identity occupies the target memory resource that host is distributed, and when inserting or pull out PCIE device, mentions to PCIE device or host
It is connect for the FPGA device of target memory resource, and with FPGA device, for inserting or pull out the PCIE interface of PCIE device.
Fig. 2 is a kind of flow chart of the hot-plug method of PCIE device provided in an embodiment of the present invention, applied to above-mentioned
The hot plug device of PCIE device.Referring to FIG. 2, the specific steps of the hot-plug method of PCIE device include:
Step S10: in BIOS start-up course, the target memory of host assignment is obtained and occupied with the identity of PCIE device
Resource.
It should be noted that BIOS (Basic Input Output System, basic input output system) is one group solid
Change the program into computer on mainboard on a rom chip, the journey of its in store most important basic input and output of computer
Self-check program and system self-triggered program after sequence, booting, major function are that the bottom, most direct hard is provided for computer
Part is set and controlled.The process of BIOS starting i.e. the initialization procedure of host, in order to ensure the PCIE being connected with host is set
It is standby normal use to need to distribute each PCIE in host during BIOS starting after host initializes and set
Standby corresponding memory source.And in this step, the purpose by the way that FPGA device to be modeled as to PCIE device is only to obtain and account for
With the target memory resource of host assignment, in addition to this, FPGA device is not carried out between host with the identity of PCIE device
I/O operation, therefore target memory resource is essentially idle memory source.
Step S11: BIOS starting after, when detect PCIE interface access new PCIE device when, establish host with
The correspondence of new PCIE device, and target memory resource is provided to new PCIE device.
It should be noted that the executing subject of this step should be FPGA device, FPGA device is by writing and storing in advance
Program in RAM executes the operation content of this step and subsequent step.After BIOS starting, i.e. the initialization of host
After process terminates and starts normal work, when detect PCIE interface access new PCIE device when, then establish new PCIE device with
Correspondence between host logically establishes the basis that IO is interacted between host and new PCIE device with this, and then will
The target memory resource that FPGA device occupies in advance is provided as memory used when carrying out IO between new PCIE device and host
Source, to prevent from not having memory source to carry out the case where reporting an error due to IO is interacted with new PCIE device because of host.
Step S12: it when detecting that PCIE interface and existing PCIE device disconnect, is received using target memory resource
The I O access that host initiates existing PCIE device.
This step is when detecting PCIE interface and existing PCIE device disconnects, i.e., existing PCIE device connects from PCIE
The operation content carried out when being extracted at mouthful, since when existing PCIE device is extracted from PCIE interface, which is set
The standby memory source in host will be released, therefore after being released in order to avoid memory source, and host is to existing PCIE device
The case where initiating I O access but can not finding the memory source of existing PCIE device generation, this step are connect using target memory resource
The I O access initiated existing PCIE device of host is received, the case where to prevent host from reporting an error.
On the basis of the topological structure of the hot plug device of above-mentioned PCIE device, PCIE device provided by the present invention
Hot-plug method, using FPGA device as PCIE device, is obtained and is occupied by host point in the start-up course of host B IOS
The target memory resource matched, and then when the PCIE interface of FPGA device accesses new PCIE device, it will be in the target that occupied in advance
It deposits resource and is supplied to new PCIE device use；When the PCIE interface of FPGA device and existing PCIE device disconnect, i.e.,
When thering is original memory source of PCIE device to be released, is received by target memory resource and existing PCIE device is initiated by host
I O access.It is obtained with the identity of PCIE device since this method first passes through FPGA device in advance and occupies the target of host assignment
Memory source, therefore when host work hot plug situation occurs in the process, the target memory shared by FPGA device can be provided
Being normally carried out for the host work in every after hot plug is supported in source as standby resources, and then ensures the normal work of host,
It ensure that the overall work stability of PCIE device Yu the constituted system of host.
Embodiment two
On the basis of the above embodiments, the present invention also provides a series of preferred embodiments.
Fig. 3 is the flow chart of the hot-plug method of another PCIE device provided in an embodiment of the present invention.Step in Fig. 3
S10 and step S12 are identical as Fig. 2, and details are not described herein.
As shown in figure 3, as a preferred embodiment, after BIOS starting, when detecting that PCIE interface connects
When entering new PCIE device, the correspondence of host Yu new PCIE device is established, and provide target memory resource to new PCIE device
It specifically includes:
Step S20: after BIOS starting, when detecting the signal in place of new PCIE device, host and new is established
The correspondence of PCIE device.
It is understood that since the circuit that new PCIE device will lead to PCIE interface when accessing PCIE interface is led
Logical, to generate level signal, i.e., the signal in place in this step, and then when detecting signal in place establishes host and new
Correspondence between PCIE device, due in the topological relation of the application, FPGA device be equivalent to foundation host with
Middleware between PCIE device, therefore corresponding control logic is executed in FPGA device, it can be realized and pass through FPGA device
The correspondence between host and PCIE device is connected.Due to certainty when the PCIE device that can be worked normally accesses PCIE interface
Level signal can be generated, therefore determines whether there is new PCIE device and detecting whether there are signal in place in this step and connects
Enter, there is higher accuracy.
Step S21: initiating to rescan the interrupt processing application of PCIE device to host, and establish target memory resource with
The subordinate relation of new PCIE device, to be identified by host and use new PCIE device.
It should be noted that announcement can be passed through within first time after initiating interrupt processing application to host in this step
Know that the current PCIE device of host changes, and then temporarily interrupt host to the I O access of PCIE device, and to rescaning
PCIE device to find new PCIE device, and then the corresponding relationship by establishing between new PCIE device and target memory resource,
That is " subordinate relation " is received and processed in I O access by target memory resource when host initiates I O access to new PCIE device.
This step has temporarily interrupted the business that host currently carries out, and then can by way of initiating interrupt processing application to host
Ensure that host completes the load to new PCIE device within first time, when improving the heat new PCIE device of insertion, to new PCIE
The loading efficiency of equipment.
Fig. 4 is the flow chart of the hot-plug method of another PCIE device provided in an embodiment of the present invention.Step in Fig. 4
S10-S11 is identical as Fig. 2, and details are not described herein.
As shown in figure 4, as a preferred embodiment, connecting when detecting that PCIE interface and existing PCIE device disconnect
When connecing, specifically included using the I O access that target memory resource receiving host initiates existing PCIE device:
Step S30: when the signal in place for detecting existing PCIE device disconnects, the existing PCIE of change is initiated to host and is set
The interrupt processing application of standby corresponding memory source, and establish the subordinate relation of target memory resource Yu existing PCIE device.
Step S31: the I O access that existing PCIE device is initiated using target memory resource receiving host.
It is understood that having PCIE device and PCIE when due to extracting existing PCIE device from PCIE interface
Access between interface is blocked, and will lead to level signal disappearance, i.e., signal in place disconnects.When existing PCIE device is in host work
When disconnecting in the state of work with PCIE interface, it may still will appear the case where host initiates I O access to existing PCIE device,
But under present case, the memory source for belonging to existing PCIE device has been released, and can not be normally received and responded host
The I O access of initiation.The occurrence of causing host unstable in order to avoid above situation, this step, which is worked as, detects existing PCIE
When the signal in place of equipment disconnects, interrupt processing application is initiated to host, the corresponding memory source of existing PCIE device is set
It is set to target memory resource, and then achievees the purpose that the subordinate relation established between target memory resource and existing PCIE device.
This step has temporarily interrupted the business that host currently carries out, and then can by way of initiating interrupt processing application to host
Ensure that host sets target memory resource for the corresponding memory source of existing PCIE device within first time, utmostly protects
The stability of host is demonstrate,proved.
In addition, as a preferred embodiment, PCIE device is specially PCIE SSD.
It should be noted that hard disk be it is current carry out big data and when cloud computing is handled, provide data storage support and
The important equipment supported is read, the readwrite performance of hard disk decides whole efficiency when big data and cloud computing are handled.Due to
The rapid development of SSD (solid state hard disk) technology, the performance of SSD constantly rise violently, and the bandwidth of flash memory is higher and higher in SSD bottom, visit
Delay when asking flash media is lower and lower, therefore reading and writing data performance with higher.Present embodiment limits PCIE device
It is set to PCIE SSD, to realize to the hot plug operations of PCIE SSD, user is allow flexibly to replace PCIE according to actual needs
SSD can further increase the scalability and flexibility of system data storage on the basis of high reading and writing data performance, improve
Flexibility when big data and cloud computing are handled to reading and writing data.
In addition, on the basis of the above embodiment, as a preferred embodiment, PCIE SSD is specially NVME
SSD。
NVME SSD is a kind of high-performance solid state hard disk under PCIE SSD type, has lower delay, lower function
Consumption and higher data read-write efficiency, therefore the reading to data can be further increased on the basis of the above embodiment
Write performance.
In addition, as a preferred embodiment, target memory resource specifically include BUS resource, DEVICE resource,
FUNCTION ID resource and MMIO space resource.
It should be noted that BUS (bus) resource is to transmit the common communication of information between the various functional components of computer
The bus of main line, the transmission harness that it is made of conducting wire, the information category transmitted according to computer, computer can divide
For data/address bus, address bus and control bus, it is respectively intended to transmission data, data address and control signal；DEVICE (is set
It is standby) resource required space resources when referring to load PCIE device；FUNCTION ID resource refers to that load PCIE device is every
Space resources required for function；MMIO (Memory mapping I/O) space resources, that is, memory-mapped I/O, I/O equipment quilt
It is placed in memory headroom, it is therefore desirable to certain space resources.Above-mentioned target resource is related in the resource content specifically included
It usually requires the resource content used at work to PCIE device, therefore opposite can guarantee the reliable of PCIE device work
Property.
In addition, as a preferred embodiment, PCIE interface is specially U.2 specification interface.
It should be noted that being released by solid state hard disk form job engineering (SSD Form Factor Work Group)
Interface specification.U.2 can not only PCIE be supported to standardize, moreover it is possible to which the specification such as compatible SAS, SATA has the equipment of access higher
Compatibility, and U.2 interface has faster reading and writing data speed, opposite can guarantee FPGA device PCIE interface and PCIE
The whole efficiency of equipment progress data interaction.
Embodiment three
The present invention also provides a kind of computer readable storage medium, computer journey is stored on computer readable storage medium
Sequence, when computer program is executed by processor the step of the realization such as hot-plug method of above-mentioned PCIE device.
Computer readable storage medium provided by the present invention is in the start-up course of host B IOS, by FPGA device
As PCIE device, the target memory resource by host assignment is obtained and occupies, and then when the PCIE interface of FPGA device accesses
When new PCIE device, the target memory resource occupied in advance is supplied to new PCIE device and is used；When the PCIE of FPGA device connects
When mouth is disconnected with existing PCIE device, i.e., when original memory source of existing PCIE device is released, pass through target memory
Resource receives the I O access initiated by host existing PCIE device.Since this computer readable storage medium first passes through FPGA in advance
Equipment obtains with the identity of PCIE device and occupies the target memory resource of host assignment, therefore goes out during host work
When existing hot plug situation, the target memory resource shared by FPGA device can be supported the master after hot plug as standby resources
Machine work in every is normally carried out, and then ensures the normal work of host, ensure that PCIE device and the constituted system of host
Overall work stability.
In addition, the present invention also provides a kind of hot plug system of PCIE device, the hot plug including above-mentioned PCIE device
Device.
The hot plug system of PCIE device provided by the present invention is to set FPGA in the start-up course of host B IOS
It is standby to be used as PCIE device, the target memory resource by host assignment is obtained and occupies, and then when the PCIE interface of FPGA device connects
When entering new PCIE device, the target memory resource occupied in advance is supplied to new PCIE device and is used；As the PCIE of FPGA device
When interface and existing PCIE device disconnect, i.e., when original memory source of existing PCIE device is released, by target
It deposits resource and receives the I O access initiated by host existing PCIE device.It is set since this system first passes through FPGA device in advance with PCIE
Standby identity obtains and occupies the target memory resource of host assignment, therefore occurs hot plug situation during host work
When, the target memory resource shared by FPGA device can be supported the host work in every after hot plug as standby resources
It is normally carried out, and then ensures the normal work of host, ensure that the overall work of PCIE device and the constituted system of host is stablized
Property.
A kind of hot plug device of PCIE device provided by the present invention, method, medium and system have been carried out in detail above
It is thin to introduce.Each embodiment is described in a progressive manner in specification, the highlights of each of the examples are with other realities
The difference of example is applied, the same or similar parts in each embodiment may refer to each other.For medium disclosed in embodiment and
For system, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, related place is referring to method portion
It defends oneself bright.It should be pointed out that for those skilled in the art, in the premise for not departing from the principle of the invention
Under, it can be with several improvements and modifications are made to the present invention, these improvement and modification also fall into the protection of the claims in the present invention
In range.
It should also be noted that, in the present specification, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes that
A little elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in the process, method, article or apparatus that includes the element.
Claims (10)
1. a kind of hot plug device of PCIE device characterized by comprising
Connect with host, occupy the target memory resource of the host assignment for the identity with PCIE device, and in insertion or
When extracting the PCIE device, the FPGA device of the target memory resource is provided to the PCIE device or the host；
It is connect with the FPGA device, for inserting or pull out the PCIE interface of the PCIE device.
2. a kind of hot-plug method of PCIE device, which is characterized in that the heat applied to PCIE device described in claim 1 is inserted
Pulling device, comprising:
In BIOS start-up course, the target memory money of the host assignment is obtained and occupied with the identity of the PCIE device
Source；
After BIOS starting, when detecting that the PCIE interface accesses new PCIE device, establish the host with
The correspondence of the new PCIE device, and the target memory resource is provided to the new PCIE device；
When detecting that the PCIE interface and existing PCIE device disconnect, using described in target memory resource reception
The I O access that host initiates the existing PCIE device.
3. according to the method described in claim 2, it is characterized in that, it is described the BIOS starting after, when detecting
When stating PCIE interface and accessing new PCIE device, establish the correspondence of the host Yu the new PCIE device, and to it is described newly
PCIE device provides the target memory resource and specifically includes:
After BIOS starting, when detecting the signal in place of the new PCIE device, the host and institute are established
State the correspondence of new PCIE device；
Initiate to rescan the interrupt processing application of the PCIE device to the host, and establish the target memory resource with
The subordinate relation of the new PCIE device, the new PCIE device is identified and used by the host.
4. according to the method described in claim 2, it is characterized in that, described ought detect that the PCIE interface is set with existing PCIE
For when disconnecting, the I O access that the host initiates the existing PCIE device is received using the target memory resource and is had
Body includes:
When the signal in place for detecting the existing PCIE device disconnects, the change existing PCIE is initiated to the host and is set
The interrupt processing application of standby corresponding memory source, and establish the subordinate of the target memory resource Yu the existing PCIE device
Relationship；
The I O access that the host initiates the existing PCIE device is received using the target memory resource.
5. according to the method described in claim 2, it is characterized in that, the PCIE device is specially PCIESSD.
6. according to the method described in claim 5, it is characterized in that, the PCIE SSD is specially NVMESSD.
7. according to the method described in claim 2, it is characterized in that, the target memory resource specifically include BUS resource,
DEVICE resource, FUNCTION ID resource and MMIO space resource.
8. according to method described in claim 2-7 any one, which is characterized in that the PCIE interface is specially U.2 specification
Interface.
9. a kind of computer readable storage medium, which is characterized in that be stored with computer on the computer readable storage medium
Program realizes that the heat such as the described in any item PCIE devices of claim 2 to 8 is inserted when the computer program is executed by processor
The step of draw out method.
10. a kind of hot plug system of PCIE device, which is characterized in that the heat including PCIE device described in claim 1 is inserted
Pulling device.
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