CN107742616A - A kind of semiconductor structure and preparation method thereof - Google Patents
A kind of semiconductor structure and preparation method thereof Download PDFInfo
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- CN107742616A CN107742616A CN201710911901.XA CN201710911901A CN107742616A CN 107742616 A CN107742616 A CN 107742616A CN 201710911901 A CN201710911901 A CN 201710911901A CN 107742616 A CN107742616 A CN 107742616A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 105
- 238000002360 preparation method Methods 0.000 title claims abstract description 46
- 230000008021 deposition Effects 0.000 claims abstract description 142
- 239000013078 crystal Substances 0.000 claims abstract description 117
- 230000006911 nucleation Effects 0.000 claims abstract description 113
- 238000010899 nucleation Methods 0.000 claims abstract description 113
- 239000012495 reaction gas Substances 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000004062 sedimentation Methods 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 13
- 230000007261 regionalization Effects 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 143
- 239000007789 gas Substances 0.000 claims description 84
- 239000012535 impurity Substances 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 28
- 230000008569 process Effects 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 14
- 229910000077 silane Inorganic materials 0.000 claims description 13
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 12
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 12
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 11
- 229910000070 arsenic hydride Inorganic materials 0.000 claims description 10
- 125000004122 cyclic group Chemical group 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 9
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 239000002019 doping agent Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 claims description 7
- 229910000078 germane Inorganic materials 0.000 claims description 3
- 239000011148 porous material Substances 0.000 claims description 2
- 238000007789 sealing Methods 0.000 abstract description 15
- 230000000694 effects Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 189
- 238000010586 diagram Methods 0.000 description 16
- 238000005516 engineering process Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 4
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008520 organization Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 150000001335 aliphatic alkanes Chemical class 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910010277 boron hydride Inorganic materials 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000005660 chlorination reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 125000003963 dichloro group Chemical group Cl* 0.000 description 1
- SCXPRUVUXBMIGZ-UHFFFAOYSA-N dichloromethane;silicon Chemical compound [Si].ClCCl SCXPRUVUXBMIGZ-UHFFFAOYSA-N 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- -1 silicon Alkane Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 238000009423 ventilation Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000010792 warming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
Abstract
The present invention provides a kind of semiconductor structure applied to memory and preparation method thereof, and preparation includes：Semiconductor base material is provided, there are some groove structures in semiconductor substrate；Crystal nucleation layer is formed in the bottom of groove structure and side wall at the first temperature using the first deposition reaction gas, sedimentary condition is provided for subsequent deposition packed layer, the crystal nucleation layer of long brilliant thickness is supplied using the pattern formation of intermittent cycle deposition；Packed layer is formed in nucleus layer surface using the second deposition reaction gas at the second temperature, packed layer is polycrystalline structure, using crystal nucleation layer so that deposition of the packed layer along the bottom of groove structure, side wall and top grows brilliant speed generally in identical, crystal nucleation layer and packed layer filling groove structure.Pass through such scheme, the preparation method of the present invention, can cause each identical to sedimentation rate of packed layer when carrying out trench fill, and then can reduce the generation of sealing phenomenon, so as to reduce because of hole caused by sealing effect, device overall structure stability and electric conductivity are improved.
Description
Technical field
The invention belongs to semiconductor preparing process technical field, more particularly to a kind of semiconductor structure and its preparation side
Method.
Background technology
With the gradual increase of integrated circuit high integration and high performance demands, semiconductor technology is towards smaller feature chi
Very little technology node development.At present, in the manufacturing technology of semiconductor, it is often necessary to carry out the filling of groove and through hole, come
Complete the preparation of semiconductor structure and whole device architecture.
However, deepening continuously with device miniaturization, the size of semiconductor structure is less and less, cause fill groove and
The difficulty of through hole is increasing, particularly when depth-to-width ratio is larger, the mistake that is such as deposited in low pressure chemical deposition technique at it
Cheng Zhong, doped polycrystalline silicon film easily react at the top of groove or slot, and then produce the phenomenon of sealing.With integrated
The micro of circuit size, production technology becomes complex, and higher aspect ratio structures cause when carrying out thin film deposition, more
Easily formed sealing phenomenon, this is primarily due to the top of the groove and touches reacting gas at first, in addition whole channel bottom and
The influence of the factors such as the speed of crystal column surface catching reaction gas of side wall so that the sedimentation rate at top is relatively faster than trenched side-wall
And bottom.Therefore, because the presence of sealing phenomenon so that hole is there is inside the conductive plugs that filling is formed in groove structure,
I.e. so that the sectional area of conductive plugs is reduced, overall conductance can be reduced, as shown in Figure 18 and Figure 19, Figure 18 is shown as existing skill
There is semiconductor structure schematic diagram existing for hole in art in groove structure, wherein, 121 represent the schematic diagram of the hole formed,
Figure 19 is shown as the structural representation in Figure 18 A-A ' sections, in addition, the presence of hole caused by sealing phenomenon so that follow-up
In etch process, once the hole formed is opened, will down it be corroded along hole, so as to destroy device architecture, such as Figure 20
It is shown, it is shown as the schematic diagram to having the groove structure of hole to perform etching in the prior art.
Therefore, a kind of semiconductor structure and preparation method thereof how is provided to solve drawbacks described above, so as to reduce semiconductor
The generation of hole in structure is necessary.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of semiconductor structure and its preparation
Method, for solve the problems, such as in the prior art semiconductor structure formation when because sealing effect produce hole.
In order to achieve the above objects and other related objects, the present invention provides a kind of semiconductor structure preparation method, including such as
Lower step：
1) semiconductor base material is provided, there are some groove structures in the semiconductor substrate；
2) nucleus is formed in the bottom of the groove structure and side wall using the first deposition reaction gas at the first temperature
Layer, for providing sedimentary condition for subsequent deposition packed layer, wherein, using the pattern formation of intermittent cycle deposition for long brilliant thick
The crystal nucleation layer of degree；And
3) packed layer is formed in the nucleus layer surface using the second deposition reaction gas at the second temperature, it is described
Packed layer is polycrystalline structure, wherein, using the crystal nucleation layer cause the packed layer along the bottom of the groove structure, side wall and
It is in generally identical that the deposition at top, which grows brilliant speed, wherein, the crystal nucleation layer and the packed layer fill the groove structure.
As a preferred embodiment of the present invention, in step 2), the forming step of the crystal nucleation layer includes：In reaction chamber
In be alternately passed through the first deposition reaction gas and the operation vacuumized, with the bottom of the groove structure and side
Wall deposits to form the crystal nucleation layer, and the single cycle of intermittent cycle deposition includes once the first deposition reaction gas
Body being passed through and once vacuumizing.
As a preferred embodiment of the present invention, the first deposition reaction gas is passed through the time described in the single cycle
For 1~20 minute, flow is passed through as 0.2~2 liter/min, and the pumpdown time described in the single cycle is 1~20 minute.
As a preferred embodiment of the present invention, the first deposition reaction gas is with the second deposition reaction gas
Identical gas.
As a preferred embodiment of the present invention, in step 2), in the intermittent periods of the first deposition reaction gas, adopt
Deposited with the 3rd deposition reaction gas, to accelerate the formation of the crystal nucleation layer, and the 3rd deposition is anti-under the same terms
The sedimentation rate of gas is answered to be less than the sedimentation rate of the first deposition reaction gas.
As a preferred embodiment of the present invention, the first deposition reaction gas is passed through the time described in the single cycle
For 1~20 minute, the flow being passed through was 0.2~2 liter/min；3rd deposition reaction gas described in the single cycle leads to
The angle of incidence is 1~20 minute, and the flow being passed through is 0.2~2 liter/min.
As a preferred embodiment of the present invention, first temperature is less than the second temperature, wherein, first temperature
Spend for 350~400 degrees Celsius, the second temperature is 450~600 degrees Celsius；Pressure when depositing the crystal nucleation layer for 80~
120 pas, pressure when depositing the packed layer are 80~120 pas, and the described of the crystal nucleation layer formed in step 2) supplies long crystalline substance
Thickness is 0.2~5 nanometer.
As a preferred embodiment of the present invention, the process of the crystal nucleation layer is formed in step 2) with forming institute in step 3)
The process for stating packed layer is completed in same reative cell.
As a preferred embodiment of the present invention, in step 2), the first impurity gas is also passed through when forming the crystal nucleation layer,
First impurity gas is collectively forming the crystal nucleation layer with the first deposition reaction gas, and first impurity gas is mixed
Debris is used for the electric conductivity for increasing the crystal nucleation layer.
As a preferred embodiment of the present invention, first impurity gas leads to simultaneously with the first deposition reaction gas
Enter, the flow of first impurity gas is 0.05~1 liter/min, the composition of first impurity gas include by hydrogen phosphide,
One kind in the group that boron chloride, arsenic hydride and germane are formed.
As a preferred embodiment of the present invention, in step 3), the second impurity gas is also passed through when forming the packed layer,
Second impurity gas is collectively forming the packed layer with the second deposition reaction gas, and second impurity gas is mixed
Debris is used for the electric conductivity for increasing the packed layer.
As a preferred embodiment of the present invention, the forming step of the packed layer includes：It is alternately logical in reaction chamber
Enter the second deposition reaction gas and second impurity gas, handed over by the way of cyclic deposition in the nucleus layer surface
The packed layer is formed for deposition, and the single cycle of the cyclic deposition includes once the logical of the second deposition reaction gas
Enter and once second impurity gas is passed through.
As a preferred embodiment of the present invention, being passed through for the second deposition reaction gas described in the single cycle is controlled
Time is 1~20 minute, and gas flow is 0.2~2 liter/min；The single is controlled to follow the second impurity gas described in product
The time is passed through as 1~10 minute, gas flow is 0.05~1 liter/min, and second impurity gas is included by hydrogen phosphide, three
One kind in the group that boron chloride and arsenic hydride are formed.
As a preferred embodiment of the present invention, in step 2), the crystal nucleation layer formed includes silicon wafer stratum nucleare, step
3) in, the packed layer formed includes polysilicon layer.
As a preferred embodiment of the present invention, the composition of the first deposition reaction gas is included by silane, dichloromethane
One kind in the group that silane and disilane are formed；The composition of the second deposition reaction gas is included by silane, dichloro
One kind in the group that monosilane and disilane are formed.
As a preferred embodiment of the present invention, the composition of the first deposition reaction gas is by silane and dichloromethane silicon
One kind in the combination of alkane and the group being made up of the combination of disilane and dichlorosilane.
The present invention also provides a kind of semiconductor structure, and the semiconductor structure includes：
Semiconductor substrate, and there are some groove structures in the semiconductor substrate；
Crystal nucleation layer, positioned at the bottom of the groove structure and side wall, and with for long brilliant thickness；And
Packed layer, positioned at the nucleus layer surface and the groove structure is full of, the packed layer is polycrystalline structure, described
Packed layer is formed based on the crystal nucleation layer with the long brilliant bottom by the groove structure of anisotropic deposition, sidewall growth, wherein, institute
State crystal nucleation layer and the packed layer fills the groove structure.
As a preferred embodiment of the present invention, the long brilliant thickness of the confession of the crystal nucleation layer is 0.2~5 nanometer, described
The composition of crystal nucleation layer includes silicon wafer core, and the composition of the packed layer includes polysilicon.
As a preferred embodiment of the present invention, the crystal nucleation layer includes doped silicon crystal nucleation layer, and the packed layer includes mixing
Miscellaneous polysilicon layer, wherein, the dopant material of the crystal nucleation layer includes to be formed selected from hydrogen phosphide, boron chloride and arsenic hydride
Group in one of which.
As a preferred embodiment of the present invention, the dopant material of the packed layer is included selected from hydrogen phosphide, tri-chlorination
One of which in the group that boron and arsenic hydride are formed.
As a preferred embodiment of the present invention, in the cross-sectional area of the groove structure, the hole inside the packed layer
The accounting of gap area is less than 3%.
As a preferred embodiment of the present invention, the bottom of the semiconductor substrate is provided with transistor arrangement, the crystal
Tubular construction has grid structure, and the semiconductor structure also includes：
Capacitor arrangement, there is spacing above the transistor arrangement, and with the transistor arrangement；
Wherein, the packed layer and the crystal nucleation layer collectively constitute multiple contact pads, to electrically connect the transistor junction
The grid structure of structure and the capacitor arrangement.
As described above, semiconductor structure of the present invention and preparation method thereof, has the advantages that：
1) preparation method of semiconductor structure provided by the invention, each of packed layer can be caused when carrying out trench fill
It is identical to sedimentation rate, and then the generation of sealing phenomenon can be reduced, so as to reduce because of hole caused by sealing effect；
2) preparation method of semiconductor structure provided by the invention, dense uniform can be formed using techniques such as cyclic depositions
Groove structure inside packed layer, improve the electric conductivity of efficiency and device；
3) semiconductor structure and organization of semiconductor memory provided by the invention have stable electric connection structure layer, so as to
Improve device overall structure stability and electric conductivity.
Brief description of the drawings
Fig. 1 is shown as the flow chart of semiconductor structure preparation method provided by the invention.
Fig. 2 is shown as providing the structural representation of semiconductor substrate in the semiconductor structure preparation of the present invention.
Fig. 3 is shown as being passed through the schematic diagram of the first deposition reaction gas in the semiconductor structure preparation of the present invention.
Fig. 4 is shown as the structural representation after being vacuumized in the semiconductor structure preparation of the present invention.
Fig. 5 is shown as being passed through showing for the first deposition reaction gas again after vacuumizing in the semiconductor structure preparation of the present invention
It is intended to.
Fig. 6 is shown as a kind of process chart for forming crystal nucleation layer provided by the invention.
Fig. 7 is shown as being passed through the 3rd deposition again after being passed through the first deposition reaction gas in the semiconductor structure preparation of the present invention
The schematic diagram of reacting gas.
Fig. 8 is shown as being passed through the first deposition again after being passed through the 3rd deposition reaction gas in the semiconductor structure preparation of the present invention
The schematic diagram of reacting gas.
Fig. 9 is shown as the process chart of another formation crystal nucleation layer provided by the invention.
Figure 10 is shown as the structural representation of the crystal nucleation layer formed in the semiconductor structure preparation of the present invention.
The semiconductor structure preparation that Figure 11 is shown as the present invention carries out the first impurity gas doping when forming crystal nucleation layer
Schematic diagram.
Figure 12 is shown as semiconductor structure of the present invention and prepares a kind of process chart to form doping crystal nucleation layer.
Figure 13 is shown as semiconductor structure of the present invention and prepares another process chart to form doping crystal nucleation layer.
Figure 14 is shown as semiconductor structure of the present invention and prepares the schematic diagram to form packed layer.
Figure 15 is shown as the structural representation that semiconductor structure of the present invention prepares the packed layer to have been formed.
Figure 16 is shown as semiconductor structure of the present invention and prepares the schematic diagram to form doping packed layer.
Figure 17 is shown as semiconductor structure of the present invention and prepares the process chart to form doping packed layer.
Figure 18 is shown as having semiconductor structure schematic diagram existing for hole in groove structure in the prior art.
Figure 19 is shown as the structural representation in Figure 18 A-A ' sections.
Figure 20 is shown as the schematic diagram to having the groove structure of hole to perform etching in the prior art.
Figure 21 is shown as a kind of schematic diagram of device architecture based on semiconductor structure provided by the invention.
Component label instructions
11 semiconductor substrates
111 groove structures
12 groove structure fillers
121 holes
21 semiconductor substrates
211 groove structures
22 crystal nucleation layers
221 first crystal nucleation layers
222 second crystal nucleation layers
23 first impurity gas sedimentaries
24 packed layers
241 first packed layers
25 second impurity gas sedimentaries
31 transistor arrangements
311 grid structures
32 capacitor arrangements
33 semiconductor structures
S1~S3 steps 1)~step 3)
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 1 is referred to Figure 21.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only showing the component relevant with the present invention in diagram rather than according to package count during actual implement
Mesh, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout form may also be increasingly complex.
Embodiment one：
The present invention provides a kind of preparation method of semiconductor structure, comprises the following steps：
As shown in S1 and Fig. 2 in Fig. 1, step 1) is carried out, there is provided semiconductor base material 21, the semiconductor substrate 21
It is interior that there are some groove structures 211；
Specifically, the semiconductor substrate 21 be ordinary skill known to can arbitrarily be formed groove structure and
The groove structure needs the semiconductor structure being filled, and such as the interlayer dielectric layer of semiconductor devices, can form groove structure, its
Conductive plugs are formed after filling, using the interconnection structure as upper and lower device layer, its material can be but be not limited to silica.Separately
Outside, the cross sectional shape of the groove structure can be the shape that rectangle, trapezoidal etc. can arbitrarily realize filling.
As shown in the S2 in Fig. 1 and Fig. 3~13, step 2) is carried out, using the first deposition reaction gas at the first temperature
The crystal nucleation layer 22 of preset thickness is formed in the bottom of the groove structure 211 and side wall；For being provided for subsequent deposition packed layer
Sedimentary condition, wherein, the crystal nucleation layer 22 using the pattern formation that intermittent cycle deposits for long brilliant thickness；And
As shown in the S3 in Fig. 1 and Fig. 3~17, step 3) is carried out, using the second deposition reaction gas at the second temperature
The packed layer 24 full of the groove structure 211 is formed in the surface of crystal nucleation layer 22, wherein, the crystal nucleation layer 22 causes
Sedimentation rate of the packed layer 24 along the bottom of the groove structure 211, side wall and top is in generally identical, wherein, the crystalline substance
Stratum nucleare 22 and the packed layer 24 fill the groove structure.
Specifically, the present invention can improve the groove structure using groove structure 211 described in the process filling of two-part
The grade of 211 inner surface (bottom and side wall) is to sedimentation rate, even if the sedimentation rate everywhere of inner surface is identical, its
In, generally in identical including approximately the same in the range of substantially identical or sedimentation rate difference 5%, so as to reduce the envelope of groove
Mouth effect, reduces the generation of hole, wherein, a layer crystal stratum nucleare is initially formed in the present invention, because the presence of the crystal nucleation layer changes
Become in original wafer the interface (inner surface of i.e. original wafer as groove structure) of the groove directly formed, it is actually former
Seizure of some wafer interfaces to deposited particles is more difficult, therefore easily causes sealing in the case where the top of the groove first has deposition
Phenomenon, particularly, crystal nucleation layer of the present invention have similar physics with the packed layer subsequently to be deposited relative to original wafer interface
Property, follow-up packed layer can grow along the crystal nucleation layer, now, top, side wall and the bottom of the groove structure 211
Sedimentation rate it is consistent, sealing phenomenon can be reduced, and then reduce because of hole caused by sealing.
In addition, the intermittent cycle deposition in the step refers to that circulation is passed through the first deposition reaction gas, it is such as advanced
Row is passed through the first deposition reaction gas of certain flow for the first time, then stops being passed through gas for a period of time, then enters again
Row is passed through the first deposition reaction gas for the second time, then stops a period of time, and the rest may be inferred, and circulation is multiple, relative to continuous
The first deposition reaction gas is passed through, forming method of the invention causes crystal nucleation layer to have the enough reaction time, so as to
The uniform crystal nucleation layer is obtained, and can further obtain the groove structure filler of high quality, wherein, the cyclic deposition
Cycle-index be more than or equal to 1, specific cycle-index is depending on actual conditions need.
Need what is illustrated, due to sealing the presence of phenomenon in the prior art, its obtained structure as shown in Figure 18 and 19, its
In, Figure 19 is shown as the schematic diagram in the A-A ' sections of Figure 18 structures, when the groove structure of the filling is as conductive plugs, due to
It the presence of hole, then can reduce sectional area, and then overall electrical efficiency can be influenceed, wherein, conductive capability G calculation formula
For G=k*A/L, k is the conductance of material, and A is conductor cross sectional area, and L is conductor length；In addition, as shown in figure 20, due to hole
Presence so that in follow-up etching process, once hole is opened, then etching will along hole continue down-cutting errosion,
Such as the part in the dotted line frame in Figure 20, device overall performance is reduced, even results in component failure.
As an example, in step 2), the forming step of the crystal nucleation layer 22 includes：Alternately it is passed through in reaction chamber
The first deposition reaction gas and the operation vacuumized, to be formed in the bottom of the groove structure 211 and side wall deposition
The crystal nucleation layer 22, and the single cycle of intermittent cycle deposition includes once being passed through for the first deposition reaction gas
Once vacuumize, as illustrated in figures 3-6.
As an example, the time that the first deposition reaction gas is passed through described in the single cycle is 1~20 minute, it is passed through
Flow be 0.2~2 liter/min, the pumpdown time described in the single cycle be 1~20 minute.
As an example, the first deposition reaction gas and the second deposition reaction gas phase are same.
Specifically, the present embodiment provides a kind of generation type of the crystal nucleation layer 22, i.e., alternately described first deposition
The operation that reacting gas is passed through and vacuumized, its each sequence of steps schematic diagram is as shown in fig. 6, wherein, vacuum pumping can be gone
The part not deposited in the first deposition reaction gas being passed through except last time, as shown in Figure 3 and Figure 4, behaviour is vacuumized by Fig. 4
Make, eliminate the gas not deposited in Fig. 3, so as to improve the uniformity and compactness in nucleus layer formation process, enter
And by repeatedly ventilation body and the circulation vacuumized, finally give preferable crystal nucleation layer.
In addition, in the method, preferably described first deposition reaction gas is with being subsequently formed described the second of packed layer
The species of deposition reaction gas is identical, selects identical gas more favorably to ensure the uniformity of the two property, so as to the filling
Layer more effectively can grow along the crystal nucleation layer, obtain imporous packed layer.
As an example, in step 2), in the intermittent periods of the first deposition reaction gas, using the 3rd deposition reaction gas
Body is deposited, to accelerate the formation of the crystal nucleation layer 22, and under the same terms the 3rd deposition reaction gas deposition speed
Rate is less than the sedimentation rate of the first deposition reaction gas, as shown in Fig. 3 and Fig. 7~10.
Specifically, the present embodiment additionally provides the forming method of another crystal nucleation layer, in the method, select be
Using the two kinds of gases that can form crystal nucleation layer, i.e., described first deposition reaction gas and the 3rd deposition reaction gas, such as
Shown in Fig. 3 and Fig. 7, Fig. 3 is shown as first being passed through the first deposition reaction gas, then the step of carry out Fig. 7, is passed through another gas
Body, i.e., described 3rd deposition reaction gas, wherein, the 3rd deposition reaction gas is passed through, and on the one hand can drive part away
The first deposition reaction gas of residual, on the other hand, due to being different reacting gas, easily filled up in addition in deposition
A kind of space of gas molecule, so as to obtain the finer and close crystal nucleation layer, further, select two kinds of different sedimentation rates
The first deposition reaction gas and the 3rd deposition reaction gas, one of which gas aggradation can also be avoided too fast, so as to ensure
The uniformity of crystal nucleation layer.
Furthermore it is preferred that it is subsequently formed the second deposition reaction gas of packed layer and the first deposition reaction gas
Body or the 3rd deposition reaction gas phase are same, and selection, can be same with the first deposition reaction gas phase in the present embodiment
With the more favourable uniformity for ensureing the two property, so as to which the packed layer more effectively can grow along the crystal nucleation layer, obtain
To imporous packed layer.
As an example, first gas described in the single cycle was passed through the time as 1~20 minute, the flow being passed through is
0.2~2 liter/min；3rd deposition reaction gas described in the single cycle was passed through the time as 1~20 minute, was passed through
Flow is 0.2~2 liter/min.
Specifically, disclosed in the present embodiment in the cyclic deposition mode of above two crystal nucleation layer, control single gas leads to
The time entered is 1~20 minute, preferably 5~10 minutes；The flow that single gas is passed through is 0.2~2 liter/min (SLM), excellent
Elect 0.5~1.5 liter/min as.In the cyclic deposition mode for depositing and vacuumizing such as the first pure gas, single gas is controlled
The time of body deposition is 6 minutes, and flow is 0.8 liter/min；In the mode of second of two kinds of gas alternating deposits, control first
The time of the deposition of deposition reaction gas and the 3rd deposition reaction gas is 15 minutes, and flow is 1 liter/min.
As an example, first temperature is less than the second temperature, wherein, first temperature is 350~400 Celsius
Degree, the second temperature are 450~600 degrees Celsius；Pressure when depositing the crystal nucleation layer is 80~120 pas, is filled out described in deposition
Pressure when filling layer is 80~120 pas.
As an example, in step 2), the preset thickness of the crystal nucleation layer of formation is 0.2~5 nanometer.
It is the crystal nucleation layer in cryogenic conditions first specifically, control the crystal nucleation layer and the formation condition of packed layer
Lower formation, low temperature can ensure that the sedimentation rate of the crystal nucleation layer is relatively low, thereby may be ensured that the uniformity and crystalline substance of crystal nucleation layer
Controllability in stratum nucleare growth course, it is warming up to higher temperature again afterwards and forms packed layer, to be advantageous to the formation of packed layer,
The doping of the packed layer, and the crystal nucleation layer and the packed layer shape in same reaction chamber can further be promoted
Into.First temperature is preferably 360~380 DEG C, and the present embodiment selection is 370 DEG C, and the second temperature is preferably 480~
550 DEG C, selection is 500 DEG C in the present embodiment.In addition, pressure when depositing the crystal nucleation layer and the packed layer is both preferably
90~110 pas, selection is 100 pas in the present embodiment.The thick crystalline substances of 0.2~5nm can be obtained under conditions of the present embodiment
Stratum nucleare, preferably 0.8~4.5nm, effectively sedimentary condition can be provided for follow-up packed layer under the thickness, and can be with
The preparation efficiency of higher integral device is obtained, is 2nm in the present embodiment.
As an example, the process that the crystal nucleation layer is formed in step 2) exists with forming the process of the packed layer in step 3)
Completed in same reative cell.The homogeneity between the crystal nucleation layer and the packed layer can be advantageously ensured that, helps to reduce
The accounting of hole inside the filling.
As an example, in step 2), the first impurity gas, first impurity gas are also passed through when forming the crystal nucleation layer
The crystal nucleation layer is collectively forming with the first deposition reaction gas, first impurity gas is used to increase the crystal nucleation layer
Electric conductivity, as shown in Figure 11~13.
As an example, first impurity gas is passed through simultaneously with the first deposition reaction gas, first doping
The flow of gas is 0.05~1 liter/min, and the composition of first impurity gas is included by hydrogen phosphide (PH3), boron chloride
(BCl3), arsenic hydride (AsH3) and germane (GeH4) one kind in the group that is formed.
Specifically, in the present embodiment, gas doping also preferably is carried out when forming the crystal nucleation layer, so as to improve
The electric conductivity of crystal nucleation layer.Preferably, first impurity gas is passed through simultaneously with the first deposition reaction gas, so as to simplify
Technique, under the formation condition of the crystal nucleation layer of the present embodiment, the crystal nucleation layer of Uniform Doped can be obtained.First doping
The flow of gas is preferably 0.1~0.5 liter/min, and selection is 0.2 liter/min in the present embodiment.
As an example, in step 3), the second impurity gas, second impurity gas are also passed through when forming the packed layer
The packed layer is collectively forming with the second deposition reaction gas, second impurity gas is used to increase the packed layer
Electric conductivity, as depicted in figs. 16 and 17.
As an example, the forming step of the packed layer includes：It is anti-that second deposition is alternately passed through in reaction chamber
Gas and second impurity gas are answered, is formed by the way of cyclic deposition in the surface alternating deposit of crystal nucleation layer 22 described
Packed layer 24, and the single cycle of the cyclic deposition includes once being passed through and once institute for the second deposition reaction gas
State being passed through for the second impurity gas.
As an example, the time that is passed through for controlling the second deposition reaction gas described in the single cycle is 1~20 minute,
Gas flow is 0.2~2 liter/min；Control what the single followed the second impurity gas described in product to be passed through the time as 1~10 point
Clock, gas flow are 0.05~1 liter/min, and second impurity gas is included by hydrogen phosphide, boron chloride and arsenic hydride institute
One kind in the group of composition.
Specifically, in the present embodiment, it is additionally included in and carries out the second impurity gas during forming the packed layer and enter
The technique of row doping, during the packed layer is formed, select the second deposition reaction gas and second doping
Gas carries out the technique of alternate cycles deposition, so as to obtain packed layer with good conductivity, furthermore it is preferred that described the
Being passed through for two deposition reaction gases and being passed through in the presence of intersecting for second impurity gas, further improve the quality of packed layer.
Specifically, the time that is passed through of the second deposition reaction gas is preferably 5~15 minutes, in the present embodiment selection be
10 minutes, the intake of the second deposition reaction gas was preferably 0.5~1.5 liter/min, and selection is 1 liter/min in the present embodiment
Clock, the time that is passed through of second impurity gas is preferably 2~8 minutes, and selection is 5 minutes in the present embodiment, the second doping gas
The flow of body is preferably 0.1~0.8 liter/min, and selection is 0.5 liter/min in the present embodiment.
As an example, in step 2), in step 2), the crystal nucleation layer that is formed includes silicon wafer stratum nucleare, in step 3), institute
The packed layer formed includes polysilicon layer.
As an example, the composition of the first deposition reaction gas is included by silane, dichlorosilane and disilane institute
One kind in the group of composition；The composition of the second deposition reaction gas is included by silane, dichlorosilane and disilane
One kind in the group formed.
As an example, the composition of the first deposition reaction gas is by the combination of silane and dichlorosilane and by second
One kind in the group that the combination of silane and dichlorosilane is formed.
Specifically, in the present embodiment, the crystal nucleation layer of formation is silicon wafer stratum nucleare, and the packed layer of formation is polycrystalline
Silicon layer, particularly, when forming two kinds of gas of crystal nucleation layer selection, further consider to regulate and control the sedimentation rate of the two, such as sink
Product speed disilane>Silane>Dichlorosilane, then select during gas to be preferably that silane and dichlorosilane match, or second silicon
Alkane and dichlorosilane carry out gas matching.
As shown in figure 11, the present invention also provides a kind of semiconductor structure, wherein, the semiconductor structure is using this implementation
Semiconductor structure obtained by the preparation method for the semiconductor structure that example provides, the semiconductor structure include：
Semiconductor substrate 21, and there are some groove structures 211 in the semiconductor substrate；
Crystal nucleation layer 22, positioned at the bottom of the groove structure 211 and side wall, and with for long brilliant thickness；And
Packed layer 24, positioned at the surface of crystal nucleation layer 22 and the groove structure 211 is full of, the packed layer 24 is polycrystalline
Structure, the packed layer 24 is based on the crystal nucleation layer 22 with bottom of the long crystalline substance of anisotropic deposition by the groove structure, side wall life
Length forms, wherein, the crystal nucleation layer 22 and the packed layer 24 fill the groove structure.
As an example, the long brilliant thickness of the confession of the crystal nucleation layer is 0.2~5 nanometer, the composition bag of the crystal nucleation layer 22
Siliceous nucleus, the composition of the packed layer 24 include polysilicon.
As an example, the crystal nucleation layer 22 includes doped silicon crystal nucleation layer, the packed layer 24 includes doped polysilicon layer, its
In, the dopant material of the crystal nucleation layer 22 is included in the group formed selected from hydrogen phosphide, boron chloride and arsenic hydride
One of which.
As an example, the dopant material of the packed layer 24, which includes, is selected from hydrogen phosphide, boron chloride and arsenic hydride institute
One of which in the group of composition.
Specifically, the present invention provides the semiconductor structure that a kind of groove structure is filled, in semiconductor structure of the invention,
Filler in its groove structure is fine and close, and imporosity, when it is used as conductive plugs, conductive capability is strong, whole device architecture it is steady
It is qualitative strong.Wherein, the 0.2~5nm crystal nucleation layer can be obtained under conditions of the present embodiment, preferably 0.8~4.5nm,
Sedimentary condition effectively can be provided for follow-up packed layer under the thickness, and the preparation of higher integral device can be obtained
Efficiency, it is 2nm in the present embodiment.
As an example, in the cross-sectional area of the groove structure, the accounting of the pore area inside the packed layer is less than
3%.
Specifically, in the structure that the application is formed, its described groove structure is by the packed layer and the crystal nucleation layer
Filling is full, the cross section that the cross section of its groove structure namely the packed layer and the crystal nucleation layer are formed, specific signal
Packed layer its internal void described in the section in reference chart 18 and 19, formed in the application can be corresponded to and account for whole cross section product not
To 3%, even less than 1%, there is significant beneficial effect relative to prior art.
As an example, the bottom of the semiconductor substrate 21 is provided with transistor arrangement 31, the transistor arrangement 31 has
Grid structure 311, the semiconductor structure also include：
Capacitor arrangement 32, there is spacing above the transistor arrangement 31, and with the transistor arrangement 31；
Wherein, the packed layer 24 and the crystal nucleation layer 22 collectively constitute multiple contact pads, to electrically connect the crystal
The grid structure 311 of tubular construction 31 and the capacitor arrangement 32.
Specifically, semiconductor structure that the embodiment of the present invention one is provided and preparation method thereof is used for the storage of the present embodiment
In device structure, the good integral device structure of electric conductivity can be obtained.
In summary, the present invention provides a kind of semiconductor structure and preparation method thereof, wherein the system of the semiconductor structure
It is standby to include：Semiconductor base material is provided, and there is a groove structure in the semiconductor substrate；Using the first deposition reaction gas
Crystal nucleation layer is formed in the bottom of the groove structure and side wall at the first temperature, for providing deposition for subsequent deposition packed layer
Condition, wherein, the crystal nucleation layer using the pattern formation that intermittent cycle deposits for long brilliant thickness；It is and anti-using the second deposition
Gas is answered to form the packed layer in the nucleus layer surface at the second temperature, the packed layer is polycrystalline structure, utilizes institute
State the deposition that crystal nucleation layer causes the packed layer along the bottom of the groove structure, side wall and top and grow brilliant speed generally in identical,
Wherein, the crystal nucleation layer and the packed layer fill the groove structure.Pass through above-mentioned technical proposal, it is provided by the invention partly to lead
The preparation method of body structure, each identical to sedimentation rate of packed layer can make it that when carrying out trench fill, and then can dropped
The generation of low sealing phenomenon, so as to reduce because of hole caused by sealing effect；The preparation side of semiconductor structure provided by the invention
Method, the inside packed layer of the groove structure of dense uniform can be formed using techniques such as cyclic depositions, improve efficiency and device
Electric conductivity；Semiconductor structure and organization of semiconductor memory provided by the invention have stable electric connection structure layer, from
And improve device overall structure stability and electric conductivity.So the present invention effectively overcome various shortcoming of the prior art and
Has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (22)
1. a kind of preparation method of semiconductor structure, it is characterised in that comprise the following steps：
1) semiconductor base material is provided, there are some groove structures in the semiconductor substrate；
2) crystal nucleation layer is formed in the bottom of the groove structure and side wall at the first temperature using the first deposition reaction gas, used
In providing sedimentary condition for subsequent deposition packed layer, wherein, using the pattern formation of intermittent cycle deposition for long brilliant thickness
The crystal nucleation layer；And
3) packed layer, the filling are formed in the nucleus layer surface using the second deposition reaction gas at the second temperature
Layer is polycrystalline structure, causes the packed layer along the heavy of the bottom of the groove structure, side wall and top using the crystal nucleation layer
The long brilliant speed of product is in generally identical, wherein, the crystal nucleation layer and the packed layer fill the groove structure.
2. the preparation method of semiconductor structure according to claim 1, it is characterised in that in step 2), the crystal nucleation layer
Forming step include：The first deposition reaction gas and the operation vacuumized are alternately passed through in reaction chamber,
To form the crystal nucleation layer, and the single cycle of intermittent cycle deposition in the bottom of the groove structure and side wall deposition
Being passed through and once vacuumize including once the first deposition reaction gas.
3. the preparation method of semiconductor structure according to claim 2, it is characterised in that described in the single cycle
One deposition reaction gas was passed through the time as 1~20 minute, and the flow being passed through is 0.2~2 liter/min, in the single cycle
The pumpdown time is 1~20 minute.
4. the preparation method of semiconductor structure according to claim 2, it is characterised in that the first deposition reaction gas with
The second deposition reaction gas is identical gas.
5. the preparation method of semiconductor structure according to claim 1, it is characterised in that in step 2), described first
The intermittent periods of deposition reaction gas, deposited using the 3rd deposition reaction gas, to accelerate the formation of the crystal nucleation layer, and
The sedimentation rate of the 3rd deposition reaction gas is less than the sedimentation rate of the first deposition reaction gas under the same terms.
6. the preparation method of semiconductor structure according to claim 5, it is characterised in that described in the single cycle
One deposition reaction gas was passed through the time as 1~20 minute, and the flow being passed through is 0.2~2 liter/min；In the single cycle
The 3rd deposition reaction gas was passed through the time as 1~20 minute, and the flow being passed through is 0.2~2 liter/min.
7. the preparation method of semiconductor structure according to claim 1, it is characterised in that first temperature is less than described
Second temperature, wherein, first temperature is 350~400 degrees Celsius, and the second temperature is 450~600 degrees Celsius；Deposition
The pressure during crystal nucleation layer is 80~120 pas, and pressure when depositing the packed layer is 80~120 pas, is formed in step 2)
The described of the crystal nucleation layer for long brilliant thickness be 0.2~5 nanometer.
8. the preparation method of semiconductor structure according to claim 1, it is characterised in that the nucleus is formed in step 2)
The process of layer is completed with forming the process of the packed layer in step 3) in same reative cell.
9. the preparation method of semiconductor structure according to claim 1, it is characterised in that in step 2), form the crystalline substance
The first impurity gas is also passed through during stratum nucleare, first impurity gas is collectively forming the crystalline substance with the first deposition reaction gas
Stratum nucleare, the dopant of first impurity gas are used for the electric conductivity for increasing the crystal nucleation layer.
10. the preparation method of semiconductor structure according to claim 9, it is characterised in that first impurity gas with
The first deposition reaction gas is passed through simultaneously, and the flow of first impurity gas is 0.05~1 liter/min, and described first
The composition of impurity gas includes one kind in the group being made up of hydrogen phosphide, boron chloride, arsenic hydride and germane.
11. the preparation method of semiconductor structure according to claim 1, it is characterised in that in step 3), filled out described in formation
The second impurity gas is also passed through when filling layer, second impurity gas is collectively forming described fill out with the second deposition reaction gas
Layer is filled, the dopant of second impurity gas is used for the electric conductivity for increasing the packed layer.
12. the preparation method of semiconductor structure according to claim 11, it is characterised in that the formation step of the packed layer
Suddenly include：The second deposition reaction gas and second impurity gas alternately are passed through in reaction chamber, it is heavy using circulation
Long-pending mode forms the packed layer in the nucleus layer surface alternating deposit, and the single cycle of the cyclic deposition includes one
Being passed through for the secondary second deposition reaction gas and being passed through for once second impurity gas.
13. the preparation method of semiconductor structure according to claim 12, it is characterised in that control in the single cycle
The second deposition reaction gas was passed through the time as 1~20 minute, and gas flow is 0.2~2 liter/min；Control the list
It is secondary follow the second impurity gas described in product be passed through the time as 1~10 minute, gas flow is 0.05~1 liter/min, described the
Two impurity gas include one kind in the group being made up of hydrogen phosphide, boron chloride and arsenic hydride.
14. the preparation method of the semiconductor structure according to any one in claim 1~13, it is characterised in that step
2) in, the crystal nucleation layer that is formed includes silicon wafer stratum nucleare, and in step 3), the packed layer formed includes polysilicon layer.
15. the preparation method of semiconductor structure according to claim 14, it is characterised in that the first deposition reaction gas
The composition of body includes one kind in the group being made up of silane, dichlorosilane and disilane；Second deposition reaction
The composition of gas includes one kind in the group being made up of silane, dichlorosilane and disilane.
16. the preparation method of semiconductor structure according to claim 14, it is characterised in that the first deposition reaction gas
The group for forming to be formed by the combination of silane and dichlorosilane and by the combination of disilane and dichlorosilane of body
In one kind.
17. a kind of semiconductor structure, it is characterised in that the semiconductor structure includes：
Semiconductor substrate, and there are some groove structures in the semiconductor substrate；
Crystal nucleation layer, positioned at the bottom of the groove structure and side wall, and with for long brilliant thickness；And
Packed layer, positioned at the nucleus layer surface and the groove structure is full of, the packed layer is polycrystalline structure, the filling
Layer is formed based on the crystal nucleation layer with the long brilliant bottom by the groove structure of anisotropic deposition, sidewall growth, wherein, the crystalline substance
Stratum nucleare and the packed layer fill the groove structure.
18. semiconductor structure according to claim 17, it is characterised in that the confession of the crystal nucleation layer grows brilliant thickness and is
0.2~5 nanometer, the composition of the crystal nucleation layer includes silicon wafer core, and the composition of the packed layer includes polysilicon.
19. semiconductor structure according to claim 18, it is characterised in that the crystal nucleation layer includes doped silicon crystal nucleation layer,
The packed layer includes doped polysilicon layer, wherein, the dopant material of the crystal nucleation layer is included selected from hydrogen phosphide, boron chloride
And the one of which in the group that is formed of arsenic hydride.
20. semiconductor structure according to claim 19, it is characterised in that the dopant material of the packed layer is included and is selected from
One of which in the group that hydrogen phosphide, boron chloride and arsenic hydride are formed.
21. semiconductor structure according to claim 18, it is characterised in that in the cross-sectional area of the groove structure, institute
The accounting for stating the pore area inside packed layer is less than 3%.
22. the semiconductor structure according to any one of claim 17 to 21, it is characterised in that the semiconductor substrate
Bottom is provided with transistor arrangement, and the transistor arrangement has grid structure, and the semiconductor structure also includes：
Capacitor arrangement, there is spacing above the transistor arrangement, and with the transistor arrangement；
Wherein, the packed layer and the crystal nucleation layer collectively constitute multiple contact pads, to electrically connect the transistor arrangement
The grid structure and the capacitor arrangement.
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