CN207353223U - A kind of semiconductor structure - Google Patents
A kind of semiconductor structure Download PDFInfo
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- CN207353223U CN207353223U CN201721269945.9U CN201721269945U CN207353223U CN 207353223 U CN207353223 U CN 207353223U CN 201721269945 U CN201721269945 U CN 201721269945U CN 207353223 U CN207353223 U CN 207353223U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 239000013078 crystal Substances 0.000 claims abstract description 105
- 230000008021 deposition Effects 0.000 claims abstract description 104
- 230000006911 nucleation Effects 0.000 claims abstract description 101
- 238000010899 nucleation Methods 0.000 claims abstract description 101
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000007789 gas Substances 0.000 claims description 81
- 239000000203 mixture Substances 0.000 claims description 27
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910000077 silane Inorganic materials 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 11
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 10
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 claims description 9
- 229910000070 arsenic hydride Inorganic materials 0.000 claims description 9
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- 239000011148 porous material Substances 0.000 claims description 3
- 238000007789 sealing Methods 0.000 abstract description 15
- 238000004062 sedimentation Methods 0.000 abstract description 15
- 230000000694 effects Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 193
- 238000000151 deposition Methods 0.000 description 107
- 239000012495 reaction gas Substances 0.000 description 71
- 239000012535 impurity Substances 0.000 description 27
- 238000000034 method Methods 0.000 description 24
- 238000010586 diagram Methods 0.000 description 23
- 238000002360 preparation method Methods 0.000 description 20
- 230000008569 process Effects 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 12
- 125000004122 cyclic group Chemical group 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910000078 germane Inorganic materials 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008520 organization Effects 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 150000001335 aliphatic alkanes Chemical class 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 125000003963 dichloro group Chemical group Cl* 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- -1 silicon Alkane Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 238000009423 ventilation Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000010792 warming Methods 0.000 description 1
Abstract
The utility model provides a kind of semiconductor structure applied to memory, including：Semiconductor substrate, and there are some groove structures in semiconductor substrate；Crystal nucleation layer, positioned at the bottom of groove structure and side wall, and with for long brilliant thickness；And filled layer, positioned at nucleus layer surface and groove structure is full of, filled layer is polycrystalline structure, and filled layer is formed based on crystal nucleation layer with the long brilliant bottom by groove structure of anisotropic deposition, sidewall growth, wherein, crystal nucleation layer and filled layer filling groove structure.Through the above scheme, the semiconductor structure of the utility model, can cause each identical to sedimentation rate of filled layer when carrying out trench fill, and then can reduce the generation of sealing phenomenon, so as to reduce the hole produced by sealing effect, device overall structure stability and electric conductivity are improved.
Description
Technical field
The utility model belongs to semiconductor preparing process technical field, more particularly to a kind of semiconductor structure.
Background technology
With the gradual increase of integrated circuit high integration and high performance demands, feature ruler of the semiconductor technology towards smaller
Very little technology node development.At present, in the manufacturing technology of semiconductor, it is often necessary to carry out the filling of groove and through hole, come
Complete the preparation of semiconductor structure and whole device architecture.
However, deepening continuously with device miniaturization, the size of semiconductor structure is less and less, cause fill groove and
The difficulty of through hole is increasing, particularly when depth-to-width ratio is larger, the mistake that is such as deposited in low pressure chemical deposition technique at it
Cheng Zhong, doped polycrystalline silicon film easily react at the top of groove or slot, and then produce the phenomenon of sealing.With integrated
The micro of circuit size, production technology becomes complex, and higher aspect ratio structures cause when carrying out thin film deposition, more
Easily formed sealing phenomenon, this is primarily due to the top of the groove and touches reacting gas at first, in addition whole channel bottom and
The influence of the factors such as the speed of crystal column surface catching reaction gas of side wall so that the sedimentation rate at top is relatively faster than trenched side-wall
And bottom.Therefore, because the presence of sealing phenomenon so that hole is there is inside the conductive plugs that filling is formed in groove structure,
I.e. so that the sectional area of conductive plugs is reduced, overall conductivity can be reduced, as shown in Figure 18 and Figure 19, Figure 18 is shown as Figure 18 and shows
It is shown as that there is semiconductor structure schematic diagram existing for hole in groove structure in the prior art, wherein, 121 represent the hole formed
Schematic diagram, Figure 19 is shown as the structure diagram in Figure 18 A-A ' sections, in addition, the presence of hole caused by sealing phenomenon, makes
Obtain in follow-up etch process, hole once being formed is opened, and will down be corroded along hole, so as to destroy device junction
Structure, as shown in figure 20, is shown as the schematic diagram to having the groove structure of hole to perform etching in the prior art.
Therefore, a kind of semiconductor structure and preparation method thereof how is provided to solve drawbacks described above, so as to reduce semiconductor
The generation of hole in structure is necessary.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of semiconductor structure, use
Because sealing effect produces hole when semiconductor structure formation in the prior art is solved the problems, such as.
In order to achieve the above objects and other related objects, the utility model provides a kind of semiconductor structure preparation method, bag
Include following steps：
1) semiconductor base material is provided, there are some groove structures in the semiconductor substrate；
2) nucleus is formed in the bottom of the groove structure and side wall using the first deposition reaction gas at the first temperature
Layer, for providing sedimentary condition for subsequent deposition filled layer, wherein, using the pattern formation of intermittent cycle deposition for long brilliant
The crystal nucleation layer of thickness；And
3) filled layer is formed in the nucleus layer surface using the second deposition reaction gas at the second temperature, it is described
Filled layer is polycrystalline structure, wherein, using the crystal nucleation layer cause the filled layer along the bottom of the groove structure, side wall and
The brilliant speed of deposition length at top is in generally identical, wherein, the crystal nucleation layer and the filled layer fill the groove structure.
As a kind of preferred solution of the utility model, in step 2), the forming step of the crystal nucleation layer includes：In reaction
The first deposition reaction gas and the operation vacuumized are alternately passed through in chamber, with the bottom of the groove structure
And side wall deposition forms the crystal nucleation layer, and the single cycle of intermittent cycle deposition includes once first deposition instead
Answer being passed through and once vacuumizing for gas.
As a kind of preferred solution of the utility model, the first deposition reaction gas is passed through described in the single cycle
Time is 1~20 minute, is passed through flow as 0.2~2 liter/min, and the pumpdown time described in the single cycle is 1~20 point
Clock.
As a kind of preferred solution of the utility model, the first deposition reaction gas and the second deposition reaction gas
Body is identical gas.
As a kind of preferred solution of the utility model, in step 2), in the interval of the first deposition reaction gas
Section, is deposited using the 3rd deposition reaction gas, to accelerate the formation of the crystal nucleation layer, and it is the described 3rd heavy under the same terms
The sedimentation rate of product reacting gas is less than the sedimentation rate of the first deposition reaction gas.
As a kind of preferred solution of the utility model, the first deposition reaction gas is passed through described in the single cycle
Time is 1~20 minute, and the flow being passed through is 0.2~2 liter/min；3rd deposition reaction gas described in the single cycle
Be passed through the time as 1~20 minute, the flow being passed through is 0.2~2 liter/min.
As a kind of preferred solution of the utility model, first temperature is less than the second temperature, wherein, described
One temperature is 350~400 degrees Celsius, and the second temperature is 450~600 degrees Celsius；Pressure when depositing the crystal nucleation layer is
80~120 pas, pressure when depositing the filled layer are 80~120 pas, the confession of the crystal nucleation layer formed in step 2)
Long crystalline substance thickness is 0.2~5 nanometer.
As a kind of preferred solution of the utility model, the process of the crystal nucleation layer and shape in step 3) are formed in step 2)
Process into the filled layer is completed in same reative cell.
As a kind of preferred solution of the utility model, in step 2), the first doping is also passed through when forming the crystal nucleation layer
Gas, first impurity gas are collectively forming the crystal nucleation layer, the first doping gas with the first deposition reaction gas
The dopant of body is used for the electric conductivity for increasing the crystal nucleation layer.
As a kind of preferred solution of the utility model, first impurity gas and the first deposition reaction gas are same
When be passed through, the flow of first impurity gas is 0.05~1 liter/min, and the composition of first impurity gas is included by phosphorus
One kind in the group that change hydrogen, boron chloride, arsenic hydride and germane are formed.
As a kind of preferred solution of the utility model, in step 3), the second doping is also passed through when forming the filled layer
Gas, second impurity gas are collectively forming the filled layer, the second doping gas with the second deposition reaction gas
The dopant of body is used for the electric conductivity for increasing the filled layer.
As a kind of preferred solution of the utility model, the forming step of the filled layer includes：Handed in reaction chamber
For the second deposition reaction gas and second impurity gas is passed through, in the crystal nucleation layer table by the way of cyclic deposition
Face alternating deposit forms the filled layer, and the single cycle of the cyclic deposition includes once the second deposition reaction gas
Be passed through and once second impurity gas is passed through.
As a kind of preferred solution of the utility model, the second deposition reaction gas described in the single cycle is controlled
The time is passed through as 1~20 minute, gas flow is 0.2~2 liter/min；The single is controlled to follow the second doping gas described in product
Body was passed through the time as 1~10 minute, and gas flow is 0.05~1 liter/min, and second impurity gas is included by phosphatization
One kind in the group that hydrogen, boron chloride and arsenic hydride are formed.
As a kind of preferred solution of the utility model, in step 2), the crystal nucleation layer formed includes silicon wafer stratum nucleare,
In step 3), the filled layer formed includes polysilicon layer.
As a kind of preferred solution of the utility model, the composition of the first deposition reaction gas is included by silane, two
One kind in the group that silyl chloride and disilane are formed；The composition of the second deposition reaction gas include by silane,
One kind in the group that dichlorosilane and disilane are formed.
As a kind of preferred solution of the utility model, the composition of the first deposition reaction gas is by silane and dichloro
One kind in the combination of monosilane and the group being made of the combination of disilane and dichlorosilane.
The utility model also provides a kind of semiconductor structure, and the semiconductor structure includes：
Semiconductor substrate, and there are some groove structures in the semiconductor substrate；
Crystal nucleation layer, positioned at the bottom of the groove structure and side wall, and with for long brilliant thickness；And
Filled layer, positioned at the nucleus layer surface and is full of the groove structure, the filled layer is polycrystalline structure, described
Filled layer is formed based on the crystal nucleation layer with the long brilliant bottom by the groove structure of anisotropic deposition, sidewall growth, wherein, institute
State crystal nucleation layer and the filled layer fills the groove structure.
As a kind of preferred solution of the utility model, the composition of the crystal nucleation layer includes silicon wafer stratum nucleare, the filled layer
Composition include polysilicon layer.
As a kind of preferred solution of the utility model, formed the gas of the silicon wafer stratum nucleare composition include by silane,
One kind in the group that dichlorosilane and disilane are formed；The composition for forming the gas of the polysilicon layer is included by silicon
One kind in the group that alkane, dichlorosilane and disilane are formed.
As a kind of preferred solution of the utility model, formed the gas of the silicon wafer stratum nucleare composition include by silane and
One kind in the combination of dichlorosilane and the group being made of the combination of disilane and dichlorosilane.
As a kind of preferred solution of the utility model, the gas of the silicon wafer stratum nucleare is formed with forming the polysilicon layer
Gas phase it is same.
As a kind of preferred solution of the utility model, the crystal nucleation layer includes doped silicon crystal nucleation layer, the filled layer bag
Doped polysilicon layer is included, wherein, the dopant material of the crystal nucleation layer, which includes, is selected from hydrogen phosphide, boron chloride and arsenic hydride institute
One of which in the group of composition.
As a kind of preferred solution of the utility model, the dopant material of the filled layer is included selected from hydrogen phosphide, three
One of which in the group that boron chloride and arsenic hydride are formed.
As a kind of preferred solution of the utility model, the long brilliant thickness of the confession of the crystal nucleation layer is 0.2~5 nanometer.
As a kind of preferred solution of the utility model, in the cross-sectional area of the groove structure, inside the filled layer
Pore area accounting be less than 3%.
As a kind of preferred solution of the utility model, the bottom of the semiconductor substrate is equipped with transistor arrangement, described
Transistor arrangement has grid structure, and the semiconductor structure further includes：
Capacitor arrangement, has spacing above the transistor arrangement, and with the transistor arrangement；
Wherein, the filled layer and the crystal nucleation layer collectively constitute multiple contact pads, to be electrically connected the transistor junction
The grid structure of structure and the capacitor arrangement.
As described above, the utility model semiconductor structure, has the advantages that：
1) preparation method of semiconductor structure provided by the utility model, can cause filled layer when carrying out trench fill
It is each identical to sedimentation rate, and then can reduce sealing phenomenon generation so that reduce because sealing effect produce hole；
2) preparation method of semiconductor structure provided by the utility model, densification can be formed using techniques such as cyclic depositions
The inside filled layer of uniform groove structure, improves the electric conductivity of efficiency and device；
3) semiconductor structure and organization of semiconductor memory provided by the utility model have stable electric connection structure layer,
So as to improve device overall structure stability and electric conductivity.
Brief description of the drawings
Fig. 1 is shown as the flow chart of semiconductor structure preparation method provided by the utility model.
Fig. 2 is shown as providing the structure diagram of semiconductor substrate in the semiconductor structure preparation of the utility model.
Fig. 3 is shown as being passed through the schematic diagram of the first deposition reaction gas in the semiconductor structure preparation of the utility model.
Fig. 4 is shown as the structure diagram after being vacuumized in the semiconductor structure preparation of the utility model.
Fig. 5 is shown as being passed through the first deposition reaction gas again after vacuumizing in the semiconductor structure preparation of the utility model
Schematic diagram.
Fig. 6 is shown as a kind of process flow chart for forming crystal nucleation layer provided by the utility model.
Fig. 7 is shown as being passed through the 3rd again after being passed through the first deposition reaction gas in the semiconductor structure preparation of the utility model
The schematic diagram of deposition reaction gas.
Fig. 8 is shown as being passed through first again after being passed through the 3rd deposition reaction gas in the semiconductor structure preparation of the utility model
The schematic diagram of deposition reaction gas.
Fig. 9 is shown as the process flow chart of another formation crystal nucleation layer provided by the utility model.
Figure 10 is shown as the structure diagram of the crystal nucleation layer formed in the semiconductor structure preparation of the utility model.
The semiconductor structure that Figure 11 is shown as the utility model prepares and carries out the first impurity gas when forming crystal nucleation layer and mix
Miscellaneous schematic diagram.
Figure 12 is shown as the utility model semiconductor structure and prepares a kind of process flow chart to form doping crystal nucleation layer.
Figure 13 is shown as the utility model semiconductor structure and prepares another process flow chart to form doping crystal nucleation layer.
Figure 14 is shown as the utility model semiconductor structure and prepares the schematic diagram to form filled layer.
Figure 15 is shown as the structure diagram that the utility model semiconductor structure prepares the filled layer to have been formed.
Figure 16 is shown as the utility model semiconductor structure and prepares the schematic diagram to form doping filled layer.
Figure 17 is shown as the utility model semiconductor structure and prepares the process flow chart to form doping filled layer.
Figure 18 is shown as having semiconductor structure schematic diagram existing for hole in groove structure in the prior art.
Figure 19 is shown as the structure diagram in Figure 18 A-A ' sections.
Figure 20 is shown as the schematic diagram to having the groove structure of hole to perform etching in the prior art.
Figure 21 is shown as a kind of schematic diagram of device architecture based on semiconductor structure provided by the invention.
Component label instructions
11 semiconductor substrates
111 groove structures
12 groove structure fillers
121 holes
21 semiconductor substrates
211 groove structures
22 crystal nucleation layers
221 first crystal nucleation layers
222 second crystal nucleation layers
23 first impurity gas sedimentaries
24 filled layers
241 first filled layers
25 second impurity gas sedimentaries
31 transistor arrangements
311 grid structures
32 capacitor arrangements
33 semiconductor structures
S1~S3 steps 1)~step 3)
Embodiment
Illustrate the embodiment of the utility model below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig.1 to Figure 21.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though when only display is with related component in the utility model rather than according to actual implementation in diagram
Component count, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation
Become, and its assembly layout form may also be increasingly complex.
Embodiment one：
The utility model provides a kind of preparation method of semiconductor structure, includes the following steps：
As shown in S1 and Fig. 2 in Fig. 1, step 1) is carried out, there is provided semiconductor base material 21, in the semiconductor substrate 21
With some groove structures 211；
Specifically, the semiconductor substrate 21 for can arbitrarily be formed known to ordinary skill groove structure and
The groove structure needs the semiconductor structure being filled, and such as the interlayer dielectric layer of semiconductor devices, can form groove structure, its
Conductive plugs are formed after filling, using the interconnection structure as upper and lower device layer, its material can be but be not limited to silica.Separately
Outside, the cross sectional shape of the groove structure can be the shape that rectangle, trapezoidal etc. can arbitrarily realize filling.
As shown in the S2 in Fig. 1 and Fig. 3~13, step 2) is carried out, using the first deposition reaction gas at the first temperature
The crystal nucleation layer 22 of preset thickness is formed in the bottom of the groove structure 211 and side wall；For being provided for subsequent deposition filled layer
Sedimentary condition, wherein, the crystal nucleation layer 22 using the pattern formation that intermittent cycle deposits for long brilliant thickness；And
As shown in the S3 in Fig. 1 and Fig. 3~17, step 3) is carried out, using the second deposition reaction gas at the second temperature
The filled layer 24 full of the groove structure 211 is formed in 22 surface of crystal nucleation layer, wherein, the crystal nucleation layer 22 causes
The sedimentation rate at the filled layer 24 along the bottom of the groove structure 211, side wall and top is in generally identical, wherein, the crystalline substance
Stratum nucleare 22 and the filled layer 24 fill the groove structure.
Specifically, the utility model can improve the groove using groove structure 211 described in the process filling of two-part
The grade of the inner surface (bottom and side wall) of structure 211 is to sedimentation rate, even if the sedimentation rate everywhere of inner surface is identical,
Wherein, generally in identical including approximately the same in the range of substantially identical or sedimentation rate difference 5%, so as to reduce groove
Effect is sealed, reduces the generation of hole, wherein, a layer crystal stratum nucleare is initially formed in the utility model, due to the crystal nucleation layer
It is real in the presence of the interface (inner surface of i.e. original wafer as groove structure) for changing the groove directly formed in original wafer
Seizure of original wafer interface to deposited particles is more difficult on border, therefore is easy to make in the case where the top of the groove first has deposition
Into sealing phenomenon, particularly, the utility model crystal nucleation layer has with the filled layer subsequently to be deposited relative to original wafer interface
Similar physical property, follow-up filled layer can be grown along the crystal nucleation layer, at this time, top, the side of the groove structure 211
The sedimentation rate of wall and bottom is consistent, can reduce sealing phenomenon, and then reduce because of hole caused by sealing.
In addition, the intermittent cycle deposition in the step refers to that circulation is passed through the first deposition reaction gas, it is such as advanced
Row is passed through the first deposition reaction gas of certain flow for the first time, then stops being passed through gas for a period of time, then again into
Row is passed through the first deposition reaction gas for the second time, then stops a period of time, and so on, circulation is multiple, relative to continuous
The first deposition reaction gas is passed through, the forming method of the utility model causes crystal nucleation layer to have the enough reaction time, so that
The uniform crystal nucleation layer can be obtained, and can further obtain the groove structure filler of high quality, wherein, the circulation
The cycle-index of deposition is more than or equal to 1, and specific cycle-index is depending on actual conditions need.
Need what is illustrated, due to sealing the presence of phenomenon in the prior art, its obtained structure as shown in Figure 18 and 19, its
In, Figure 19 is shown as the schematic diagram in the A-A ' sections of Figure 18 structures, when the groove structure of the filling is as conductive plugs, due to
The presence of hole, then can reduce sectional area, and then can influence overall electrical efficiency, wherein, the calculation formula of conductive capability G
For G=k*A/L, k is the conductivity of material, and A is conductor cross sectional area, and L is conductor length；In addition, as shown in figure 20, due to hole
Presence so that in follow-up etching process, once hole is opened, then etching will along hole continue down-cutting errosion,
Such as the part in the dotted line frame in Figure 20, device overall performance is reduced, even results in component failure.
As an example, in step 2), the forming step of the crystal nucleation layer 22 includes：Alternately it is passed through in reaction chamber
The first deposition reaction gas and the operation vacuumized, to be formed in the bottom of the groove structure 211 and side wall deposition
The crystal nucleation layer 22, and the single cycle of intermittent cycle deposition includes once being passed through for the first deposition reaction gas
Once vacuumize, as illustrated in figures 3-6.
As an example, the time that the first deposition reaction gas is passed through described in the single cycle is 1~20 minute, it is passed through
Flow be 0.2~2 liter/min, the pumpdown time described in the single cycle be 1~20 minute.
As an example, the first deposition reaction gas and the second deposition reaction gas phase are same.
Specifically, the present embodiment provides a kind of generation type of the crystal nucleation layer 22, i.e., alternately described first deposition
The operation that reacting gas is passed through and vacuumizes, its each sequence of steps schematic diagram is as shown in fig. 6, wherein, vacuum pumping can be gone
Undeposited part in the first deposition reaction gas being passed through except last time, as shown in Figure 3 and Figure 4, behaviour is vacuumized by Fig. 4
Make, eliminate undeposited gas in Fig. 3, so as to improve the uniformity and compactness in nucleus layer formation process, into
And by repeatedly ventilation body and the circulation vacuumized, finally obtain preferable crystal nucleation layer.
In addition, in the method, preferably the first deposition reaction gas is with being subsequently formed described the second of filled layer
The species of deposition reaction gas is identical, selects identical gas more favorably to ensure the uniformity of the two property, so that the filling
Layer can more effectively be grown along the crystal nucleation layer, obtain imporous filled layer.
As an example, in step 2), in the intermittent periods of the first deposition reaction gas, using the 3rd deposition reaction gas
Body is deposited, to accelerate the formation of the crystal nucleation layer 22, and under the same terms the 3rd deposition reaction gas deposition speed
Rate is less than the sedimentation rate of the first deposition reaction gas, as shown in Fig. 3 and Fig. 7~10.
Specifically, the present embodiment additionally provides the forming method of another crystal nucleation layer, in the method, selected as
Using the two kinds of gases that can form crystal nucleation layer, i.e., described first deposition reaction gas and the 3rd deposition reaction gas, such as
Shown in Fig. 3 and Fig. 7, Fig. 3 is shown as first being passed through the first deposition reaction gas, then the step of carry out Fig. 7, is passed through another gas
Body, i.e., described 3rd deposition reaction gas, wherein, the 3rd deposition reaction gas is passed through, and on the one hand can drive part away
In addition the remaining first deposition reaction gas, on the other hand, due to being different reacting gas, is easily filled up in deposition
A kind of gap of gas molecule, so as to obtain the finer and close crystal nucleation layer, further, selects two kinds of different sedimentation rates
The first deposition reaction gas and the 3rd deposition reaction gas, one of which gas aggradation can also be avoided too fast, so as to ensure
The uniformity of crystal nucleation layer.
Furthermore it is preferred that it is subsequently formed the second deposition reaction gas of filled layer and the first deposition reaction gas
Body or the 3rd deposition reaction gas phase are same, and selected as and the first deposition reaction gas phase are same in the present embodiment, can
With the more favourable uniformity for ensureing the two property, so that the filled layer can more effectively be grown along the crystal nucleation layer, obtain
To imporous filled layer.
As an example, first gas described in the single cycle was passed through the time as 1~20 minute, the flow being passed through is
0.2~2 liter/min；3rd deposition reaction gas described in the single cycle was passed through the time as 1~20 minute, was passed through
Flow is 0.2~2 liter/min.
Specifically, disclosed in the present embodiment in the cyclic deposition mode of above two crystal nucleation layer, control single gas leads to
The time entered is 1~20 minute, is preferably 5~10 minutes；The flow that single gas is passed through is 0.2~2 liter/min (SLM), excellent
Elect 0.5~1.5 liter/min as.In the cyclic deposition mode for depositing and vacuumizing such as the first pure gas, single gas is controlled
The time of deposition is 6 minutes, and flow is 0.8 liter/min；In the mode of second of two kinds of gas alternating deposits, control first is heavy
The time of the deposition of product reacting gas and the 3rd deposition reaction gas is 15 minutes, and flow is 1 liter/min.
As an example, first temperature is less than the second temperature, wherein, first temperature is Celsius for 350~400
Degree, the second temperature are 450~600 degrees Celsius；Pressure when depositing the crystal nucleation layer is 80~120 pas, is filled out described in deposition
Pressure when filling layer is 80~120 pas.
As an example, in step 2), the preset thickness of the crystal nucleation layer of formation is 0.2~5 nanometer.
It is the crystal nucleation layer in cryogenic conditions first specifically, control the crystal nucleation layer and the formation condition of filled layer
Lower formation, low temperature can ensure that the sedimentation rate of the crystal nucleation layer is relatively low, thereby may be ensured that the uniformity and crystalline substance of crystal nucleation layer
Controllability in stratum nucleare growth course, is warming up to higher temperature and forms filled layer again afterwards, to be conducive to the formation of filled layer,
The doping of the filled layer, and the crystal nucleation layer and the filled layer shape in same reaction chamber can further be promoted
Into.First temperature is preferably 360~380 DEG C, 370 DEG C of the present embodiment selected as, and the second temperature is preferably 480~
550 DEG C, 500 DEG C of selected as in the present embodiment.In addition, pressure when depositing the crystal nucleation layer and the filled layer is both preferably
90~110 pas, 100 pa of selected as in the present embodiment.The crystalline substance of 0.2~5nm thickness can be obtained under conditions of the present embodiment
Stratum nucleare, is preferably 0.8~4.5nm, effectively can provide sedimentary condition for follow-up filled layer under the thickness, and can obtain
It is 2nm in the present embodiment to the preparation efficiency of higher integral device.
As an example, the process that the crystal nucleation layer is formed in step 2) exists with forming the process of the filled layer in step 3)
Completed in same reative cell.It can advantageously ensure that the homogeneity between the crystal nucleation layer and the filled layer, help to reduce
The accounting of hole inside the filling.
As an example, in step 2), the first impurity gas, first impurity gas are also passed through when forming the crystal nucleation layer
The crystal nucleation layer is collectively forming with the first deposition reaction gas, first impurity gas is used to increase the crystal nucleation layer
Electric conductivity, as shown in Figure 11~13.
As an example, first impurity gas is passed through at the same time with the first deposition reaction gas, first doping
The flow of gas is 0.05~1 liter/min, and the composition of first impurity gas is included by hydrogen phosphide (PH3), boron chloride
(BCl3), arsenic hydride (AsH3) and germane (GeH4) one kind in the group that is formed.
Specifically, in the present embodiment, gas doping also preferably is carried out when forming the crystal nucleation layer, so as to improve
The electric conductivity of crystal nucleation layer.Preferably, first impurity gas is passed through at the same time with the first deposition reaction gas, so as to simplify
Technique, under the formation condition of the crystal nucleation layer of the present embodiment, can obtain the crystal nucleation layer of Uniform Doped.First doping
The flow of gas is preferably 0.1~0.5 liter/min, 0.2 liter/min of selected as in the present embodiment.
As an example, in step 3), the second impurity gas, second impurity gas are also passed through when forming the filled layer
The filled layer is collectively forming with the second deposition reaction gas, second impurity gas is used to increase the filled layer
Electric conductivity, as depicted in figs. 16 and 17.
As an example, the forming step of the filled layer includes：It is anti-that second deposition is alternately passed through in reaction chamber
Gas and second impurity gas are answered, is formed by the way of cyclic deposition in the 22 surface alternating deposit of crystal nucleation layer described
Filled layer 24, and the single cycle of the cyclic deposition include once the second deposition reaction gas being passed through and it is once described
Second impurity gas is passed through.
As an example, the time that is passed through for controlling the second deposition reaction gas described in the single cycle is 1~20 minute,
Gas flow is 0.2~2 liter/min；Control what the single followed the second impurity gas described in product to be passed through the time as 1~10 point
Clock, gas flow are 0.05~1 liter/min, and second impurity gas is included by hydrogen phosphide, boron chloride and arsenic hydride institute
One kind in the group of composition.
Specifically, in the present embodiment, be additionally included in during forming the filled layer carry out the second impurity gas into
The technique of row doping, during the filled layer is formed, selects the second deposition reaction gas and second doping
Gas carries out the technique of alternate cycles deposition, so as to obtain filled layer with good conductivity, furthermore it is preferred that described the
Being passed through for two deposition reaction gases and being passed through in the presence of intersecting for second impurity gas, further improve the quality of filled layer.
Specifically, the time that is passed through of the second deposition reaction gas is preferably 5~15 minutes, selected as in the present embodiment
10 minutes, the intake of the second deposition reaction gas was preferably 0.5~1.5 liter/min, 1 liter/min of selected as in the present embodiment
Clock, the time that is passed through of second impurity gas is preferably 2~8 minutes, selected as 5 minutes in the present embodiment, the second doping gas
The flow of body is preferably 0.1~0.8 liter/min, 0.5 liter/min of selected as in the present embodiment.
As an example, in step 2), in step 2), the crystal nucleation layer that is formed includes silicon wafer stratum nucleare, in step 3), institute
The filled layer formed includes polysilicon layer.
As an example, the composition of the first deposition reaction gas is included by silane, dichlorosilane and disilane institute
One kind in the group of composition；The composition of the second deposition reaction gas is included by silane, dichlorosilane and disilane
One kind in the group formed.
As an example, the composition of the first deposition reaction gas is by the combination of silane and dichlorosilane and by second
One kind in the group that the combination of silane and dichlorosilane is formed.
Specifically, in the present embodiment, the crystal nucleation layer of formation is silicon wafer stratum nucleare, and the filled layer of formation is polycrystalline
Silicon layer, particularly, when forming two kinds of gas of crystal nucleation layer selection, further considers to regulate and control the sedimentation rate of the two, such as sinks
Product speed disilane>Silane>Dichlorosilane, then select preferably silane and dichlorosilane during gas to match, or second silicon
Alkane and dichlorosilane carry out gas matching.
As shown in figure 11, the utility model also provides a kind of semiconductor structure, wherein, the semiconductor structure is using this
The obtained semiconductor structure of preparation method for the semiconductor structure that embodiment provides, the semiconductor structure include：
Semiconductor substrate 21, and there are some groove structures 211 in the semiconductor substrate；
Crystal nucleation layer 22, positioned at the bottom of the groove structure 211 and side wall, and with for long brilliant thickness；And
Filled layer 24, positioned at 22 surface of crystal nucleation layer and is full of the groove structure 211, the filled layer 24 is polycrystalline
Structure, the filled layer 24 is based on the crystal nucleation layer 22 with bottom of the long crystalline substance of anisotropic deposition by the groove structure, side wall life
Length forms, wherein, the crystal nucleation layer 22 and the filled layer 24 fill the groove structure.
As an example, the long brilliant thickness of the confession of the crystal nucleation layer is 0.2~5 nanometer.
As an example, the composition of the crystal nucleation layer 22 includes silicon wafer stratum nucleare, the composition of the filled layer 24 includes polysilicon
Layer.
As an example, the composition for forming the gas of the silicon wafer stratum nucleare is included by silane, dichlorosilane and disilane
One kind in the group formed；The composition for forming the gas of the polysilicon layer is included by silane, dichlorosilane and second
One kind in the group that silane is formed.
As an example, formed the gas of the silicon wafer stratum nucleare composition comprising by silane and dichlorosilane combination and
One kind in the group be made of the combination of disilane and dichlorosilane.
As an example, formed the gas of the silicon wafer stratum nucleare and formed the polysilicon layer gas phase it is same.
As an example, the crystal nucleation layer 22 includes doped silicon crystal nucleation layer, the filled layer 24 includes doped polysilicon layer, its
In, the dopant material of the crystal nucleation layer 22 is included in the group that hydrogen phosphide, boron chloride and arsenic hydride are formed
One of which.
As an example, the dopant material of the filled layer 24, which includes, is selected from hydrogen phosphide, boron chloride and arsenic hydride institute
One of which in the group of composition.
Specifically, the utility model provides the semiconductor structure that a kind of groove structure is filled, the utility model is partly led
In body structure, the filler in its groove structure is fine and close, and imporosity, when it is used as conductive plugs, conductive capability is strong, whole device
The stability of structure is strong.Wherein, the crystal nucleation layer of 0.2~5nm can be obtained under conditions of the present embodiment, is preferably 0.8
~4.5nm, effectively sedimentary condition can be provided under the thickness for follow-up filled layer, and can obtain higher overall device
The preparation efficiency of part, is 2nm in the present embodiment.
As an example, in the cross-sectional area of the groove structure, the accounting of the pore area inside the filled layer is less than
3%.
Specifically, in the structure that the application is formed, its described groove structure is by the filled layer and the crystal nucleation layer
Filling is full, the cross section that the cross section of its groove structure namely the filled layer and the crystal nucleation layer are formed, specific signal
Filled layer its internal void described in the section in reference chart 18 and 19, formed in the application can be corresponded to and account for whole cross section product not
To 3%, even less than 1%, there is significant beneficial effect relative to the prior art.
As an example, the bottom of the semiconductor substrate 21 is equipped with transistor arrangement 31, the transistor arrangement 31 has
Grid structure 311, the semiconductor structure further include：
Capacitor arrangement 32, has spacing above the transistor arrangement 31, and with the transistor arrangement 31；
Wherein, the filled layer 24 and the crystal nucleation layer 22 collectively constitute multiple contact pads, to be electrically connected the crystal
The grid structure 311 of pipe structure 31 and the capacitor arrangement 32.
Specifically, semiconductor structure that the utility model embodiment one is provided and preparation method thereof is used for the present embodiment
In memory construction, the good integral device structure of electric conductivity can be obtained.
In conclusion the utility model provides a kind of semiconductor structure, wherein the semiconductor structure includes：It is semiconductor-based
Material, and there are some groove structures in the semiconductor substrate；Crystal nucleation layer, positioned at the bottom of the groove structure and side wall, and
With for long brilliant thickness；And filled layer, positioned at the nucleus layer surface and the groove structure is full of, the filled layer is more
Crystal structure, the filled layer is based on the crystal nucleation layer with bottom of the long crystalline substance of anisotropic deposition by the groove structure, sidewall growth
Form, wherein, the crystal nucleation layer and the filled layer fill the groove structure.Through the above technical solutions, the utility model
The preparation method of the semiconductor structure of offer, can cause each identical to sedimentation rate of filled layer when carrying out trench fill,
And then the generation of sealing phenomenon can be reduced, so as to reduce the hole produced by sealing effect；It is provided by the utility model partly to lead
The preparation method of body structure, can form the inside filled layer of the groove structure of dense uniform using techniques such as cyclic depositions, carry
The electric conductivity of high efficiency and device；Semiconductor structure and organization of semiconductor memory provided by the utility model, which have, to be stablized
Electric connection structure layer, so as to improve device overall structure stability and electric conductivity.So the utility model effectively overcomes now
There is the various shortcoming in technology and have high industrial utilization.
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
God and all equivalent modifications completed under technological thought or change, should be covered by the claim of the utility model.
Claims (10)
1. a kind of semiconductor structure, it is characterised in that the semiconductor structure includes：
Semiconductor substrate, and there are some groove structures in the semiconductor substrate；
Crystal nucleation layer, positioned at the bottom of the groove structure and side wall, and with for long brilliant thickness；And
Filled layer, positioned at the nucleus layer surface and is full of the groove structure, and the filled layer is polycrystalline structure, the filling
Layer is formed based on the crystal nucleation layer with the long brilliant bottom by the groove structure of anisotropic deposition, sidewall growth, wherein, the crystalline substance
Stratum nucleare and the filled layer fill the groove structure.
2. semiconductor structure according to claim 1, it is characterised in that the composition of the crystal nucleation layer includes silicon wafer stratum nucleare,
The composition of the filled layer includes polysilicon layer.
3. semiconductor structure according to claim 2, it is characterised in that form the composition bag of the gas of the silicon wafer stratum nucleare
Containing one kind in the group being made of silane, dichlorosilane and disilane；Form the group of the gas of the polysilicon layer
One kind into comprising the group being made of silane, dichlorosilane and disilane.
4. semiconductor structure according to claim 3, it is characterised in that form the composition bag of the gas of the silicon wafer stratum nucleare
One kind in the group formed containing the combination by silane and dichlorosilane and by the combination of disilane and dichlorosilane.
5. semiconductor structure according to claim 2, it is characterised in that form the gas of the silicon wafer stratum nucleare with forming institute
The gas phase for stating polysilicon layer is same.
6. semiconductor structure according to claim 2, it is characterised in that the crystal nucleation layer includes doped silicon crystal nucleation layer, institute
Stating filled layer includes doped polysilicon layer, wherein, the dopant material of the crystal nucleation layer include selected from hydrogen phosphide, boron chloride with
And the one of which in the group that is formed of arsenic hydride.
7. semiconductor structure according to claim 6, it is characterised in that the dopant material of the filled layer is included and is selected from
One of which in the group that hydrogen phosphide, boron chloride and arsenic hydride are formed.
8. semiconductor structure according to claim 1, it is characterised in that the confession of the crystal nucleation layer grows brilliant thickness and is
0.2~5 nanometer.
9. semiconductor structure according to claim 1, it is characterised in that described in the cross-sectional area of the groove structure
The accounting of pore area inside filled layer is less than 3%.
10. semiconductor structure according to any one of claim 1 to 9, it is characterised in that the bottom of the semiconductor substrate
Portion is equipped with transistor arrangement, and the transistor arrangement has grid structure, and the semiconductor structure further includes：
Capacitor arrangement, has spacing above the transistor arrangement, and with the transistor arrangement；
Wherein, the filled layer and the crystal nucleation layer collectively constitute multiple contact pads, to be electrically connected the transistor arrangement
The grid structure and the capacitor arrangement.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106816384A (en) * | 2015-11-30 | 2017-06-09 | 英飞凌科技股份有限公司 | Make the method and device of layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106816384A (en) * | 2015-11-30 | 2017-06-09 | 英飞凌科技股份有限公司 | Make the method and device of layer |
| CN106816384B (en) * | 2015-11-30 | 2019-11-15 | 英飞凌科技股份有限公司 | Make the method and device of layer |
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