CN103137450A - Trench type power metal oxide semiconductor (MOS) device and manufacturing process thereof - Google Patents
Trench type power metal oxide semiconductor (MOS) device and manufacturing process thereof Download PDFInfo
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- CN103137450A CN103137450A CN2011103749460A CN201110374946A CN103137450A CN 103137450 A CN103137450 A CN 103137450A CN 2011103749460 A CN2011103749460 A CN 2011103749460A CN 201110374946 A CN201110374946 A CN 201110374946A CN 103137450 A CN103137450 A CN 103137450A
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Abstract
The invention discloses a manufacturing process of a trench type power metal oxide semiconductor (MOS) device. The process includes the following steps that (1) a layer of polycrystalline silicon is deposited in a trench with grown gate-oxide, and the thickness of the polycrystalline silicon necessarily guarantees a sufficient gap in the trench so that silicide of metal tungsten can be smoothly and subsequently filled in step (2); (2) a layer of silicide of metal tungsten is deposited on an all silicon wafer so as to fully fill the gap in the trench; (3) the silicide of metal tungsten and the polycrystalline silicon are back etched to surface gate-oxide by a dry etching; and (4) subsequent steps of body area filling and propelling, source area filling and propelling, interlayer dielectric medium deposition, etching contacting hole and contacting hole filling and top layer metal deposition are performed. Besides, the invention further discloses a trench type power MOS device. According to the trench type power MOS device and the manufacturing process thereof, a layer of silicide of metal tungsten (WSix) is grown on a grid electrode on the basis of existing trench type power MOS processes so that the obtained grid resistance is lower than that of prior processes.
Description
Technical field
The invention belongs to the semiconductor integrated circuit manufacturing process, relate in particular to a kind of groove type power MOS device and method of manufacturing technology thereof.
Background technology
In semiconductor integrated circuit, the structure of existing typical groove type power MOS (metal-oxide semiconductor (MOS)) device as shown in Figure 1, comprise from the bottom to top silicon substrate, drain electrode, tagma, source region, gate trench, contact hole, interlayer dielectric and top-level metallic, grow successively in gate trench grid oxygen and polysilicon.
Present common groove type power MOS device, the factor that affects resistance is mainly that groove dimensions and polysilicon mix concentration.The ubiquitous problem of existing groove type power MOS device is that resistance is higher.Therefore, how reducing the groove type power MOS device resistance, is the problem of needing solution badly.Idea of the present invention is the silicide (WSix) of growth layer of metal tungsten on grid polycrystalline silicon, makes resistance only be the resistance magnitude of metal, reaches the performance of planar device.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of method of manufacturing technology of groove type power MOS device, the present invention is on the basis of existing groove type power MOS technique, silicide (WSix) by growth layer of metal tungsten on grid obtains the lower resistance of more original technique.For this reason, the present invention also provides a kind of groove type power MOS device.
For solving the problems of the technologies described above, the invention provides a kind of method of manufacturing technology of groove type power MOS device, comprise the steps:
Step 2, the silicide of deposition layer of metal tungsten is to fill up the groove internal pore on the total silicon sheet;
In step 1, in described groove, growth grid oxygen adopts the dried oxygen technique of high temperature, and growth temperature range is 900～1050 degrees centigrade, and the thickness of described grid oxygen is 150～1000 dusts.Described polysilicon adopts the chemical vapour deposition technique deposition, and the depositing temperature scope is 500～600 degrees centigrade, and the thickness of this polysilicon is 500～1000 dusts.
In step 2, the silicide of described deposition layer of metal tungsten adopts chemical vapour deposition technique, and the depositing temperature scope is 550～600 degrees centigrade, and the thickness of the silicide of this tungsten is 1500～2500 dusts.
In step 3, described dry etching is take grid oxygen as etching stop layer.
In addition, the present invention also provides a kind of groove type power MOS device, comprises from the bottom to top silicon substrate, drain electrode, tagma, source region, gate trench, contact hole, interlayer dielectric, top-level metallic; Grow successively in the gate trench silicide of grid oxygen, polysilicon and tungsten makes the silicide that is provided with tungsten in gate trench in the middle of polysilicon to reduce resistance Rg.
Compared to the prior art, the present invention has following beneficial effect: the present invention is on the manufacturing process basis of original groove type power MOS device, chemical vapor deposition WSix and WSix etch step have only been increased, just greatly reduced the thickness of polysilicon deposition, technical process is simple, process costs increases less, but can obtain the lower device than existing groove type power MOS device product resistance Rg, thereby improve the resistance of device.
Description of drawings
Fig. 1 is the generalized section of existing typical groove type power MOS device structure;
Fig. 2-Fig. 5 is the process flow diagram that adopts the inventive method; Wherein, Fig. 2 is the generalized section after the inventive method step 1 is completed; Fig. 3 is the generalized section after the inventive method step 2 is completed; Fig. 4 is the generalized section after the inventive method step 3 is completed; Fig. 5 is the generalized section (being the generalized section of groove type power MOS device structure of the present invention) after the inventive method step 4 is completed.
Description of reference numerals in figure:
1 is epitaxial loayer, as the MOS device drain; 2 is grid oxic horizon; 3 is grid polycrystalline silicon; 4 is the silicide (WSix) of tungsten; 5 is the source region; 6 are body district (being the tagma); 7 is interlayer dielectric; 8 is contact hole; 9 is top-level metallic; 10 is the contact hole injection region.
Embodiment
The present invention is further detailed explanation below in conjunction with drawings and Examples.
As Fig. 2～shown in Figure 5, the method for manufacturing technology of a kind of groove type power MOS device of the present invention specifically comprises the steps:
1. be at first that etching forms gate trench on silicon substrate, in groove by the dried oxygen technique of high temperature growth one deck grid oxic horizon 2, its thickness is 150～1000 dusts (visual organ spare requires to decide), temperature range is 900～1050 degrees centigrade, deposit the grid polycrystalline silicon 3 of layer with the method for chemical vapour deposition (CVD) in the groove of grid oxic horizon 2 of having grown, the depositing temperature scope is 500～600 degrees centigrade, the thickness of grid polycrystalline silicon 3 is 500～1000 dusts (take 0.4 micron wide groove as example), guarantee to have in groove enough spaces to deposit with the silicide (WSix) of convenient follow-up tungsten be as the criterion (seeing Fig. 2).
2. the method with chemical vapour deposition (CVD) deposits the silicide 4 of layer of metal tungsten on grid polycrystalline silicon 3, the depositing temperature scope is 550～600 degrees centigrade, the thickness of the silicide 4 of tungsten is 1500～2500 dusts, to guarantee to fill up groove space be as the criterion (seeing Fig. 3).
3. the silicide 4 of dry etching tungsten and grid polycrystalline silicon 3 to grid oxic horizon 2 surfaces, (are seen Fig. 4) take grid oxic horizon 2 as etching stop layer.
4. subsequent technique and conventional power MOS transistor device technology are in full accord (comprises that tagma 6 is injected, propelling, source region 5 is injected, is advanced, interlayer dielectric 7 deposits, forming contact hole 8 and contact hole injects and forms contact hole injection region 10, the steps such as top-level metallic 9 depositions), finally obtain the lower device of a kind of resistance (seeing Fig. 5).As shown in Figure 5, groove type power MOS device of the present invention comprises drain electrode 1, tagma 6, source region 5, gate trench, contact hole 8, interlayer dielectric 7, top-level metallic 9 from the bottom to top; Grow successively in the gate trench silicide 4 of grid oxic horizon 2, grid polycrystalline silicon 3 and tungsten is provided with the silicide 4 of tungsten to reduce resistance Rg in the middle of making gate trench inner grid polysilicon 2.
Claims (6)
1. the method for manufacturing technology of a groove type power MOS device, is characterized in that: comprise the steps:
Step 1, deposition one deck polysilicon in the groove of grid oxygen of having grown, polysilicon thickness should be guaranteed enough spaces are arranged in groove so that subsequent step 2 is inserted the silicide of tungsten smoothly;
Step 2, the silicide of deposition layer of metal tungsten is to fill up the groove internal pore on the total silicon sheet;
Step 3 is returned the silicide of tungsten and polysilicon by dry etching and is carved to surperficial grid oxygen;
Step 4 comprises that the tagma is injected, propelling, and the source region is injected, advanced, the interlayer dielectric deposit, and etching contact hole and contact hole inject, the subsequent technique of top-level metallic deposition step.
2. the method for manufacturing technology of power MOS (Metal Oxide Semiconductor) device as claimed in claim 1, it is characterized in that: in step 1, in described groove, growth grid oxygen adopts the dried oxygen technique of high temperature, and growth temperature range is 900～1050 degrees centigrade, and the thickness of described grid oxygen is 150～1000 dusts.
3. the method for manufacturing technology of power MOS (Metal Oxide Semiconductor) device as claimed in claim 1 or 2, it is characterized in that: in step 1, described polysilicon adopts the chemical vapour deposition technique deposition, and the depositing temperature scope is 500～600 degrees centigrade, and the thickness of this polysilicon is 500～1000 dusts.
4. the method for manufacturing technology of power MOS (Metal Oxide Semiconductor) device as claimed in claim 1, it is characterized in that: in step 2, the silicide of described deposition layer of metal tungsten adopts chemical vapour deposition technique, and the depositing temperature scope is 550～600 degrees centigrade, and the thickness of the silicide of this tungsten is 1500～2500 dusts.
5. the method for manufacturing technology of power MOS (Metal Oxide Semiconductor) device as claimed in claim 1, it is characterized in that: in step 3, described dry etching is take grid oxygen as etching stop layer.
6. a groove type power MOS device, comprise silicon substrate, drain electrode, tagma, source region, gate trench, contact hole, interlayer dielectric, top-level metallic from the bottom to top; It is characterized in that: the silicide of grow successively in gate trench grid oxygen, polysilicon and tungsten makes the silicide that is provided with tungsten in gate trench in the middle of polysilicon to reduce resistance Rg.
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| CN2011103749460A CN103137450A (en) | 2011-11-22 | 2011-11-22 | Trench type power metal oxide semiconductor (MOS) device and manufacturing process thereof |
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| CN2011103749460A CN103137450A (en) | 2011-11-22 | 2011-11-22 | Trench type power metal oxide semiconductor (MOS) device and manufacturing process thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538452A (en) * | 2014-12-29 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Structure of groove type MOSFET and manufacturing method |
| CN105762193A (en) * | 2016-04-28 | 2016-07-13 | 上海格瑞宝电子有限公司 | MOSFET and preparation method thereof |
| CN107017167A (en) * | 2017-03-01 | 2017-08-04 | 上海华虹宏力半导体制造有限公司 | The manufacture method of trench-gate device with shield grid |
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| CN1757117A (en) * | 2003-03-05 | 2006-04-05 | 先进模拟科技公司 | Trench power MOSFET with planarized gate bus |
| CN1787194A (en) * | 2004-12-08 | 2006-06-14 | 上海华虹Nec电子有限公司 | Method for mfg. large power MOS tube with small wire wide slot type structure |
| CN1979828A (en) * | 2005-12-07 | 2007-06-13 | 中国科学院物理研究所 | Metal silicide nano-wire and its making method |
| US20090140329A1 (en) * | 2007-11-14 | 2009-06-04 | Rohm Co. Ltd. | Semiconductor Device |
-
2011
- 2011-11-22 CN CN2011103749460A patent/CN103137450A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1757117A (en) * | 2003-03-05 | 2006-04-05 | 先进模拟科技公司 | Trench power MOSFET with planarized gate bus |
| CN1787194A (en) * | 2004-12-08 | 2006-06-14 | 上海华虹Nec电子有限公司 | Method for mfg. large power MOS tube with small wire wide slot type structure |
| CN1979828A (en) * | 2005-12-07 | 2007-06-13 | 中国科学院物理研究所 | Metal silicide nano-wire and its making method |
| US20090140329A1 (en) * | 2007-11-14 | 2009-06-04 | Rohm Co. Ltd. | Semiconductor Device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538452A (en) * | 2014-12-29 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Structure of groove type MOSFET and manufacturing method |
| CN105762193A (en) * | 2016-04-28 | 2016-07-13 | 上海格瑞宝电子有限公司 | MOSFET and preparation method thereof |
| CN107017167A (en) * | 2017-03-01 | 2017-08-04 | 上海华虹宏力半导体制造有限公司 | The manufacture method of trench-gate device with shield grid |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Application publication date: 20130605 |