CN107703878A - A kind of PLC distributed remotes I/O expansion module - Google Patents
A kind of PLC distributed remotes I/O expansion module Download PDFInfo
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- CN107703878A CN107703878A CN201711153979.6A CN201711153979A CN107703878A CN 107703878 A CN107703878 A CN 107703878A CN 201711153979 A CN201711153979 A CN 201711153979A CN 107703878 A CN107703878 A CN 107703878A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25268—PLD programmable logic device
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Abstract
The invention discloses a kind of PLC distributed remotes I/O expansion module, and it includes PLC main frames, some interface modules, some I/O modules.PLC main frames load these interface modules as main website, and each interface module loads a number of I/O module as a slave station, and each interface module is with corresponding I/O module using shared self-defined parallel-expansion bus communication.PLC main frames form distributed I/O expansion structure by interface module and I/O module.PLC master station and interface module shared drive, data are exchanged by fieldbus or real-time ethernet.A region is marked off in the internal memory RAM of PLC master station as shared region shared_RAM, specially with the internal memory shared_DPRAM of each interface module on address space mutual maps mutually.PLC main frame passage time pieces control in turn communications of the shared region shared_RAM from the interface module on different nodes.The extended mode of the present invention improves the ability of PLC host process I/O modules.
Description
The application is Application No. CN201510863641.4, the applying date 2015/11/27, and entitled one kind
The divisional application of the extended method of PLC I/O expansion modules.
Technical field
The present invention relates to a kind of PLC I/O expansions module, more particularly to a kind of PLC distributed remotes I/O expansion module.
Background technology
At present, any a PLC of market sale supports I/O expansion.When the IO deficiencies of main frame, it can pass through
Expansion module/unit increases the processing IO of whole PLC system ability.Extension IO can be done by module, such as siemens
The extension IO of S7_300 series of PLC by module making, interface module, digital quantity input module, digital output module,
Digital quantity input/output module, Analog input mModule, analog output module, analog input and output module and other
Special functional module etc..
Each its interface module of the PLC of brand and extended method are different from, and are related to product vital strategic secrets.As a system
PLC enterprise is made if it is desired to the ability for expanding the PLC processing IO of oneself meets the interface module and IO of its own protocol it is necessary to develop
Module.
The content of the invention
The present invention proposes a kind of PLC distributed remotes I/O expansion module, and its extended mode greatly improves PLC host process
The ability of I/O module.
The present invention is realized using following technical scheme：A kind of PLC distributed remotes I/O expansion module, it include PLC main frames,
Some interface modules, some I/O modules；The PLC main frames are as main website and load these interface modules, and each interface module is made
A number of I/O module is loaded for a slave station, each interface module is self-defined parallel using what is shared with corresponding I/O module
Expansion bus communicates, and the PLC main frames form distributed I/O with some I/O modules by some interface modules and extended
Structure；The PLC master station and some interface module shared drives, data are exchanged by fieldbus or real-time ethernet；
A region is marked off in the internal memory RAM of the PLC master station as shared region shared_RAM, specially with each interface module
Internal memory shared_DPRAM on address space mutual maps mutually；The PLC main frames control shared region by some time piece
The communication in turn of domain shared_RAM and the interface module on different nodes.
As the further improvement of such scheme, the quantity of the I/O module of each interface module loading is by self-defined parallel expansion
The address wire digit for opening up bus determines：2Address wire digit。
As the further improvement of such scheme, each interface module is with the PLC main frames using fieldbus or real-time
Ethernet communication.
As the further improvement of such scheme, PLC main frames are internally interrupted under control, and pipe is carried out by multiple timeslices
Reason control, and switch each interface module in turn.
Further, PLC main frames and each interface module shared drive in a manner of real-time exchange data.
As the further improvement of such scheme, the internal memory shared_DPRAM of each interface module is a dual-port
RAM, communicated by fieldbus or real-time ethernet, the data being stored in internal memory shared_DPRAM, and synchronization map
Into the shared region shared_RAM of PLC main frames region of memory x units；Wherein, x=1,2 ... .N, N are timeslice
Quantity be also shared region shared_RAM memory partitioning number；Internal memory shared_DPRAM divisions in each interface module
Into M region of memory, M is that the slot number of interface module is the maximum quantity that interface module loads I/O module.
Further, each timeslice includes administrative unit phase_period_counter, timer TS_timer, double
Comparator compare_unit；Administrative unit phase_period_counter is the management of a phase, cycle and counter
Unit, phase state or cycle count state are operated in for managing timeslice；Dual comparator compare_unit often connects
Receive an interrupt signal and export two interrupt signals：TS_INT_0 and TS_INT_1；
Administrative unit phase_period_counter receiving phase deviants t_phase, periodic duty time span value
T_period, Synchronization Control clock SYNO, individual pulse signal Load_phase, global enable time piece channel signal
GLOBAL_EN, enabled timer signal Timer_EN, and output phase skew Phase_period_value, timer TS_
Timer resets and restarts timing signal Set_TS_0, loads fiducial value TS_timer_EN, phase offset state activation letter
Number Phase_active；
Timer TS_timer receives the enabled timer signal Timer_EN, the timing signal Set_TS_0, institute
State and load fiducial value TS_timer_EN, and output procedure value TS_timer_value,
Dual comparator compare_unit receives the set-point of the enabled timer signal Timer_EN, two comparators
COMP_value_1 and COMP_value_2, two comparators enabled COMP_EN_1 and COMP_EN_2, the timing signal
Set_TS_0, the loading fiducial value TS_timer_EN, and export two interrupt signals TS_INT_0, TS_INT_1；
Wherein, phase offset state activation signal Phase_active is once activated, timer TS-timer, dual comparator
Comparator_unit will be interrupted；Two interrupt signals TS_INT_0, TS_INT_1 are output to interrupt control unit.
Yet further, phase pushing figure t_phase is Synchronization Control clock SYNO integral multiple, t_phase=n ×
SYNO, the size for representing phase pushing figure t_phase are equal to the length of n Synchronization Control clock pulses；Phase pushing figure t_
Phase be used for correct because thrashing and caused by interrupt signal deviation；Phase pushing figure t_phase is that dynamic changes, and
Before next cycle run time length value t_period arrivals, timing signal Set_TS_0=0, interrupt operation timer
TS_timer, comparator comparator_unit, break period=phase pushing figure t_phase；Periodic duty time span value
T_period is Synchronization Control clock SYNO integral multiple, t_period=m × SYNO, exactly represents periodic duty time span
Value t_period size is equal to the length of m Synchronization Control clock pulses；Periodic duty time span value t_period's
In period, interrupt signal is produced periodically；Periodic duty time span value t_period is that dynamic changes, administrative unit
Phase_period_counter uses new numerical value after terminating in the current cycle of operation；In timing signal Set_TS_0=1
When and timer reset reclocking before new fiducial value exported give dual comparator compare_unit.
Preferably, dispatch of taking turns of the PLC main frames by the management realization to multiple timeslices to these interface modules,
And pass through the length of phase pushing figure t_phase in each timeslice of dynamic regulation so that each timeslice is synchronous, is achieved in
The synchronous operation of each interface module.
More preferably, when first synchronised clock control signal SYNO arrives, global enable time piece channel signal
GLOBAL_EN=1, timer signal Timer_EN=1 is enabled, then administrative unit phase_period_counter is operated in
Period states, output phase skew Phase_period_value is phase pushing figure t_phase, while timing signal Set_
TS_0=1 resets timer TS-timer and counted up since 0；Timing signal Set_TS_0=1 loads fiducial value simultaneously
TS_timer_EN=1, the set-point COMP_value_ of two comparators is loaded before timer TS-timer is started counting up
1st, in COMP_value_2, periodic duty time span value t_period hereafter, timer TS-timer is counted, and works as timer
During TS-timer currency TS_COUNT=COMP_value_1, interrupt signal TS_INT_0 is exported；As timer TS-
During timer currency TS_COUNT=COMP_value_2, interrupt signal TS_INT_1 is exported；
During first periodic duty time span value t_period, system-computed goes out interrupt output because shake needs
X SYNO is offset, when just can guarantee that the interrupt signal of dual comparator compare_unit outputs meets synchronism requirement, the
At the end of a cycle run time length value t_period, global enable time piece channel signal GLOBAL_EN=1, enable
Timer signal Timer_EN=0, individual pulse signal Load_phase=1, then administrative unit phase_period_
Counter is operated in period states, and phase offset Phase_period_value is phase pushing figure t_phase, same to phase
Position shift state activation signal phase_active=1, load fiducial value TS_timer_EN=0, disabling timer TS_timer
With dual comparator compare_unit, timing signal Set_TS_0=1, newest COMP_ is loaded before working condition starts
Value_1, COMP_value_2, in x Synchronization Control clock SYNO hereafter, exported without interrupt signal；
After first periodic duty time span value t_period terminates, second period run time length value t_
Before period starts, global enable time piece channel signal GLOBAL_EN=1, enabled timer signal Timer_EN=1,
Individual pulse signal Load_phase=0, administrative unit phase_period_counter are operated in period states again,
Before new periodic duty time span value t_period starts, newest COMP_value_1, COMP_value_2 are loaded.
In summary, PLC master station realizes that one of method extended is：Without interface module, pass through PLC main frames and each IO
The shared self-defined parallel-expansion bus communication of module, realizes interconnection, has reached extension IO purpose.Without interface module, most
I/O expansion is limited in one's ability greatly, is limited by address/data digit, typically not over 8 I/O modules.PLC master station, which is realized, to expand
The two of the method for exhibition are：PLC I/O expansion is realized by fieldbus or real-time ethernet using interface module.Interface module with
PLC main frames are that fieldbus or real-time ethernet communicate, and interface module is with each I/O module using shared self-defined parallel expansion
Bus communication is opened up, using interface module PLC main frames can be made to realize that distributed I/O extends.
Brief description of the drawings
Fig. 1 is the structural representation of the PLC locals I/O expansion module of the embodiment of the present invention 1.
The structural representation of the PLC distributed remote I/O expansion modules of Fig. 2 embodiment of the present invention 2.
Fig. 3 is the structural representation of Fig. 2 specific refinement.
Fig. 4 is the structural representation of the shared region of PLC main frames in Fig. 3.
Fig. 5 is the structural representation of the internal memory of interface module in Fig. 3.
Fig. 6 is the motion control framework of the ARM kernels with timeslice in Fig. 3.
Fig. 7 is the structural representation of timeslice management in Fig. 6.
Fig. 8 is the refinement structure chart of timeslice management in Fig. 7.
Fig. 9 is the structural representation of timeslice in Fig. 8.
Figure 10 is the signal timing diagram of Fig. 8 timeslice management.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Embodiment 1
Referring to Fig. 1, PLC locals I/O expansion module includes PLC main frames 1, some I/O modules 2.PLC main frames 1 load these
I/O module 2.PLC main frames 1 share self-defined parallel-expansion bus 3 with each I/O module 2, pass through shared self-defined parallel-expansion
Bus 3 communicates and extends IO numbers.The quantity of these I/O modules 2 is determined by the address wire digit of self-defined parallel-expansion bus：2Address wire digit.The quantity of I/O module 2 is also referred to as slot number.
The present embodiment does not have to interface module, total by the shared self-defined parallel-expansion of PLC main frames 1 and each I/O module 2
Line 3 communicates, and realizes interconnection, has reached extension IO purpose.Without interface module, maximum I/O expansion it is limited in one's ability, by address/
The limitation of data bits, typically not over 8 I/O modules.
Embodiment 2
Referring to Fig. 2, the PLC distributed remote I/O expansions module of the present embodiment includes PLC main frames 10, some interface modules
40th, some I/O modules 50.PLC main frames 10 load these interface modules 40 as main website, and each interface module 40 is as a section
Point 20 i.e. slave station loads a number of I/O module 50.Each interface module 40 is with PLC main frames 10 using fieldbus or real-time
Ethernet communication, each interface module 40 are communicated with corresponding I/O module 50 using shared self-defined parallel-expansion bus 30.
PLC main frames 10 form distributed I/O expansion structure by some interface modules 40 and I/O module 50.Each interface module loading
The quantity of I/O module is determined by the address wire digit of self-defined parallel-expansion bus：2 address wire digits.
The present embodiment realizes the I/O expansion of PLC main frames 10 using interface module 40 by fieldbus or real-time ethernet.
Interface module is that fieldbus or real-time ethernet communicate with PLC main frames 10, and interface module uses what is shared with each I/O module
Self-defined parallel-expansion bus 30 communicates.Using interface module PLC main frames 10 can be made to realize that distributed I/O extends.
The I/O expansion of PLC main frames 10, maximum I/O expansion are realized by fieldbus or real-time ethernet using interface module
It is very capable, only by the register capacity of the hardware of PLC main frames 10, the hardware of PLC main frames 10 has great IO abilities, interface
How many I/O module just can be extended for module.
The I/O expansion of PLC main frames 10 is realized by fieldbus or real-time ethernet using interface module, passes through network section
20 are put to extend, an interface module is exactly 1 each node 20, and then interface module determines according to the width of address/data bits
The quantity of I/O module is loaded, this is slot number.One groove installs an I/O module.2 nodes have only been drawn in Fig. 2.Each node=1
The I/O module of individual+8 grooves of interface module.As shown in Fig. 2 address size=3, data bits=12,23=8, so at most may be used
To address 8 grooves, i.e. 8 I/O modules.
The characteristics of the present embodiment 2：
1st, it is of the invention, interface module 40 can be used to realize that PLC main frames 10 expand with the long-range of I/O module 50, distributed I/O
Exhibition；PLC local I/O expansion can also be realized without using interface module 40；
2nd, the interface module 50 that the present invention designs with locally-installed, can extend IO ability with enhancing；
3rd, realize that PLC main frames 10 extend with I/O module 50 using interface module, posting on the hardware of PLC main frames 10 can be played
The maximum IO abilities that storage assigns；
4th, present invention design I/O module 50 can be directly locally-installed with PLC main frames 10, to realize limited I/O expansion energy
Power；
5th, PLC main frames 10 and interface module 40+IO modules.
Concrete methods of realizing concerning embodiments of the invention 2 is described below.
Incorporated by reference to Fig. 3, in PLC main frames 10, mainly there are internal memory RAM, timeslice management, interrupt control, fieldbus or reality
When Ethernet interface.Shared_RAM is the exclusive region divided in PLC internal memories RAM.Interface module mainly has shared_
DPRAM, timeslice management, interrupt control, Switch control, self-defined parallel-expansion EBI, fieldbus or in real time with
Too network interface.There are local dual port memories Local_DPRAM, and local working memory Local_SRAM in I/O module.
PLC main frames 10 and the shared drive of interface module 40, data are exchanged by fieldbus or real-time ethernet 60.PLC
A region is marked off in the internal memory RAM of main frame 10 as shared region shared_RAM, specially with the internal memory of interface module 40
Shared_DPRAM mutual maps mutuallies on address space, as long as ensureing the real-time of communication mechanism, it is possible to ensure PLC main frames 10
Shared_RAM and the uniformity and real-time of the shared_DPRAM data in interface module 40 in internal memory.
The 10 passage time piece management of PLC main frames, control management is interrupted, to control shared_RAM region of memorys and different sections
Interface module 40 on point communicates.I.e. in defined time leaf length, as shown in figure 4, shared_RAM region of memorys one with
The shared_DPRAM in interface module 40 on node one is written and read operation.After the defined time terminates, shared_RAM
Region of memory two is written and read operation with the shared_DPRAM in the interface module 40 on node two.By that analogy.When last
After the read-write operation of one node is completed, system control is returned to the operation to first node.Go round and begin again.
Because the real-time that fieldbus or real-time ethernet 60 communicate is very strong, therefore it ensure that the memory field of PLC main frames 10
Domain shared_RAM and the uniformity and real-time of the shared_DPRAM data in each Node Interface Module 40.
Interface module 40 is both-way communication, on the one hand logical by fieldbus or real-time ethernet 60 and PLC main frames 10
News, on the other hand by being communicated by self-defined parallel-expansion EBI with I/O module 50.The both-way communication of interface module 40
All it is shared drive communication.
Shared_DPRAM in interface module 40 is a two-port RAM, passes through fieldbus or real-time ethernet 60
Communication, the data being stored in shared_DPRAM, in the shared_RAM region of memory x units of synchronization map to PLC.(x
=1,2 ... .N, N timeslice number, and memory partitioning number).
Shared_DPRAM in interface module 40, will be divided into m region of memory, the slot number of m=interface modules=connect
The maximum quantity of mouth mold block carry I/O module.Illustrate, address wire=3bit in self-defined parallel-expansion bus, then interface module
40 slot number=23=8, the interface module 40 at most can be with 8 I/O modules 50 of carry.Shared_ in interface module 40
DPRAM division M region of memory successively with the dual port memories Local_DPRAM in the I/O module 50 on corresponding groove number one by one
It is corresponding, mutually mapping.I.e.：The Local_DPRAM mono- in I/O module 50 on shared_DPRAM region of memory M and groove M
One correspondence, and mutual maps mutually.Data be it is reciprocity, as shown in Figure 5.
M region of memory of the shared_DPRAM divisions in interface module 40, under CPU (MCU) control, by interior
The self-defined parallel-expansion EBI in portion communicates with I/O module 50 successively respectively, and self-defined parallel-expansion EBI only has one
It is individual, in order to allow Local_DPRAM in I/O module in time, it is corresponding with the shared_DPRAM in interface module exactly in
Mapping of field data are deposited, there is Switch control unit inside interface module, carry out switch data passage.I.e.：In CPU (MCU) control
Under system, interface module is using timeslice management, interruption control, the number of timely switching switch unit in predetermined time interval
According to passage, with ensure M region of memory in shared_DPRAM in time, exactly with the Local_ in corresponding I/O module
DPRAM exchanges data.
I/O module 50 is arranged on the notch of interface module 40, and the electronics that each I/O module 50 is described oneself attribute is set
Standby file, the physical installation of I/O module 50 are finished, it is necessary to configure these I/O modules 50 in the hardware management software of PLC main frames 10
Electronic device file, the PLC main frames 10 and I/O module 50 configured is exactly a PLC network, and it is exactly PLC network that it, which configures that part,
Hardware information.Hardware information is will be by the hardware management software download of PLC main frames 10 into the flash of PLC main frames 10.PLC
Network hardware information can be resided in the flash of PLC main frames 10, and power-off is not affected, and re-power automatic loading hardware information.
The PLC network configured, it is impossible to arbitrarily change model, quantity, the location order of I/O module 50, otherwise PLC main frames
10 will be unable to identify.If changed it is necessary to reconfigure PLC network hardware information, and it is downloaded to PLC main frames 10
In flash.
There are a local dual port memories Local_DPRAM, Local_DPRAM to latch live IO information in I/O module 50.
And by internal custom parallel-expansion bus with the corresponding region of memory in interface module 40shared_DPRAM in time,
Data are exchanged exactly.In I/O module 50 also have a local SRAM, be I/O module 50 working memory, the live IO after sampling
Information is just kept in sram, and is remained under latch signal in Local_DPRAM.
I/O module 50 judges whether the information from interface module 40 is directed to oneself by address wire, if for certainly
Oneself, then I/O module 50 exchanges data with 40 corresponding region of memory of interface module.Other I/O modules 50 wait.Timeslice and in
Under the management of disconnected control, each I/O module 50 has equal opportunity to be communicated with interface module 40.
Further illustrate, these timeslices can use the motion control framework (only motion control is relevant) of ARM kernels, such as scheme
Shown in 6.ARM kernels, communicated by AHB_Master in instruction buffer I-CACHE, address caching D_CACHE and piece.By right
The communication in turn from the interface module on different nodes is realized in the management of multiple timeslices, and passes through each timeslice of dynamic regulation
Interior phase pushing figure t_phase length so that each timeslice is synchronous, is achieved in the synchronous fortune of each interface module 40
OK.Although the present embodiment by taking ARM kernels as an example, is not limited to ARM kernels, go for MIPS kernels CPU, × 86 kernel
CPU etc..
In figure 6, management, timeslice are managed by respective AHB interface to driver when interrupting control unit, operation
Port controlling _ PLL and driver port MAC+PHY are controlled.
Driver port MAC+PHY exports driver connected port, such as RJ45.Interrupt control unit, operation when management, when
Between piece management, driver port controlling _ PLL and driver port MAC+PHY by respective AHB interface through AHB_IF turn
Change, communicated with AHB_Master.
As shown in fig. 7, timeslice management strategy, each timeslice passage time piece AHB_ interface units are double with AHB_BUS
To communication, each timeslice each exports two interruptions, timeslice _ 0 and timeslice _ 1.Interrupt signal is uniformly transported to interruption control
In bus processed, by interruption control unit United Dispatching.
The quantity of timeslice is the quantity tight association according to process, and motion controller can carry several axles, it is necessary to
Several timeslices.Motion control core program is exactly that timeslice interrupt routine _ n is performed within the time as defined in timeslice, control
Drive the rotation of the number of axle.Timeslice sum=1+ motion controllers carry the quantity of axle.
Such as CNC System from Siemens Sinumerik NCU730.3, the maximum controllable number of axle 31, then time of motion control
Piece quantity=31+1=32.There is a timeslice to run motion control core program, be not involved in the wheel of the control driving number of axle
Turn.In the figure 7, n --- timeslice quantity.Figure after Fig. 7 refinements is as shown in Figure 8.
In fig. 8, driver port controlling and driver port controlling _ PLL, in dotted line frame=time blade unit, the time
Piece passage, n, its Synchronization Control clock come from driver port controlling _ PLL, manage during operation, driver port controlling it is same
Step control clock comes from driver port controlling _ PLL.
TS_INT_00、TS_INT_01：TS=Time Slice abridge, as follows；INT=Interrupt abridges, below
Together.No. 0 interruption of TS_INT_00=timeslices 0, No. 1 interruption of TS_INT_01=timeslices 0.It is as follows.
TSM=Time Slice Management, timeslice management abbreviation INT_TSM0=interrupt control _ timeslice 0,
Interrupt in control unit, the interruption control management to No. 0 passage of timeslice.It is as follows.
It is all：It is all logical to be managed during operation, interrupt control management, driver port controlling and driver port controlling _ PLL
Corresponding AHB-IF interface units are crossed, management controls time blade unit.
Referring to Fig. 9, single time chip architecture is：Each timeslice=administrative unit phase_period_
Counter, timer TS_timer, dual comparator compare_unit, this is one of characteristic of the present invention, with the current time
Piece is different.
In fig.9, phase_period_counter：It is the administrative unit of a phase, cycle and counter, for managing
Reason timeslice is operated in phase state or cycle count state.
Comparator_unit:It is a dual comparator, each comparator exports an interrupt signal, and dual comparator is defeated
Go out two interrupt signals：TS_INT_0 and TS_INT_1.
SYNO：Synchronization Control clock, from driver port controlling _ PLL, purposes：For the defeated of synchronous all timeslices
Go out.This is also one of characteristic of the present invention, and multiple timeslices can be used to carry out effectively management and control, reach having for the present invention
Beneficial effect.
GLOBAL_EN：Global enable time piece passage, GLOBAL_EN='1', institute is enabled sometimes while initialization
Between piece passage.GLOBAL_EN=0, all isochronous surfaces are resetted, but retain the value of the registers such as phase, cycle.
Phase:It is same to phase_period_counter administrative unit input phase deviants t_phase, t_phase
Step control clock SYNO integral multiple, such as t_phase=3 × SYNO, the size for exactly representing phase value are equal to 3 synchronous controls
The length of clock pulses processed.Phase pushing figure be used for correct because thrashing and caused by interrupt signal deviation, i.e., artificially increase
Add a field offset amount, so as to artificially manufacture interrupt output skew, so as to be that output interrupt signal meets synchronous require.Phase is inclined
Shifting value t_phase is that dynamic changes, and has, is how many all by software again without phase pushing figure t_phase, t_phase value
It is automatic to calculate, and before next t_period arrivals, Set_TS_0=0, interrupt operation timer timer TS-timer,
Comparator Comparator_unit, break period=t_phase.This is also one of characteristic of the present invention, and the present invention is run
It is crucial.
Period:Periodic duty time span value t_period is inputted to phase_period_counter administrative units,
T_period is Synchronization Control clock SYNO integral multiple, such as t_period=9 × SYNO, exactly represents the size of phase value
The length of equal to m=9 Synchronization Control clock pulses.For periodic duty, within the t_period periods, in producing periodically
Break signal.T_period is that dynamic changes, and is calculated automatically by software, and Phase_Period_Counter can be in current operation week
Phase terminates (Phase_Period_Counter passes through dead-center position) uses new numerical value afterwards.When Set_TS_0=1 simultaneously
And timer resets reclocking and new fiducial value is exported to comparator unit before.This is also one of characteristic of the present invention,
It is the key that the present invention is run.
Load_phase：Individual pulse signal, activate Phase_active so that phase_period_counter is managed
Cell operation is in Phase states.
Timer_EN：Enabled timer.
Phase_period_value：The phase offset t_Phase of phase_period_counter administrative units output
Or timing cycle setting value t_period.
TS_timer_value：The timer procedure value of timer TS_TIMER outputs.
COMP_value_1、COMP_value_2：To the set-point 1 and set-point 2 of comparator input, set-point 1/2 is
Dynamic change, in each t_period, software can all calculate new fiducial value automatically, then TS_timer_EN=1 when
Wait and load new fiducial value.This is also one of characteristic of the present invention.
COMP_EN_1、COMP_EN_2：Comparator 1 is enabled, comparator 2 is enabled, for producing interrupt signal 1, interrupting letter
Numbers 2.
Phase_active：Phase offset state activation, once activation, timer TS-timer, comparator
Comparator_unit will be interrupted.
TS_timer_EN：Comparator Comparator_unit is enabled, and loads fiducial value COMP_value_1, COMP_
value_2。
Set_TS_0：Timer TS-timer resets and restarts timing.
TS_INT_0、TS_INT_1：Timeslice administrative unit is output to interrupt signal 0, the interrupt signal of interrupt control unit
1。
Management applied to some timeslices and the control method of the present invention is illustrated incorporated by reference to Fig. 8, Figure 10.
In Figure 10, from left to right, when first synchronised clock control signal SYNO arrives, GLOBAL_EN=1, Timer_EN=1,
Phase_period_counter administrative units are operated in period states, output：Phase_period_value is t_
Period (t_period=9 × SYNO in figure) while Set_TS_0=1 enable timer TS-timer, timer is reset simultaneously
Counted up since 0, Set_TS_0=1 while TS_timer_EN=1, fiducial value is loaded before timer starts counting up
COMP_value_1, COMP_value_2, in t_period hereafter, timer count, as the currency TS_ of timer
During COUNT=COMP_value_1, TS_INT_0 is exported.
As the currency TS_COUNT=COMP_value_2 of timer, TS_INT_1 is exported.
In the process system calculate automatically COMP_value_1, COMP_value_2 of next cycle, t_period,
t_phase。
During first t_period, system-computed goes out interrupt output because shake needs to offset 3 SYNO, ability
Ensure that the interrupt signal of comparator output meets synchronism requirement.Therefore, (the timer TS- at the end of first t_period
Timer obtains maximum), GLOBAL_EN=1, Timer_EN=0, Load_phase=1, phase_period_counter
Administrative unit is operated in phase states, and Phase_period_value is t_phase (t_phase=3 × SYNO in figure), together
When phase_active=1, TS_timer_EN=0, disable timer and comparator, Set_TS_0=1, open in phase states
Newest COMP_value_1, COMP_value_2 are loaded before beginning, in 3 SYNO hereafter, without interrupt output.
After t_phase terminates, before second t_period starts, GLOBAL_EN=1, Timer_EN=1, Load_
Phase=0, phase_period_counter administrative unit are operated in period states again, start in new t_period
Before, newest COMP_value_1, COMP_value_2 are loaded, herein below is the same as first t_period.
Therefore, there are shared_DPRAM, timeslice management in interface module 40, interrupt control, be Switch control, self-defined
Parallel-expansion EBI, fieldbus or real-time ethernet interface.In the case where interrupting control, passage time piece management is controlled and taken turns
Stream switching shared_DPRAM regions exchange data with I/O module 30.The present invention is also equipped with real-time：Counted automatically in each cycle
Calculate, adjust automatically phase pushing figure t_phase.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement made within refreshing and principle etc., should be included in the scope of the protection.
Claims (10)
- A kind of 1. PLC distributed remotes I/O expansion module, it is characterised in that：It includes PLC main frames, some interface modules, some I/O module；The PLC main frames load these interface modules as main website, and each interface module loads a fixed number as a slave station The I/O module of amount, each interface module is with corresponding I/O module using shared self-defined parallel-expansion bus communication, the PLC Main frame forms distributed I/O expansion structure by some interface modules and some I/O modules；It is characterized in that：The PLC master station and some interface module shared drives, data are exchanged by fieldbus or real-time ethernet；Institute State and a region marked off in the internal memory RAM of PLC master station as shared region shared_RAM, specially with each interface module Internal memory shared_DPRAM mutual maps mutuallies on address space；The PLC main frames control shared region by some time piece The communication in turn of shared_RAM and the interface module on different nodes.
- 2. PLC distributed remotes I/O expansion module as claimed in claim 1, it is characterised in that：Each interface module loading The quantity of I/O module is determined by the address wire digit of self-defined parallel-expansion bus：2Address wire digit。
- 3. PLC distributed remotes I/O expansion module as claimed in claim 1, it is characterised in that：Each interface module with it is described PLC main frames are communicated using fieldbus or real-time ethernet.
- 4. PLC distributed remotes I/O expansion module as claimed in claim 1, it is characterised in that：PLC main frames internally interrupt control Under system, control is managed by multiple timeslices, and switch each interface module in turn.
- 5. PLC distributed remotes I/O expansion module as claimed in claim 4, it is characterised in that：PLC main frames and each interface mould Block shared drive in a manner of real-time exchange data.
- 6. PLC distributed remotes I/O expansion module as claimed in claim 1, it is characterised in that：The internal memory of each interface module Shared_DPRAM is a two-port RAM, is communicated by fieldbus or real-time ethernet, being stored in internal memory shared_ Data in DPRAM, and synchronization map is into the shared region shared_RAM of PLC main frames region of memory x units；Its In, x=1, the quantity that 2 ... .N, N are timeslice are also shared region shared_RAM memory partitioning number；Each interface module Interior internal memory shared_DPRAM is divided into M region of memory, and M is that the slot number of interface module is that interface module loads I/O module Maximum quantity.
- 7. PLC distributed remotes I/O expansion module as claimed in claim 6, it is characterised in that：Each timeslice includes management Unit phase_period_counter, timer TS_timer, dual comparator compare_unit；Administrative unit phase_ Period_counter is the administrative unit of a phase, cycle and counter, is to be operated in phase shape for managing timeslice State or cycle count state；Dual comparator compare_unit often receives an interrupt signal and exports two interrupt signals：TS_ INT_0 and TS_INT_1；Administrative unit phase_period_counter receiving phase deviants t_phase, periodic duty time span value t_ Period, Synchronization Control clock SYNO, individual pulse signal Load_phase, global enable time piece channel signal GLOBAL_ EN, enabled timer signal Timer_EN, and output phase skew Phase_period_value, timer TS_timer are reset And restart timing signal Set_TS_0, load fiducial value TS_timer_EN, phase offset state activation signal Phase_ active；Timer TS_timer receives the enabled timer signal Timer_EN, the timing signal Set_TS_0, the dress Load fiducial value TS_timer_EN, and output procedure value TS_timer_value,Dual comparator compare_unit receives the set-point of the enabled timer signal Timer_EN, two comparators COMP_value_1 and COMP_value_2, two comparators enabled COMP_EN_1 and COMP_EN_2, the timing signal Set_TS_0, the loading fiducial value TS_timer_EN, and export two interrupt signals TS_INT_0, TS_INT_1；Wherein, phase offset state activation signal Phase_active is once activated, timer TS-timer, dual comparator Comparator_unit will be interrupted；Two interrupt signals TS_INT_0, TS_INT_1 are output to interrupt control unit.
- 8. PLC distributed remotes I/O expansion module as claimed in claim 7, it is characterised in that：Phase pushing figure t_phase is Synchronization Control clock SYNO integral multiple, t_phase=n × SYNO, the size for representing phase pushing figure t_phase are equal to n The length of Synchronization Control clock pulses；Phase pushing figure t_phase be used for correct because thrashing and caused by interrupt signal it is inclined Difference；Phase pushing figure t_phase is that dynamic changes, and arrives it in next cycle run time length value t_period Before, timing signal Set_TS_0=0, interrupt operation timer TS_timer, comparator comparator_unit, the break period =phase pushing figure t_phase；Periodic duty time span value t_period is Synchronization Control clock SYNO integral multiple, t_ Period=m × SYNO, the size for exactly representing periodic duty time span value t_period are equal to m Synchronization Control clock arteries and veins The length of punching；Within periodic duty time span value t_period period, interrupt signal is produced periodically；During periodic duty Between length value t_period be that dynamic changes, administrative unit phase_period_counter can terminate in the current cycle of operation New numerical value is used afterwards；New ratio when timing signal Set_TS_0=1 and before timer clearing reclocking Dual comparator compare_unit is given compared with value output.
- 9. PLC distributed remotes I/O expansion module as claimed in claim 8, it is characterised in that：The PLC main frames pass through to more The dispatch of taking turns to these interface modules is realized in the management of individual timeslice, and passes through phase offset in each timeslice of dynamic regulation Value t_phase length so that each timeslice is synchronous, is achieved in the synchronous operation of each interface module.
- 10. PLC distributed remotes I/O expansion module as claimed in claim 9, it is characterised in that：When first synchronised clock control signal SYNO arrives, global enable time piece channel signal GLOBAL_EN=1, make Can timer signal Timer_EN=1, then administrative unit phase_period_counter be operated in period states, export phase Position skew Phase_period_value is phase pushing figure t_phase, while timing signal Set_TS_0=1 makes timer TS-timer resets and counted up since 0；Timing signal Set_TS_0=1 loads fiducial value TS_timer_EN=1 simultaneously, Set-point COMP_value_1, COMP_value_2 of two comparators are loaded before timer TS-timer is started counting up, Hereafter in periodic duty time span value t_period, timer TS-timer is counted, current as timer TS-timer During value TS_COUNT=COMP_value_1, interrupt signal TS_INT_0 is exported；As timer TS-timer currency TS_ During COUNT=COMP_value_2, interrupt signal TS_INT_1 is exported；During first periodic duty time span value t_period, system-computed goes out interrupt output because shake needs partially X SYNO is moved, when just can guarantee that the interrupt signal of dual comparator compare_unit outputs meets synchronism requirement, at first At the end of periodic duty time span value t_period, global enable time piece channel signal GLOBAL_EN=1, enabled timing Device signal Timer_EN=0, individual pulse signal Load_phase=1, then administrative unit phase_period_counter works Make in period states, phase offset Phase_period_value is phase pushing figure t_phase, while phase offset state Activation signal phase_active=1, fiducial value TS_timer_EN=0 is loaded, disable timer TS_timer and dual comparator Compare_unit, timing signal Set_TS_0=1, load before working condition starts newest COMP_value_1, In COMP_value_2, x Synchronization Control clock SYNO hereafter, exported without interrupt signal；After first periodic duty time span value t_period terminates, second period run time length value t_ Before period starts, global enable time piece channel signal GLOBAL_EN=1, enabled timer signal Timer_EN=1, Individual pulse signal Load_phase=0, administrative unit phase_period_counter are operated in period states again, Before new periodic duty time span value t_period starts, newest COMP_value_1, COMP_value_2 are loaded.
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| CN105511387B (en) | 2018-04-20 |
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