TWI352296B - Chip system and signal transmission method thereof - Google Patents

Chip system and signal transmission method thereof Download PDF

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TWI352296B
TWI352296B TW96129669A TW96129669A TWI352296B TW I352296 B TWI352296 B TW I352296B TW 96129669 A TW96129669 A TW 96129669A TW 96129669 A TW96129669 A TW 96129669A TW I352296 B TWI352296 B TW I352296B
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wafer
signal
slave
packet
mode
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Description

1352296 九、發明說明: 【發明所屬之技術領域】 本發明係關於-種晶片系統’尤指—種根據一專屬串 協定來組成訊號與傳輸訊號的晶^統及其訊號傳 【先前技術】1352296 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer system, in particular, a crystal and a signal transmission of a signal and a transmission signal according to a proprietary string protocol. [Prior Art]

的小型化與整合化係為時下業者與消費者共 =追求的目I —般而言,電子產品係以可程式技術來作 W =制⑼片_體編程’來控制核心控制器晶片的各 個週邊裝置’以_產品的功能要求。以往,核心控制器 =時4工制夕項裝置時’各個裝置的位址線與控制線均須轉 接於核心控制器的接腳,利用不同接腳的控制資源來對各 個裝置作控制或資料存取。由於核心控制器所控制的週邊 功能日益增加,所佔用的控制器接腳資源也隨之增加。為 了解決此-問題’適合短距傳輸的晶片間同步串列通信介 面(Inter-chip synchronous serial c〇m_icati〇n imerface) 從而問世。 =述之同步串列介面包括有數條分別傳送時脈訊號與 串列貝料的傳輸線,核心、控制器與執行週邊功能的從屬晶 $的:關接腳係同時耦接於該些傳輸線,按照個別位址來 完成晶片間的控制功能或資料存取。如此一來,便可大幅 減一主從控制器間的連接線數量。目前,微控制器所泛用 的晶片間同步串列通信介面包括有I2C ( Inter integrated circuit )、SPI ( Serial peripheral interface )與微線介面 (Microwire interface)等三種。 6 i352296 上述二種通信介面中,Pc通信介面係被廣泛採用。 為二線式傳輪’包括-串列f料線(SeHd. data line,咖), 以及一串列時脈線(Serial ciock line,SCL)。依據l2c協定, j2C具有三種速度模式,包括有標準模式(封包傳輪速率 外達100Kbps)、快速模式(封包傳輸速率可達_ 與高速模式(封包傳輸速率可達3 4Mbps)。 有鑑於半導體製程與資料處理技術係日益精進 微處理器與微控制器的資料處理效能也隨之提升 時脈速率亦持續提升’因此’對於晶片 ;;卢 速率要求係更進—步。由於&等現有通信協定是 的時序邏輯達到通訊效果,硬體電路㈣而無 系統時脈傳輸。為了加速主從控制器晶片間控制命令= 輸速率,提升電子產品的效能,因此,本案發明人係提出 本案。本發明係提出訊號傳輸方法與傳輸介面,The miniaturization and integration system is the pursuit of the current industry and consumers. In general, electronic products use programmable technology to make W = system (9) film-body programming to control the core controller chip. Each peripheral device 'has the functional requirements of the product. In the past, when the core controller=time 4 industrial device, the address line and the control line of each device must be transferred to the pins of the core controller, and the control resources of different pins are used to control each device or Data access. As the peripheral functions controlled by the core controller increase, the controller pin resources occupied also increase. In order to solve this problem, an inter-chip synchronous serial c〇m_icati〇n imerface is available. The synchronous serial interface includes a plurality of transmission lines for respectively transmitting the clock signal and the series of baits, and the core, the controller and the slave crystal for performing the peripheral function are: the connection pins are simultaneously coupled to the transmission lines, according to Individual addresses are used to complete control functions or data access between wafers. In this way, the number of connections between the master and slave controllers can be significantly reduced. At present, the inter-chip synchronous serial communication interface widely used by the microcontroller includes three types: an I2C (Inter Integrated Circuit), an SPI (Serial Peripheral Interface), and a Microwire Interface. 6 i352296 Among the above two communication interfaces, the Pc communication interface is widely used. It is a two-line transfer wheel 'includes a series of line lines (SeHd. data line), and a series of serial ciock lines (SCL). According to the l2c agreement, j2C has three speed modes, including standard mode (packet transmission rate up to 100Kbps), fast mode (packet transmission rate up to _ and high speed mode (packet transmission rate up to 34 Mbps). In view of semiconductor manufacturing process The data processing technology and data processing technology are increasingly improving the data processing performance of microprocessors and microcontrollers, and the clock rate is also increasing. Therefore, for the wafer; the rate requirement is more advanced. Because of the existing communication such as & The agreement is that the sequential logic achieves the communication effect, and the hardware circuit (4) has no system clock transmission. In order to speed up the master-slave controller inter-chip control command = transmission rate and improve the performance of the electronic product, the inventor of the present invention proposed the case. The invention proposes a signal transmission method and a transmission interface,

訊框格式(F_ef瞻at)與封包處理流程,使 H 得以快速减與處理,俾使晶以統的傳輪速 = 升。此外,:於封包格式的簡化,使得處理傳送封包二 理封包的硬體設計成本大為降低。 ·^珂匕興處 【發明内容】 因此,本發明之目的係在於提供—種 號傳輸方法’錢由規社控制器晶片與^=訊 專屬串列祕協定組成訊號與傳輸訊號,係可 器晶片與從屬晶片的訊號傳輸速率大幅提升。于工 本發明係揭示-種晶片系統,晶片系統包括— 益晶片、至>-從屬晶片以及一傳輸介面。主控制心片 7 1352296 係產生一時脈訊號,從屬晶片係耦接於至少一具有個別位 * 址之週邊功能裝置,傳輸介面係耦接於主控制器晶片以及 從屬晶片之間。傳輸介面包括有一資料線以及一時脈線, 貧料線係搞接於主控制裔晶片以及從屬晶片之間’時脈線 係耦接於主控制器晶片以及從屬晶片之間,以將時脈訊號 傳輸至從屬晶片。其中主控制器晶片以及從屬晶片係依照 一專屬串列通訊協定組成訊號,並透過資料線雙向傳輸訊 號,以根據週邊功能裝置個別的位址,控制週邊功能裝置 ® 的運作。 所述之主控制器晶片以及該從屬晶片具有個別的封包 處理機制與有限狀態機,主控制器晶片與從屬晶片個別之 封包處理機制與有限狀態機係根據專屬串列通訊協定,控 制主控制器晶片與從屬晶片間之訊號組成格式與訊號傳輸 程序。主控制器晶片與從屬晶片間之訊號傳輸類別包括有 一中斷模式、一寫入模式、一主動讀取模式、一被動讀取 模式、一重置模式以及一喚醒模式。 • 本發明再揭示一種訊號傳輸方法,係適用於所述之晶 片系統中該中斷模式的訊號傳輸。中斷模式之訊號傳輸方 法的步驟係首先,主控制器晶片組成一中斷命令封包;其 次,主控制器晶片將中斷命令封包傳輸至從屬晶片;最後, ' 從屬晶片組成一中斷回應封包傳輸至主控制器晶片,以回 • 應中斷命令封包的接收。 本發明再揭示一種訊號傳輸方法,係適用於所述之晶 片系統中該寫入模式的訊號傳輸。寫入模式之訊號傳輸方 法的步驟係首先,主控制器晶片組成一寫入控制命令封 8 f ’其次’主控制器晶片將寫入控制命令封包傳輸至從屬 B曰片。 本發明再揭示-種訊號傳輸方法,係適用於所述之晶 =統中該线讀取模式的職傳輪。主動讀取模式之訊 方法的步驟係首先,主控制器晶片組成-讀取控制 至物^ ’其〜’主控制器晶片將讀取控制命令封包傳輸 «屬晶片。 片系ίΓ紐揭示—種訊號傳輸方法,麵用於所述之晶 銳傳動讀取模式的訊號傳輪。被動讀取模式之訊 4輪:法的步驟係首先,主控制器晶片組成一中斷命令 片;龙;人…主控制益晶片將中斷命令封包傳輸至從屬晶 晶片二’從屬晶片組成―中斷回應封包傳輪至主控制器 飯成」中斷命令封包的接收;最後,主控制器晶片 應_=彳命令封包傳駐㈣“,㈣應中斷回 j巴的接收。 片系嘵揭不一種訊號傳輸方法,係適用於所述之晶 法的步重置模式之訊號傳輪方 屬晶片.甘^ 拴制态曰曰片組成一重置訊號傳輸至從 本黎^人’主控制器晶片將重置訊號傳輸至從屬晶片。 片系统訊號傳輪方法,係適用於所述之晶 法的步驟伤奐Γ杈式的心虎傳輪。喚醒模式之訊號傳輪方 晶片從屬晶片組成-喚醒訊號;其次,從屬 字奐醒訊號傳輸至主控制 片回復為正常楛…4 片’取後,主控制器晶 :正㈣场作,㈣應於喚醒訊號的接收。 之概述與接下來的詳細說明及附圖,皆是為了能 進一步說明本發明為達成預定目的所採取之方式、手段及 功效。而有關本發明的其他目的及優點,將在後續的說明 及圖式中加以闡述。 【實施方式】 本發明所揭示之晶片系統及其訊號傳輸方法’係規範 主控制器晶片以及週邊從屬晶片根據一專屬串列通訊協定 組成訊號與傳輪訊號,以達成通訊之目的。 首先’請參閱第一圖,該圖係為本發明所揭示晶片系 統10之系統架構示意圖。如第一圖所示,晶片系統10包 括有一主控制器晶片12、複數個從屬晶片141〜14N以及一 傳輸介面16。傳輸介面16包括有一時脈線(Clock line) 162以及一資料線(Data line) 164,主控制器晶片12與從 屬晶片141〜14N係分別連接傳輸介面16之時脈線162以 及資料線164。主控制器晶片12係耦接於一主機(圖中未 示)’所述之主機係作為晶片系統1〇的主要控制核心。舉 例來說,於一電腦系統中,主機係指電腦之中央處理單元, 主控制器晶片12係指中央處理單元週邊之鍵盤控制器,一 般而言,主控制器晶片12常被賦予多種控制功能,而從屬 曰曰片141〜14N可為主控制器晶片12所控制的通用輸出入 蜂擴充晶片、馬達驅動晶片與背米板驅動晶片等。 其中,資料線164係雙向傳輸串列封包訊號。主控制 器晶>1 12與從屬晶片141〜14N根據控制模式來扮演傳送 端與接收端,以發送封包訊號到資料線164,以及從資料 線164接收封包訊號,並對接收到的封包訊號作回應。晶 1352296 片系統H) t,主控制器晶片12係產生—時脈訊號 ,,傳輸。於—具體實施例中,•脈訊號的頻率“ 允控制裔晶片12系統時脈的頻率相同。舉例來說,倘若主 3器晶片U的系統時脈頻率為16MHz,則時脈訊號的 貝罕便為16MHz,而時脈週期約為62 5ns。從而,晶片系 統川的封包訊賴輸料便可提高為㈣雜醉:而^The frame format (F_ef view at) and the packet processing process enable H to be quickly reduced and processed, so that the crystal transfer speed = liter. In addition, the simplification of the packet format greatly reduces the hardware design cost of processing the transport packet. ·^珂匕兴处 [Summary of the Invention] Therefore, the object of the present invention is to provide a method for transmitting a variety of signals, which is composed of a controller and a proprietary protocol. The signal transmission rate of the chip and the slave chip is greatly increased. The present invention discloses a wafer system including a wafer, a >-subordinate wafer, and a transmission interface. The master control chip 7 1352296 generates a clock signal, and the slave chip system is coupled to at least one peripheral function device having an individual address, and the transmission interface is coupled between the main controller chip and the slave wafer. The transmission interface includes a data line and a clock line. The lean line is connected between the main control chip and the slave chip. The clock line is coupled between the main controller chip and the slave chip to connect the clock signal. Transfer to the slave wafer. The main controller chip and the slave chip form a signal according to a dedicated serial communication protocol, and transmit signals bidirectionally through the data line to control the operation of the peripheral function device ® according to the individual address of the peripheral function device. The main controller chip and the slave wafer have separate packet processing mechanisms and finite state machines, and the individual controller chip and the slave chip individually process the packet processing mechanism and the finite state machine according to the exclusive serial communication protocol to control the main controller. The signal between the chip and the slave wafer forms a format and a signal transmission program. The signal transmission category between the master controller chip and the slave chip includes an interrupt mode, a write mode, an active read mode, a passive read mode, a reset mode, and an awake mode. The present invention further discloses a signal transmission method suitable for signal transmission of the interrupt mode in the wafer system. The step of the signal transmission method of the interrupt mode is first, the main controller chip forms an interrupt command packet; secondly, the main controller chip transmits the interrupt command packet to the slave wafer; finally, the 'slave chip constitutes an interrupt response packet transmission to the main control The chip is back to the reception of the interrupted command packet. The invention further discloses a signal transmission method suitable for signal transmission in the write mode in the wafer system. The step of the signal transmission method of the write mode is first, the main controller chip is composed of a write control command block 8 f ' secondly, the main controller chip transfers the write control command packet to the slave B slice. The invention further discloses a signal transmission method, which is suitable for the job transmission wheel of the line reading mode in the crystal system. The method of actively reading the mode is the first step of the main controller chip composition-read control to the object ^'the main controller chip will read the control command packet transmission «the genus wafer. The film system 揭示 揭示 reveals a signal transmission method for the signal transmission of the crystal sharp drive read mode. Passive read mode signal 4 rounds: the steps of the method are first, the main controller chip constitutes an interrupt command piece; the dragon; the person... the main control benefit chip transmits the interrupt command packet to the slave crystal chip two 'subordinate wafers' interrupt response The packet transmission to the main controller "Oi Cheng" interrupts the reception of the packet; finally, the main controller chip should be _=彳 command packet relay (4) ", (4) should be interrupted back to j bar reception. The film system does not reveal a signal transmission The method is applied to the step-reset mode of the crystal method of the signal transfer wheel. The ^ 拴 拴 曰曰 组成 组成 组成 组成 组成 组成 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置The signal transmission to the slave chip. The chip system signal transmission method is applied to the step of the crystal method, the scar-type heart-shaped wheel. The wake-up mode signal-transmitting chip-side slave wafer-waking signal; Secondly, the subordinate word awake signal is transmitted to the main control piece and returned to normal 楛...4 pieces 'after the main controller crystal: positive (four) field, (4) should be received by the wake-up signal. The summary and the following detailed description and Drawings, both Other objects and advantages of the present invention will be described in the following description and drawings in order to explain the present invention. The chip system and its signal transmission method 'is a specification of the main controller chip and the peripheral slave chip to form a signal and a transmission signal according to a dedicated serial communication protocol for the purpose of communication. First, please refer to the first figure, which is A schematic diagram of the system architecture of the wafer system 10 disclosed herein. As shown in the first figure, the wafer system 10 includes a main controller wafer 12, a plurality of slave wafers 141~14N, and a transmission interface 16. The transmission interface 16 includes a clock. A clock line 162 and a data line 164, the main controller chip 12 and the slave chips 141 to 14N are respectively connected to the clock line 162 of the transmission interface 16 and the data line 164. The main controller chip 12 is coupled. The host system connected to a host (not shown) is used as the main control core of the wafer system. For example, In the system, the host refers to the central processing unit of the computer, and the main controller chip 12 refers to the keyboard controller around the central processing unit. Generally, the main controller chip 12 is often given various control functions, and the subordinate 141 ~14N can be a general-purpose output into the bee expansion chip, the motor drive chip and the backplane drive chip controlled by the main controller chip 12. Among them, the data line 164 is a bidirectional transmission serial packet signal. The main controller crystal > 12 and slave chips 141~14N play the transmitting end and the receiving end according to the control mode, send the packet signal to the data line 164, and receive the packet signal from the data line 164, and respond to the received packet signal. Crystal 1352296 chip system H) t, the main controller chip 12 generates a clock signal, and transmits. In the specific embodiment, the frequency of the pulse signal "allows the frequency of the 12 system clocks of the control chip to be the same. For example, if the system clock frequency of the main chip U is 16 MHz, the clock signal of the Bahan It is 16MHz, and the clock cycle is about 62 5ns. Thus, the wafer system's packet information can be improved to (4) drunk: and ^

控制器晶片12與從屬晶片141〜14N之間的控制便得 形流暢與迅速。 —主控制器晶#12與從屬晶4 141〜14N内部均具 《引擎(Protocol engine)。所述之協定引擎係由配人 =源所共同構成’並根據一專屬串列通信協定的: 1封包的編、解碼,將晶片内部的命令訊號組成封 匕訊號,及將接收到的封包訊號處理轉換為晶片内部的命The control between the controller wafer 12 and the slave wafers 141 to 14N is smooth and rapid. - The main controller crystal #12 and the slave crystals 4 141 to 14N each have a "protocol engine". The agreement engine is composed of the matching source=source and is based on a proprietary serial communication protocol: 1 packet encoding and decoding, the command signal inside the chip is composed of the sealing signal, and the received packet signal is received. Processing is converted to the inside of the wafer

主控制器晶月12與每-從屬晶片141〜14N具有個別 ,封包處理機制與有限狀態機(Fimte _臟―觀) 來根據此專屬串列通信協定_序邏輯,控制主控制器晶 m與從屬晶片141〜刚按照財的訊框格式組成訊號 :、傳輸訊號。從屬晶片141〜14N分顺接並控制一或多個 週邊功能裝置,每一週邊功能裝置具有個別的位址 测峨),主控制器晶片12係'對各個從屬晶片141〜14N =各個週邊功能裝置定址,以便辨識封包訊號的正確來 源,與確保封包訊號送達正確目的地。 的片系統10中,主控制态晶片丨2與從屬晶片141〜14N 間的訊號傳輸類別包括有中斷模式、寫入模式、主動讀取 11 1352296 模式、被動讀取模式、重置模式與喚醒模式,其中主動讀 取模式為主控制器晶片12主動對從屬晶片141〜14N作讀 取動作;而被動讀取模式則是由從屬晶片141〜14N對主控 制器晶片12發送中斷要求,再由主控制器晶片12對從屬 晶片14卜HN作讀取,或由從屬晶片141〜14N直接對主控 制器晶片12作讀取。 以下便逐一介紹本發明之各種封包訊號格式。主控制 器晶片12所組成訊號的類別包括有中斷命令封包以及控 制命令封包。藉以對從屬晶片141〜14N及其個別所耦接之 週邊功能裝置下達中斷及讀寫控制。 請參閱弟一圖’該圖係為主控制器晶片12端之控制命 令封包200之結構示意圖。如第二圖所示,控制命令封包 200為20位元。控制命令封包200包括有一起始位元(;Start bit) 210、一結束位元(End bit) 250 以及三攔位 220、230、 240。其中’起始位元210與結束位元250分別位於控制命 令封包200的第一位元與第二十位元,用以識別控制命令 封包200的完整性。欄位220為命令攔,以2位元來表示 控制模式為主動項取模式或為寫入模式。於一具體實施 例’欄位220為01表示控制命令封包2〇〇為一讀取控制命 令封包,欄位220為10表示控制命令封包2〇〇為一寫入^ 制命令封包。欄位230為位址攔,以8位元來表示接受封 包訊號之目的地位址。欄位240為資料欄,以8位元^填 入控制命令資料。 ' 請參閱第三圖,該圖係為主控制器晶片12端的中斷命 令封包300結構示意圖。如第三圖所示,中斷命令封包%P〇 12 1352296 為12位元。中斷命令封包3〇〇包括有一起始位元一 結束位元340以及二攔位320、33〇。其中,起始位元、3 = 與結束位元340分別位於中斷命令封包3〇〇的第—位元與 第忙位元,用錢财斷命令封包·的完整性。· 320係為命令攔’攔位32〇 ^ 2位元,用以定義控制 為中斷模式。於-具體實施例’攔位32◦為〇〇即表示此^ 包係作中斷控制。欄位330為位址攔,以8位元來表示中 斷命令封包300的目的地位址。附帶一提的是,此中^命 令封包3 00的訊框格式亦可彈性作為主控制器晶片丨2對= 有從屬晶片141〜14N下達系統命令的訊框格式。若是將搁 位320為00解釋為系統命令,則攔位33〇則轉變為系統命 從屬晶片141〜14Ν所組成的訊號類別包括有中斷回廡 封包與命令回應封包等訊號格式,以回應主控制器晶片& 所下達的讀寫控制命令與中斷命令。請參閱第四圖,該圖 係為從屬晶片的命令回應封包4〇〇結構示意圖。如第四圖 所示,命令回應封包4〇〇為ίο位元。命令回應封包4〇〇 ^ 括有一起始位元410、一結束位元43〇以及—攔位42〇。起 始位元410與結束位元430分別位於命令回應封包4〇〇的 第〆位元與第十位元,用以識別命令回應封包4〇〇的完整 性,而欄位42〇為資料攔,以8位元來填入資料。 請參閱第五圖,邊圖係為從屬晶片的中斷回應封包 5〇〇之、结構示思圖。如第五圖所示,中斷回應封包500為 1〇位元。中斷回應封包500包括有一起始位元510、一結 束位元53〇以及一攔位520。起始位元510與結束位元53〇 13 分別位於中斷回應封包500的笛一a _ t 識別中斷回應封包500的完‘ = 十位元’用以 屬日日片可具有八個週邊功能襄置。攔位520中每-位元 _,7係代表-特定週邊功能裂置的中斷值二: 裝置的中斷狀態。 .肩不 以下便逐一說明本發明之 ^ Μ 讯唬傳輸方法的中斷模式、 寫入杈式、主動項取模式、被 醒模式之步誠程。軸轉以、重置模式及喚 第一、中斷模式: 請參閱第六圖’該圖係為晶片系統 驟流程圖。其中相關之系統架構請同時來閱第圖二步 示,該方法係始於主控制⑨θ /^代表“。如第六圖所 著’便根據欲進行中斷控制之週邊::=: :02)。接 中斷命令封包(步驟S6G4) ^^置㈣’組成一 控制此欲情之週邊功能F ^此巾斷命令封包傳輸到 _。從屬晶片根據^屬W 14 (步驟 中斷回應封包傳輸至主控制器a 7、的中斷值,組成-包的接收(步驟S608)。苴後 12 ’以回應中斷命令封 置狀態(步驟S600)。〃 才空制器晶片12再回到閒 第一、寫入权式: 請參閱第七圖,該圖係為曰 驟流程圖。如第七圖所示,:^ 統10之寫入模式之步 於閒置狀態(步驟S700)時"/係始於主控制器晶片12 守基於韌體的控制,產 馬 ς需求(步驟S702)。接著,便根據欲寫入之週邊功能裝 立址,組成一寫入控制命令封包(步驟S704),並將此 .入控制命令封包傳輸到從屬晶片步驟S706)。其後, 主控制器晶片12再回到閒置狀態(步驟S7〇〇)。'、 12組成寫人控制命令封包傳輸至 仗屬曰日片Μ前,將根據中斷模式的步驟流程,對欲寫 ==裝置作中斷控制’以根據控制此週 ==覆的中斷回應封包,決定是否組成寫入控制 °Ρ·7封包傳輸至從屬晶片14。 第三、主動讀取模式: 之:ΪΓ八圖’該圖係為晶片系統10之主動讀取模式 之步驟流程圖。如第八圖所示,首先,主控制哭曰片12 於閒置狀態(步驟sη士 子工利口口日日片12 取需长、 基靭體的控制,產生一讀 取而承C步驟S802 )。接箬,φ批生,丨M A u 取之週邊功能妒置位 "為日曰片12便根據欲讀 S80d脸f置 成一讀取控制命令封包(步驟 並將此頃取控制命令封包傳輸到從屬曰片14 (^牛 驟S806)。其後,你遛曰μ号韧刿攸屬日曰片Η (步 斷是否須回應讀取㈣1八 讀取控制命令封包,判 若步驟S8〇f6工°卩7封包的接收(步驟S808 )。倘 片12進入二?為:’則回到步驟S_,主控制器晶 晶片14組成—命:回:::驟_的判斷為* ’則從屬 驟漏)。其後,12(步 S8〇〇)〇 TJ〇°日曰片12再進入閒置狀態(步驟 從屬晶片14 曰片12組成讀寫控制命令封包傳輸至 剛’:艮據中斷模式的步驟流程,對欲讀取之 1352296 週邊功能裝置作中斷控制, 從屬晶片所回覆的中斷回鹿封勺控制此週邊功能裝置之 命令封包傳輸至從屬晶片二、广’決定是否組成讀 取控制 第四、被動讀取模式: 被動讀取模式為從屬晶The main controller crystal 12 and each of the slave chips 141 to 14N have individual, packet processing mechanisms and finite state machines (Fimte_dirty-view) to control the main controller crystal m and according to the exclusive serial communication protocol The slave chip 141~ has just formed a signal: a transmission signal according to the frame format of the money. The slave chips 141 to 14N are sequentially connected and control one or more peripheral function devices, each of the peripheral function devices has an individual address measurement, and the master controller chip 12 is 'for each of the slave chips 141 to 14N=each peripheral function The device is addressed to identify the correct source of the packet signal and to ensure that the packet signal is delivered to the correct destination. In the chip system 10, the signal transmission categories between the main control state chip 丨2 and the slave chips 141~14N include an interrupt mode, a write mode, an active read 11 1352296 mode, a passive read mode, a reset mode, and an awake mode. The active read mode is that the master controller chip 12 actively performs read operations on the slave chips 141 to 14N; and the passive read mode is that the slave chips 141 14 14N send interrupt requests to the master controller chip 12, and then the master The controller wafer 12 reads the slave wafer 14 HN or directly reads the master controller wafer 12 from the slave wafers 141 14 14N. The various packet signal formats of the present invention are described below. The categories of signals composed by the main controller chip 12 include interrupt command packets and control command packets. Interrupt and read/write control is performed on the slave peripheral devices 141 to 14N and their respective peripheral functional devices. Please refer to the figure of the younger one. This figure is a schematic diagram of the control command packet 200 of the terminal 12 of the main controller. As shown in the second figure, the control command packet 200 is 20 bits. Control command packet 200 includes a start bit 210, an end bit 250, and three bays 220, 230, 240. Wherein the start bit 210 and the end bit 250 are respectively located in the first bit and the twentieth of the control command packet 200 for identifying the integrity of the control command packet 200. Field 220 is a command bar, which is represented by 2 bits. The control mode is the active item fetch mode or the write mode. In a specific embodiment, the field 220 is 01 to indicate that the control command packet 2 is a read control command packet, and the field 220 is 10 to indicate that the control command packet 2 is a write command packet. Field 230 is the address block, and the destination address of the packet signal is represented by 8 bits. Field 240 is a data column, and the control command data is filled in by octet ^. Please refer to the third figure, which is a schematic diagram of the structure of the interrupt command packet 300 on the 12th end of the main controller chip. As shown in the third figure, the interrupt command packet %P〇 12 1352296 is 12 bits. The interrupt command packet 3 includes a start bit one end bit 340 and two stop bits 320, 33. The start bit, 3 = and the end bit 340 are respectively located in the first bit and the busy bit of the interrupt command packet 3, and the integrity of the packet is blocked by the money. · The 320 series is the command blocker's 32 〇 ^ 2 bits to define the control to interrupt mode. In the embodiment, the block 32 is 〇〇, indicating that the packet is interrupted. Field 330 is the address block, and the destination address of the interrupt command packet 300 is represented by 8 bits. Incidentally, the frame format of the packet 3 00 can also be flexibly used as the main controller chip 丨 2 pair = the slave frame 141 〜 14N issues the frame format of the system command. If the position 320 is interpreted as a system command, the block 33〇 is converted into a system-dependent slave chip 141~14. The signal type consisting of an interrupt reply packet and a command response packet is in response to the main control. Read and write control commands and interrupt commands issued by the chip & Please refer to the fourth figure, which is a schematic diagram of the command response packet of the slave wafer. As shown in the fourth figure, the command response packet 4 is ίο bit. The command response packet 4〇〇 includes a start bit 410, an end bit 43〇, and a block 42〇. The start bit 410 and the end bit 430 are respectively located at the third bit and the tenth bit of the command response packet 4, for identifying the integrity of the command response packet 4, and the field 42 is the data block. , fill in the information with 8 bits. Please refer to the fifth figure. The side view is the interrupt response packet of the slave chip. As shown in the fifth figure, the interrupt response packet 500 is one bit. The interrupt response packet 500 includes a start bit 510, a stop bit 53A, and a block 520. The start bit 510 and the end bit 53〇13 are respectively located in the interrupt response packet 500, and the end of the interrupt response packet 500 is completed == tens place for the genus day slice to have eight peripheral functions. Set. Each bit in the block 520 _, 7 represents the interrupt value of the specific peripheral function split 2: the interrupt status of the device. The shoulders are not described below, and the interrupt mode, the write mode, the active item fetch mode, and the wake mode of the method of the transmission method of the present invention are explained one by one. Axis turn, reset mode and call first, interrupt mode: Please refer to the sixth figure' This figure is the wafer system flow chart. For the related system architecture, please refer to the second step of the figure. The method starts from the main control 9θ /^ stands for “. As shown in the sixth figure, it is based on the periphery of the interrupt control::=: :02) Connect the interrupt command packet (step S6G4) ^^ set (four) 'compose a control peripheral function F ^ This wipes the command packet transmission to _. The slave wafer is transmitted according to the genus W 14 (step interrupt response packet transmission to the main controller a 7. Interrupt value, composition-packet reception (step S608). After 12' in response to the interrupt command sealing state (step S600). 才 The air conditioner chip 12 is returned to the idle first, write right For the following figure, please refer to the seventh figure, which is a flowchart. As shown in the seventh figure, when the write mode of the system 10 is in the idle state (step S700), the "/ begins with the main control. The firmware of the firmware 12 is based on the control of the firmware, and the production is required (step S702). Then, according to the peripheral function to be written, a write control command packet is formed (step S704), and the input is made. The control command packet is transferred to the slave wafer step S706). Thereafter, the master controller chip 12 Return to the idle state (step S7〇〇). ', 12 constitutes the writer control command packet transmission to the 曰 曰 Μ , , , , , , , , , , , , 根据 根据 根据 根据 根据 根据 根据 根据 根据The interrupt response packet of this week == is controlled, and it is determined whether or not the composition of the write control is transmitted to the slave wafer 14. Third, the active read mode: This is the image of the wafer system 10 The flow chart of the steps of the active reading mode. As shown in the eighth figure, firstly, the main control crying film 12 is in an idle state (step sη士子工利口日日片12 take-up length, base firmware control, generate A read and take C step S802). Then, φ batch, 丨MA u take the peripheral function 妒 set " for the 曰 曰 12 will be set according to the S80d face f to read a control command packet (step And transfer this control command packet to the slave 14 14 (^牛骤S806). After that, you 遛曰μ 刿攸 刿攸 刿攸 Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η The command packet is judged to be received by the step S8 〇 f6 卩 7 packets (step S808). The slice 12 enters two? as: 'When returning to step S_, the main controller crystal chip 14 is composed - life: back::: the judgment of the _ is * 'the sub-sliding leak.) Thereafter, 12 (step S8 〇〇 〇TJ〇°曰片12 re-enters the idle state (step slave sub-chip 14 曰片12 constitutes read-write control command packet transmission to just ': step according to the interrupt mode, for the 1352296 peripheral function device to be read Interrupt control, interrupted by the slave wafer, returning to the deer sealing spoon to control the peripheral function device's command packet transmission to the slave chip. 2. Wide decision to determine whether to form the read control. Fourth, passive read mode: Passive read mode is slave crystal

來之中斷命令封包後,組成—巾^收到主控制器晶片傳 回應封包傳輸至主控制器晶片丨,回應封包,並將此中斷 根據中斷回應封包的内容:主二J著:主控制器晶片12 求封包的狀;其後,從屬晶以回應中斷要 L 命令封包的接收,組成—命令回 應封包傳輸至主控制器晶片12。 第五:重置模式: 本發明所揭示之專屬串列通訊協定係定義了主控制哭 晶片12對所有從屬晶片H1〜MN的重置(Rese〇控制了After the interrupt command packet is received, the component-towel ^ receives the main controller chip transmission response packet transmission to the main controller chip, responds to the packet, and responds to the interrupt according to the contents of the interrupt packet: the master 2: the main controller The wafer 12 is in the form of a packet; thereafter, the slave crystal responds to the receipt of the interrupt L command packet, and the component response command packet is transmitted to the main controller chip 12. Fifth: Reset Mode: The exclusive serial communication protocol disclosed in the present invention defines the reset of the master control chip 12 for all slave chips H1 to MN (Rese〇 control

請參閱第九圖,該圖係為本發明所揭示之訊號傳輸方法之 重置模式時序圖,顯示出時脈訊號與重置訊號的時序關 係。時脈訊號與重置訊號係分別透過時脈線m2與資料線 164傳輸,重置模式的步驟為主控制器晶片12組成一重置 訊號’並將此重置訊號傳輸至從屬晶片14。倘若資料線的 常態為高準位狀態,所述之重置訊號可為持續時脈週 期的低準位訊號,其中N為一大於1的整數。第九圖的具 體實施例中,資料線164在常態為高準位狀態,當主控制 器晶片12重置從屬晶片時,係持續產生512至1024個時 脈週期的低準位訊號,從屬晶片141〜14N識別訊號型態為 16 !352296 重置訊號,便執行晶片重置程序。 第六··唤醒模式: 請參閱第十圖’該圖係為主控制器晶片12的時脈產生 系統的系統架構示意圖。如第十圖所示,時脈產生系統 包括有一多工器121及一除頻器123,多工器121可輪入 ~~時脈訊號CLK1、CLK2。舉例來說,其時脈頻率分別為 32MHz (高頻模式)及32KHz (低頻模式),輸入多工器 121的時脈吼號CLK1、CLK2係基於一致能訊號EN的邏 輯值,擇一輸出至除頻器123作進一步頻率分割,以產生 —時脈訊號CLK輸出至時脈線162。 所述之專屬串列通訊協定係定義主控制器晶片12具 有一正常模式及一省電模式,主控制器晶片12可於閒置一 段時間後進入省電狀態,以節省電力消耗。於正常狀態下, 夕工為121係基於致能訊號εν的邏輯值,選擇高頻模式 的時脈訊號CLK1輸出;於省電模式下,致能訊號£1^將 轉變邏輯值’以控制多工器121選擇低頻模式的時脈訊號 CLK2輸出。 喚醒模式之步驟首先係由從屬晶片14組成一喚醒訊 號傳輸到主控制器晶片12,將主控制器晶片12由省電模 式中喚醒,以回復正常模式操作。請同時參閱第十一圖, «亥圖係為本發明所揭示之訊號傳輸方法之喚醒時序圖,顯 不出喚醒模式下,時脈訊號CLK、喚醒訊號WAKE、中斷 訊號INT與致能訊?虎EN間的時序關係,其中時脈訊號clk 由主控制器晶片12輸出,並藉時脈線162上傳輪;喚醒訊 唬WAKE疋由從屬晶片14產生,並藉資料線傳輸到 17 1352296 主控制器晶片12的訊號;中斷訊號INT為主控制器晶片 12内部接收到喚醒訊號WAKE後所產生中斷省電模式的 訊號;而致能訊號EN為主控制器晶片π内部所產生。Please refer to the ninth figure, which is a reset mode timing diagram of the signal transmission method disclosed in the present invention, showing the timing relationship between the clock signal and the reset signal. The clock signal and the reset signal are transmitted through the clock line m2 and the data line 164, respectively. The reset mode step forms a reset signal for the master controller chip 12 and transmits the reset signal to the slave wafer 14. If the normal state of the data line is a high level state, the reset signal may be a low level signal of a continuous clock period, where N is an integer greater than one. In the specific embodiment of the ninth embodiment, the data line 164 is in a high-level state in a normal state. When the main controller chip 12 resets the slave wafer, the low-level signal of 512 to 1024 clock cycles is continuously generated. The 141~14N identification signal type is 16 !352296 reset signal, and the wafer reset procedure is executed. Sixth · Awakening mode: Please refer to the tenth figure'. This figure is a system architecture diagram of the clock generation system of the main controller chip 12. As shown in the tenth figure, the clock generation system includes a multiplexer 121 and a frequency divider 123. The multiplexer 121 can rotate the ~~ clock signals CLK1 and CLK2. For example, the clock frequency is 32MHz (high frequency mode) and 32KHz (low frequency mode), and the clock signals CLK1 and CLK2 of the input multiplexer 121 are based on the logic value of the uniform energy signal EN, and the output is selected to The frequency divider 123 performs further frequency division to generate a clock signal CLK output to the clock line 162. The exclusive serial communication protocol defines that the main controller chip 12 has a normal mode and a power saving mode, and the main controller chip 12 can enter a power saving state after being idle for a period of time to save power consumption. In the normal state, Xigong is the 121 system based on the logic value of the enable signal εν, and selects the clock signal CLK1 output of the high frequency mode; in the power saving mode, the enable signal £1^ will change the logic value 'to control more The processor 121 selects the clock signal CLK2 output of the low frequency mode. The awake mode is first performed by the slave wafer 14 composing a wake-up signal to the master controller chip 12, and the master controller chip 12 is woken up in the power-saving mode to resume normal mode operation. Please also refer to the eleventh figure. «Haitu is the wake-up timing diagram of the signal transmission method disclosed in the present invention. In the wake-up mode, the clock signal CLK, the wake-up signal WAKE, the interrupt signal INT and the enable signal are not displayed. The timing relationship between the tigers EN, wherein the clock signal clk is output by the main controller chip 12 and is transmitted by the clock line 162; the wake-up signal WAKE is generated by the slave wafer 14 and transmitted by the data line to the main control of 17 1352296 The signal of the chip 12 is interrupted. The signal INT is generated by the internal controller chip 12 after receiving the wake-up signal WAKE. The enable signal EN is generated inside the chip π of the main controller.

如第十一圖所示,致能訊號ΕΝ為高準位,此時,多 工器121將選擇32ΚΗζ的時脈訊號CLK2來產生時脈訊號 CLK,使得時脈訊號CLK以低頻模式輸出,以節省電力消 耗’當從屬晶片14產生持續一個時脈週期為低準位的喚醒 訊號WAKE輪出至主控制器晶片12後,主控制器晶片、12 内部係產生—中斷訊號INT中斷省電模式,主控制器晶片 12亚回應中斷訊號INT,將致能訊號EN的邏輯值由高準 =轉變為低準位。致能訊號EN邏輯值的轉變將控制多工 益121選擇32MHz的時脈訊號CLIC1來產生時脈訊號 使得時脈訊號CLK以高頻模式輸出,以支援主控帝; 益晶片12的正常模式操作。As shown in FIG. 11 , the enable signal ΕΝ is at a high level. At this time, the multiplexer 121 selects the 32 ΚΗζ clock signal CLK2 to generate the clock signal CLK, so that the clock signal CLK is output in the low frequency mode. Saving power consumption' When the slave wafer 14 generates a wake-up signal WAKE that continues to a low level with a clock cycle to the main controller chip 12, the main controller chip, 12 internal system generates an interrupt signal INT interrupt power saving mode, The main controller chip 12 sub-responds to the interrupt signal INT, and the logic value of the enable signal EN is changed from the high level = low level to the low level. The transition of the logic value of the enable signal EN will control the multi-function 121 to select the 32MHz clock signal CLIC1 to generate the clock signal so that the clock signal CLK is output in the high frequency mode to support the master control; the normal mode operation of the chip 12 .

^又,另—具體實施例中,主控制器晶片12於省電模式 下,中斷時脈訊號的輸出,從屬晶片14必須利用自行產生 的時脈訊號來支援喚醒訊號的產生與傳輸。 由以上實例詳述,當可知悉本發明之晶片系統及其 列Ϊ傳Μ法中’主㈣器晶片與從屬晶片係根據專屬串 ^讯協定的規縣組成訊號與傳輸减,且本發明之專 協&簡化了封包訊號的結構,使得主控制器晶 作^虛奴屬晶片間得以快速地組成封包訊號,並快速地 僂丄二處理,攸而可依照主控制器晶片的系統時脈頻率來 封:执f況:虎’使得晶片系統的傳輸速率大幅提升。此外, ”、的簡彳b亦將使得封包處理與傳輸機㈣硬體設計 18 1352296 成本大為降低。 惟,以上所述,僅為本發明的具體實施例之詳細說明 * 及圖式而已,並非用以限制本發明,本發明之所有範圍應 ·· 以下述之申請專利範圍為準,任何熟悉該項技藝者在本發 明之領域内,可輕易思及之變化或修飾皆可涵蓋在以下本 案所界定之專利範圍。 【圖式簡單說明】 • 第一圖係為本發明所揭示之晶片系統之系統架構示意 圖; 第二圖係為本發明所揭示之控制命令封包之結構示意 圖; 第三圖係為本發明所揭示之中斷命令封包之結構示意 圖; 第四圖係為本發明所揭示之命令回應封包之結構示意 圖; • 第五圖係為本發明所揭示之中斷回應封包之結構示意 圖, 第六圖係為本發明所揭示之訊號傳輸方法之寫入模式 . 之步驟流程圖; 第七圖係為本發明所揭示之訊號傳輸方法之主動讀取 模式之步驟流程圖, '第八圖係為本發明所揭示之訊號傳輸方法之中斷模式 之步驟流程圖; . 第九圖係為本發明所揭示之訊號傳輸方法之重置模式 19 1352296 時序圖; 第十圖係為本發明所揭示之主控制器晶片的時脈產生 系統之一具體實施例之系統架構示意圖;以及 第十一圖係為本發明所揭示之訊號傳輪方法之喚醒模 式時序圖。 【主要元件符號說明】 1 〇 .晶片系統 12 :主控制器晶片 121 :多工器 141〜14N :從屬晶片 162 :時脈線 200 :控制命令封包 12〇:時脈產生系統 123:除頻器 16 .傳輪介面 164 :資料線 210、310、410、510 :起始位元 220、230、240、320、330、420、520 :攔位 250、340、430、530 :結東位元 300 :中斷命令封包 400 :命令回應封包 500 :中斷回應封包 CLK、CLK1、CLK2 :時脈訊號 EN :致能訊號 INT :中斷訊號 WAKE :喚醒訊號 20Further, in another embodiment, the main controller chip 12 interrupts the output of the clock signal in the power saving mode, and the slave chip 14 must use the self-generated clock signal to support the generation and transmission of the wake-up signal. As is clear from the above examples, when it is known that the wafer system of the present invention and its serial transmission method, the main (four) wafer and the slave wafer are combined according to the rules and regulations of the exclusive serial communication protocol, and the present invention is The Association & simplifies the structure of the packet signal, so that the main controller crystals can quickly form a packet signal and quickly process it, which can be based on the system clock of the main controller chip. The frequency to seal: the situation: the tiger's make the transfer rate of the wafer system greatly increased. In addition, the simplification b of the package will also greatly reduce the cost of the packet processing and the transmission (4) hardware design 18 1352296. However, the above description is only a detailed description of the specific embodiment of the present invention* and the drawings. It is not intended to limit the invention, and all of the scope of the present invention is intended to be limited to the following claims. Any change or modification that can be easily conceived in the field of the present invention can be covered by the following. The scope of the patent defined in the present application. [Simplified illustration of the drawings] The first diagram is a schematic diagram of the system architecture of the wafer system disclosed by the present invention; the second diagram is a schematic diagram of the structure of the control command packet disclosed by the present invention; The figure is a schematic structural diagram of an interrupt command packet disclosed by the present invention; the fourth figure is a schematic structural diagram of a command response packet disclosed by the present invention; • FIG. 5 is a schematic structural diagram of an interrupt response packet disclosed by the present invention. Figure 6 is a flow chart of the steps of the signal transmission method disclosed in the present invention. The seventh figure is the disclosure of the present invention. A flow chart of the steps of the active reading mode of the transmission method, 'the eighth figure is a flow chart of the steps of the interrupt mode of the signal transmission method disclosed by the present invention; ninth figure is the weight of the signal transmission method disclosed by the present invention Mode 19 is a timing diagram of a specific embodiment of a clock generation system of a main controller chip disclosed in the present invention; and FIG. 11 is a signal transmission disclosed in the present invention. The wake-up mode timing diagram of the round method. [Main component symbol description] 1 晶片. Wafer system 12: main controller chip 121: multiplexer 141~14N: slave wafer 162: clock line 200: control command packet 12: Pulse generation system 123: frequency divider 16. Transmission interface 164: data lines 210, 310, 410, 510: start bits 220, 230, 240, 320, 330, 420, 520: blocks 250, 340, 430 530: knot east bit 300: interrupt command packet 400: command response packet 500: interrupt response packet CLK, CLK1, CLK2: clock signal EN: enable signal INT: interrupt signal WAKE: wake-up signal 20

Claims (1)

13-52296 、申請專利範圍: ⑽年8月12曰修正替換頁 晶片系統,包括 種 — 晶片,係產生一時脈訊號,其中該時脈訊號 、、’,Ί主控制器晶片之—系統時脈的頻率相同; >、一從屬晶片’係祕於至少—週邊功能I置,里中 該週邊功能裝置具有個別之位址;以及 /、 一傳輸介面’ _接於該主控制器晶片以及該從屬晶片 之間’ s亥傳輸介面包括: 一資料線’ _接於該主控制器晶片以及該從屬晶片 之間;以及 一時脈線,_接於該主控制器晶片以及該從屬晶片 之間,以將該時脈訊號傳輸至該從屬晶片; 其中該主控制器晶片以及該從屬晶片係依照一專屬串 列通訊協定組成訊號,並透過該資料線雙向傳輸訊 说’以根據該週邊功能裝置個別的位址,控制該週邊 功能裝置的運作。 2、 如帽專利範圍第!項所述之晶片系統,其中根據該專 屬串列通tfl協定,社控制所域減的類別包 括有一中斷命令封包及一控制命令封包。 3、 如中請專利範圍第2項所述之晶片系統,其中根據該專 屬串列通訊協定,該中斷命令封包為12位元,並被區分 為一起始位元、一結束位元以及二攔位,該等欄位係分 別用以定義中斷命令以及接受中斷之目的地位址。 4、 如申請專利範圍第2項所述之晶片紐,其中根據該專 屬串列通訊協定,該控制命令封包為2〇位元,並被區分 21 1352296 ; 100年8月12曰修正替換頁 為一起始位元、一結束位元以及三欄位,該等攔位係分 別用以定義一控制模式、接受命令之目的地以及命令資 料。 ' 5、如申請專利範圍第2項所述之晶片系統,其中根據該專 屬串列通訊協定,該控制命令封包為12位元,並被區分 為一起始位元、一結束位元以及二欄位,該二攔位係分 別用以定義一系統控制模式以及該系統控制模式的種 類。 6、 如申請專利範圍弟1項所述之晶片糸統,其中根據該專 屬串列通訊協定,該從屬晶片所組成訊號的類別包括有 一中斷回應封包以及一命令回應封包。 7、 如申請專利範圍第6項所述之晶片系統,其中根據該專 屬串列通訊協定,該命令回應封包為10位元,並被區分 為一起始位元、一結束位元以及一欄位,該欄位係用以 填入資料。 8、 如申請專利範圍第6項所述之晶片系統,其中根據該專 屬串列通訊協定,該中斷回應封包為10位元,並被區分 為一起始位元、一結束位元以及一欄位,該欄位係用以 填入該從屬晶片所耦接之週邊功能裝置的中斷值。 . 9、如申請專利範圍第1項所述之晶片系統,其中該主控制 器晶片與該從屬晶片具有個別的封包處理機制與有限 狀態機,該主控制器晶片與該從屬晶片個別之封包處理 機制與有限狀態機係根據該專屬串列通訊協定,控制該 主控制器晶片與該從屬晶片間之訊號組成格式與訊號 傳輸程序。 ' 22 10、,丄 100年8月12日修正 11 請專利範圍第9項所述之晶片系統該主控制 :晶片及該從屬晶片間之訊號傳輸類別包括有一中斷 模式冑入模式、一主動讀取模式、一被動讀取模式、 —重置模式以及一喚醒模式。 ―,訊號傳輸方法’係剌於申請專利範圍第1G項所述 ^晶片純巾該巾斷模式的訊㈣輸,該職傳輸方法 包括下列步驟: 忒主控制态晶片组成一中斷命令封包; 該主控制器晶#將該巾斷命令封包傳輸至該從 片;以及 12 該=屬晶片組成一中斷回應封包傳輸至該主控制器晶 片,以回應該中斷命令封包的接收。 I?:::方法,係適用於申請專利範圍第1〇項所述 ==該寫入模式的訊號傳輸’該訊號傳輸方法 該主控制器晶片組成一寫入控制命令封包;以及 邊=制器晶片將該寫入控制命令封包傳輸至該從屬 11 Γι專利親圍第12項所述之訊號傳輸方法,盆中於'亥 =;片組成該寫入控制命令封包的步驟前,更包 δ亥主控制器晶片組成一中齡八八A 封包傳輸至該從封包’並將該中斷命令 該,屬晶片組成—中斷回應封包傳輸 片’以回應該中斷命令封包;以及/王控制益曰曰 23 1352296 100年8月12曰修正替換頁 該主控制器晶片根據該中_應封包,k是否組成i~~ 寫入控制命令封—該從屬晶片。 14、 一,號傳輸方法,係期於申請專利範㈣H)項所述 之曰曰片系先中。亥主動項取模式的訊號傳輪,該訊號傳輸 方法包括下列步驟: 該主控制器晶片組成-讀取控制命令封包;以及 該主控制器晶片將該讀取控制命令封包傳輸至該從 晶片。 15、 如申請專利範圍第14項所述之訊號傳輸方法,其中於該 主控制器晶片將該讀取控制命令封包傳送至該從屬晶 片之後,更包括下列步驟: 該從屬晶片根據該讀取控制命令封包,判斷是否須回應 5亥5買取控制命令封包的接收;以及 倘若判斷結果為是,則該主控制器晶片組成一命令回應 封包傳輸至該主控制器晶片。 16、 如申請專利範圍第14項所述之訊號傳輸方法,其中於該 主控制器晶片組成該讀取控制命令封包的步驟前,更包 括下列步驟: 该主控制器晶片組成一中斷命令封包,並將該中斷命令 封包傳輸至該從屬晶片;以及 該從屬晶片組成一中斷回應封包傳輸至該主控制器晶 片,以回應該中斷命令封包。 17、 —種訊號傳輸方法,係適用於申請專利範圍第1〇項所述 之晶片系統中該被動讀取模式的訊號傳輸,該訊號傳輸 方法包括下列步驟: · 24 1352296 . 100年8月12日修正替換頁 該主控制器晶片組成一中斷命令封包; 該主控制器晶片將該中斷命令封包傳輸至該從屬晶片; 該從屬晶片組成一中斷回應封包傳輸至該主控制器晶 ' 片,以回應該中斷命令封包的接收;以及 該主控制器晶片組成一讀取控制命令封包傳輸至該從 屬晶片,以回應該中斷回應封包的接收。 18、 如申請專利範圍第17項所述之訊號傳輸方法,其中於該 主控制器晶片將該讀取控制命令封包傳輸至該從屬晶 片之後,更包括下列步驟: 該從屬晶片根據該讀取控制命令封包,判斷是否須回應 該讀取控制命令封包的接收;以及 倘若判斷結果為是,則該從屬晶片組成一命令回應封包 傳輸至該主控制器晶片。 19、 一種訊號傳輸方法,係適用於申請專利範圍第10項所述 之晶片系統中該重置模式的訊號傳輸,該訊號傳輸方法 包括下列步驟: 該主控制器晶片組成一重置訊號;以及 該主控制器晶片將該重置訊號傳輸至該從屬晶片。 20、 如申請專利範圍第19項所述之訊號傳輸方法,其中該資 料線的常態為高準位狀態,該重置訊號係為持續N個時 脈週期的低準位訊號,其中N為一大於1的整數。 21、 如申請專利範圍第20項所述之訊號傳輸方法,其中該N 值係介於512至1024之間。 22、 一種訊號傳輸方法,係適用於申請專利範圍第10項所述 之蠤片系統中該喚醒模式的訊號傳輸,以將該主控制器 25 23 24 25 26 晶片由一省電模式中喚醒 驟: 100年8月12日修正替換頁 該訊號傳輪包括下列 〇從屬晶片組成—喚醒訊號; 片將該喚醒訊號傳輸至該主控制器晶片;以及 弋==片回復為—正f模式操作’以回應於該喚 醒訊號的接收。 專利範圍第22項所述之訊號傳輸方法,其中於該 2 $式下’ $主控制器晶片係控制該時脈訊號為高頻 ^省電"^式下,該主控㈣係控龍時脈訊號 下=?核,轉變為低頻模式’於該主控制器晶片回復該 一吊板式操作時,係控制該時脈訊號由低頻模式 向頻槿忒。 =申請專鄕圍第23摘敎訊賴輸方法,其中該資 ;線的常恶為高準位狀態,該唤醒訊號係為持續N個時 脈週期的低準位訊號’其巾N為—大於1的整數。 ,、申明專利範圍第22項所述之訊號傳輸方法,其中於該 省電模式下主控制器係巾斷產生該時脈訊號,於該 控制器曰曰片回復該正常模式操作時,係回復該時脈訊 號為正常傳輪。 2請專·圍第25項所述之喊#輸方法,其中該從 曰日片係產生一時脈訊號,以支援該唤醒訊號的組成與 傳輸。 =申請專利範圍第%項所述之訊號傳輸方法,其中該資 料線的$態為南準位狀態,該喚醒訊號係為持續N個時 脈週期的低準位訊號’其.中N為一大於丨的整數。 26 2713-52296, the scope of application for patents: (10) August 12th, revised replacement page wafer system, including seed-to-wafer, generates a clock signal, where the clock signal, ', Ί main controller chip - system clock The frequency is the same; >, a slave wafer is secreted at least by the peripheral function I, wherein the peripheral function device has an individual address; and/or a transmission interface is connected to the main controller chip and The 'shai transmission interface between the slave wafers includes: a data line _ is connected between the main controller chip and the slave wafer; and a clock line is connected between the main controller chip and the slave wafer, Transmitting the clock signal to the slave chip; wherein the master controller chip and the slave chip form a signal according to a dedicated serial communication protocol, and transmit a two-way transmission through the data line to "in accordance with the peripheral function device The address of the device controls the operation of the peripheral function device. 2, such as the cap patent range! The wafer system of claim 1, wherein the category of the community control field reduction includes an interrupt command packet and a control command packet according to the specific serial link tfl agreement. 3. The wafer system of claim 2, wherein the interrupt command packet is 12 bits according to the exclusive serial communication protocol, and is divided into a start bit, an end bit, and a second block. Bits, these fields are used to define the interrupt command and accept the destination address of the interrupt. 4. The wafer card described in claim 2, wherein the control command packet is 2 bits according to the exclusive serial communication protocol, and is distinguished by 21 1352296; A start bit, an end bit, and three fields are used to define a control mode, a destination to accept the command, and command data. 5. The wafer system of claim 2, wherein the control command packet is 12 bits according to the exclusive serial communication protocol, and is divided into a start bit, an end bit, and two columns. Bits, the two blocks are used to define a system control mode and the type of the system control mode, respectively. 6. The wafer system as claimed in claim 1 wherein, according to the proprietary serial communication protocol, the class of signals formed by the slave chip includes an interrupt response packet and a command response packet. 7. The wafer system of claim 6, wherein the command response packet is 10 bits according to the exclusive serial communication protocol, and is divided into a start bit, an end bit, and a field. This field is used to fill in the information. 8. The wafer system of claim 6, wherein the interrupt response packet is 10 bits according to the exclusive serial communication protocol, and is divided into a start bit, an end bit, and a field. The field is used to fill in the interrupt value of the peripheral function device to which the slave wafer is coupled. 9. The wafer system of claim 1, wherein the master controller wafer and the slave wafer have separate packet processing mechanisms and finite state machines, and the master controller wafer and the slave wafer are individually packaged. The mechanism and the finite state machine control the signal composition format and signal transmission procedure between the main controller chip and the slave chip according to the exclusive serial communication protocol. ' 22 10, 8August 12th, Rev. 11 Please refer to the wafer system described in ninth patent. The main control: the signal transmission category between the chip and the slave chip includes an interrupt mode input mode, an active read. Take mode, a passive read mode, - reset mode, and an awake mode. ―, the signal transmission method 剌 is in the application of the patent scope of the 1G item, the wafer wipe mode of the towel mode (four) transmission, the job transmission method comprises the following steps: 忒 the main control state wafer constitutes an interrupt command packet; The master controller crystal # transmits the wipe command packet to the slave; and 12 the slave wafer constitutes an interrupt response packet transmitted to the master controller chip to respond to the receipt of the interrupt command packet. The I?::: method is applicable to the application of the patent scope of the first item == the signal transmission of the write mode 'the signal transmission method, the main controller chip constitutes a write control command packet; and the side = system The device wafer transmits the write control command packet to the signal transmission method described in Item 12 of the subordinate 11 Γι patent, in the basin, before the step of composing the write control command packet, The main controller chip consists of a middle-aged eight-eight A packet transmitted to the slave packet 'and the interrupt command, which belongs to the chip-interrupt response packet transmission slice' to return the interrupt command packet; and / Wang control benefits 23 1352296 August 12, 2014 Correction replacement page The main controller chip according to the middle _ should be packaged, whether k constitutes i~~ write control command seal - the slave wafer. 14. The transmission method of No.1 is the first in the film system mentioned in the application of patent (4) H). The signal transmission method of the active item selection mode includes the following steps: the main controller chip composes a read control command packet; and the main controller chip transmits the read control command packet to the slave wafer. 15. The signal transmission method of claim 14, wherein after the main controller chip transfers the read control command packet to the slave wafer, the method further comprises the following steps: the slave wafer is controlled according to the read The command packet determines whether it is necessary to respond to the receipt of the buy control command packet; and if the result of the determination is yes, the master controller chip forms a command response packet to be transmitted to the main controller chip. The signal transmission method of claim 14, wherein before the step of forming the read control command packet by the main controller chip, the method further comprises the following steps: the main controller chip forms an interrupt command packet, And transmitting the interrupt command packet to the slave wafer; and the slave wafer is configured to transmit an interrupt response packet to the master controller chip to respond to the interrupt command packet. 17. The signal transmission method is applicable to the signal transmission in the passive reading mode in the wafer system described in claim 1 of the patent application. The signal transmission method comprises the following steps: · 24 1352296. August 12, 100 The master controller replaces the page to form an interrupt command packet; the master controller chip transmits the interrupt command packet to the slave wafer; the slave wafer constitutes an interrupt response packet transmitted to the master controller chip The reception of the command packet should be interrupted; and the master controller chip is configured to transmit a read control command packet to the slave wafer in response to the receipt of the interrupt response packet. 18. The signal transmission method of claim 17, wherein after the main controller chip transmits the read control command packet to the slave wafer, the method further comprises the following steps: the slave wafer is controlled according to the read The command packet determines whether it is necessary to read back the reception of the control command packet; and if the result of the determination is yes, the slave wafer constitutes a command response packet transmitted to the main controller chip. 19. A signal transmission method for signal transmission in the reset mode in a wafer system according to claim 10, the signal transmission method comprising the steps of: the main controller chip composing a reset signal; The master controller chip transmits the reset signal to the slave wafer. 20. The signal transmission method according to claim 19, wherein the normal state of the data line is a high level state, and the reset signal is a low level signal for a duration of N clock cycles, wherein N is a An integer greater than one. 21. The signal transmission method of claim 20, wherein the N value is between 512 and 1024. 22. A signal transmission method, which is applicable to the signal transmission of the awake mode in the stencil system described in claim 10, to wake up the main controller 25 23 24 25 26 from a power saving mode : Correction of the replacement page on August 12, 100. The signal transmission includes the following subordinate wafers consisting of a wake-up signal; the slice transmits the wake-up signal to the main controller chip; and 弋 == the slice returns to - positive f mode operation' In response to the receipt of the wake-up signal. The signal transmission method according to Item 22 of the patent scope, wherein in the 2 $ type, the main controller chip system controls the clock signal to be a high frequency ^ power saving "^ type, the main control (four) is controlled by the dragon Under the clock signal, the core is converted to the low frequency mode. When the main controller chip returns to the hanging plate operation, the clock signal is controlled from the low frequency mode to the frequency. = Apply for the 23rd pick-up method, which is the capital; the normal evil of the line is the high-level state, and the wake-up signal is a low-level signal that lasts for N clock cycles. An integer greater than one. The signal transmission method of claim 22, wherein the main controller is configured to generate the clock signal in the power saving mode, and the controller responds when the controller returns to the normal mode operation. The clock signal is a normal transmission wheel. 2 Please use the shouting method described in item 25, which generates a clock signal from the next day to support the composition and transmission of the wake-up signal. = The signal transmission method described in item 5% of the patent application, wherein the $ state of the data line is a south level state, and the wake-up signal is a low level signal for a continuous N clock period 'N. An integer greater than 丨. 26 27
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