TWI352296B - Chip system and signal transmission method thereof - Google Patents

Description

1352296 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer system, in particular, a crystal and a signal transmission of a signal and a transmission signal according to a proprietary string protocol. [Prior Art]

The miniaturization and integration system is the pursuit of the current industry and consumers. In general, electronic products use programmable technology to make W = system (9) film-body programming to control the core controller chip. Each peripheral device 'has the functional requirements of the product. In the past, when the core controller=time 4 industrial device, the address line and the control line of each device must be transferred to the pins of the core controller, and the control resources of different pins are used to control each device or Data access. As the peripheral functions controlled by the core controller increase, the controller pin resources occupied also increase. In order to solve this problem, an inter-chip synchronous serial c〇m_icati〇n imerface is available. The synchronous serial interface includes a plurality of transmission lines for respectively transmitting the clock signal and the series of baits, and the core, the controller and the slave crystal for performing the peripheral function are: the connection pins are simultaneously coupled to the transmission lines, according to Individual addresses are used to complete control functions or data access between wafers. In this way, the number of connections between the master and slave controllers can be significantly reduced. At present, the inter-chip synchronous serial communication interface widely used by the microcontroller includes three types: an I2C (Inter Integrated Circuit), an SPI (Serial Peripheral Interface), and a Microwire Interface. 6 i352296 Among the above two communication interfaces, the Pc communication interface is widely used. It is a two-line transfer wheel 'includes a series of line lines (SeHd. data line), and a series of serial ciock lines (SCL). According to the l2c agreement, j2C has three speed modes, including standard mode (packet transmission rate up to 100Kbps), fast mode (packet transmission rate up to _ and high speed mode (packet transmission rate up to 34 Mbps). In view of semiconductor manufacturing process The data processing technology and data processing technology are increasingly improving the data processing performance of microprocessors and microcontrollers, and the clock rate is also increasing. Therefore, for the wafer; the rate requirement is more advanced. Because of the existing communication such as & The agreement is that the sequential logic achieves the communication effect, and the hardware circuit (4) has no system clock transmission. In order to speed up the master-slave controller inter-chip control command = transmission rate and improve the performance of the electronic product, the inventor of the present invention proposed the case. The invention proposes a signal transmission method and a transmission interface,

The frame format (F_ef view at) and the packet processing process enable H to be quickly reduced and processed, so that the crystal transfer speed = liter. In addition, the simplification of the packet format greatly reduces the hardware design cost of processing the transport packet. ·^珂匕兴处 [Summary of the Invention] Therefore, the object of the present invention is to provide a method for transmitting a variety of signals, which is composed of a controller and a proprietary protocol. The signal transmission rate of the chip and the slave chip is greatly increased. The present invention discloses a wafer system including a wafer, a >-subordinate wafer, and a transmission interface. The master control chip 7 1352296 generates a clock signal, and the slave chip system is coupled to at least one peripheral function device having an individual address, and the transmission interface is coupled between the main controller chip and the slave wafer. The transmission interface includes a data line and a clock line. The lean line is connected between the main control chip and the slave chip. The clock line is coupled between the main controller chip and the slave chip to connect the clock signal. Transfer to the slave wafer. The main controller chip and the slave chip form a signal according to a dedicated serial communication protocol, and transmit signals bidirectionally through the data line to control the operation of the peripheral function device ® according to the individual address of the peripheral function device. The main controller chip and the slave wafer have separate packet processing mechanisms and finite state machines, and the individual controller chip and the slave chip individually process the packet processing mechanism and the finite state machine according to the exclusive serial communication protocol to control the main controller. The signal between the chip and the slave wafer forms a format and a signal transmission program. The signal transmission category between the master controller chip and the slave chip includes an interrupt mode, a write mode, an active read mode, a passive read mode, a reset mode, and an awake mode. The present invention further discloses a signal transmission method suitable for signal transmission of the interrupt mode in the wafer system. The step of the signal transmission method of the interrupt mode is first, the main controller chip forms an interrupt command packet; secondly, the main controller chip transmits the interrupt command packet to the slave wafer; finally, the 'slave chip constitutes an interrupt response packet transmission to the main control The chip is back to the reception of the interrupted command packet. The invention further discloses a signal transmission method suitable for signal transmission in the write mode in the wafer system. The step of the signal transmission method of the write mode is first, the main controller chip is composed of a write control command block 8 f ' secondly, the main controller chip transfers the write control command packet to the slave B slice. The invention further discloses a signal transmission method, which is suitable for the job transmission wheel of the line reading mode in the crystal system. The method of actively reading the mode is the first step of the main controller chip composition-read control to the object ^'the main controller chip will read the control command packet transmission «the genus wafer. The film system 揭示 揭示 reveals a signal transmission method for the signal transmission of the crystal sharp drive read mode. Passive read mode signal 4 rounds: the steps of the method are first, the main controller chip constitutes an interrupt command piece; the dragon; the person... the main control benefit chip transmits the interrupt command packet to the slave crystal chip two 'subordinate wafers' interrupt response The packet transmission to the main controller "Oi Cheng" interrupts the reception of the packet; finally, the main controller chip should be _=彳 command packet relay (4) ", (4) should be interrupted back to j bar reception. The film system does not reveal a signal transmission The method is applied to the step-reset mode of the crystal method of the signal transfer wheel. The ^ 拴 拴 曰曰 组成 组成 组成 组成 组成 组成 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置The signal transmission to the slave chip. The chip system signal transmission method is applied to the step of the crystal method, the scar-type heart-shaped wheel. The wake-up mode signal-transmitting chip-side slave wafer-waking signal; Secondly, the subordinate word awake signal is transmitted to the main control piece and returned to normal 楛...4 pieces 'after the main controller crystal: positive (four) field, (4) should be received by the wake-up signal. The summary and the following detailed description and Drawings, both Other objects and advantages of the present invention will be described in the following description and drawings in order to explain the present invention. The chip system and its signal transmission method 'is a specification of the main controller chip and the peripheral slave chip to form a signal and a transmission signal according to a dedicated serial communication protocol for the purpose of communication. First, please refer to the first figure, which is A schematic diagram of the system architecture of the wafer system 10 disclosed herein. As shown in the first figure, the wafer system 10 includes a main controller wafer 12, a plurality of slave wafers 141~14N, and a transmission interface 16. The transmission interface 16 includes a clock. A clock line 162 and a data line 164, the main controller chip 12 and the slave chips 141 to 14N are respectively connected to the clock line 162 of the transmission interface 16 and the data line 164. The main controller chip 12 is coupled. The host system connected to a host (not shown) is used as the main control core of the wafer system. For example, In the system, the host refers to the central processing unit of the computer, and the main controller chip 12 refers to the keyboard controller around the central processing unit. Generally, the main controller chip 12 is often given various control functions, and the subordinate 141 ~14N can be a general-purpose output into the bee expansion chip, the motor drive chip and the backplane drive chip controlled by the main controller chip 12. Among them, the data line 164 is a bidirectional transmission serial packet signal. The main controller crystal > 12 and slave chips 141~14N play the transmitting end and the receiving end according to the control mode, send the packet signal to the data line 164, and receive the packet signal from the data line 164, and respond to the received packet signal. Crystal 1352296 chip system H) t, the main controller chip 12 generates a clock signal, and transmits. In the specific embodiment, the frequency of the pulse signal "allows the frequency of the 12 system clocks of the control chip to be the same. For example, if the system clock frequency of the main chip U is 16 MHz, the clock signal of the Bahan It is 16MHz, and the clock cycle is about 62 5ns. Thus, the wafer system's packet information can be improved to (4) drunk: and ^

The control between the controller wafer 12 and the slave wafers 141 to 14N is smooth and rapid. - The main controller crystal #12 and the slave crystals 4 141 to 14N each have a "protocol engine". The agreement engine is composed of the matching source=source and is based on a proprietary serial communication protocol: 1 packet encoding and decoding, the command signal inside the chip is composed of the sealing signal, and the received packet signal is received. Processing is converted to the inside of the wafer

The main controller crystal 12 and each of the slave chips 141 to 14N have individual, packet processing mechanisms and finite state machines (Fimte_dirty-view) to control the main controller crystal m and according to the exclusive serial communication protocol The slave chip 141~ has just formed a signal: a transmission signal according to the frame format of the money. The slave chips 141 to 14N are sequentially connected and control one or more peripheral function devices, each of the peripheral function devices has an individual address measurement, and the master controller chip 12 is 'for each of the slave chips 141 to 14N=each peripheral function The device is addressed to identify the correct source of the packet signal and to ensure that the packet signal is delivered to the correct destination. In the chip system 10, the signal transmission categories between the main control state chip 丨2 and the slave chips 141~14N include an interrupt mode, a write mode, an active read 11 1352296 mode, a passive read mode, a reset mode, and an awake mode. The active read mode is that the master controller chip 12 actively performs read operations on the slave chips 141 to 14N; and the passive read mode is that the slave chips 141 14 14N send interrupt requests to the master controller chip 12, and then the master The controller wafer 12 reads the slave wafer 14 HN or directly reads the master controller wafer 12 from the slave wafers 141 14 14N. The various packet signal formats of the present invention are described below. The categories of signals composed by the main controller chip 12 include interrupt command packets and control command packets. Interrupt and read/write control is performed on the slave peripheral devices 141 to 14N and their respective peripheral functional devices. Please refer to the figure of the younger one. This figure is a schematic diagram of the control command packet 200 of the terminal 12 of the main controller. As shown in the second figure, the control command packet 200 is 20 bits. Control command packet 200 includes a start bit 210, an end bit 250, and three bays 220, 230, 240. Wherein the start bit 210 and the end bit 250 are respectively located in the first bit and the twentieth of the control command packet 200 for identifying the integrity of the control command packet 200. Field 220 is a command bar, which is represented by 2 bits. The control mode is the active item fetch mode or the write mode. In a specific embodiment, the field 220 is 01 to indicate that the control command packet 2 is a read control command packet, and the field 220 is 10 to indicate that the control command packet 2 is a write command packet. Field 230 is the address block, and the destination address of the packet signal is represented by 8 bits. Field 240 is a data column, and the control command data is filled in by octet ^. Please refer to the third figure, which is a schematic diagram of the structure of the interrupt command packet 300 on the 12th end of the main controller chip. As shown in the third figure, the interrupt command packet %P〇 12 1352296 is 12 bits. The interrupt command packet 3 includes a start bit one end bit 340 and two stop bits 320, 33. The start bit, 3 = and the end bit 340 are respectively located in the first bit and the busy bit of the interrupt command packet 3, and the integrity of the packet is blocked by the money. · The 320 series is the command blocker's 32 〇 ^ 2 bits to define the control to interrupt mode. In the embodiment, the block 32 is 〇〇, indicating that the packet is interrupted. Field 330 is the address block, and the destination address of the interrupt command packet 300 is represented by 8 bits. Incidentally, the frame format of the packet 3 00 can also be flexibly used as the main controller chip 丨 2 pair = the slave frame 141 〜 14N issues the frame format of the system command. If the position 320 is interpreted as a system command, the block 33〇 is converted into a system-dependent slave chip 141~14. The signal type consisting of an interrupt reply packet and a command response packet is in response to the main control. Read and write control commands and interrupt commands issued by the chip & Please refer to the fourth figure, which is a schematic diagram of the command response packet of the slave wafer. As shown in the fourth figure, the command response packet 4 is ίο bit. The command response packet 4〇〇 includes a start bit 410, an end bit 43〇, and a block 42〇. The start bit 410 and the end bit 430 are respectively located at the third bit and the tenth bit of the command response packet 4, for identifying the integrity of the command response packet 4, and the field 42 is the data block. , fill in the information with 8 bits. Please refer to the fifth figure. The side view is the interrupt response packet of the slave chip. As shown in the fifth figure, the interrupt response packet 500 is one bit. The interrupt response packet 500 includes a start bit 510, a stop bit 53A, and a block 520. The start bit 510 and the end bit 53〇13 are respectively located in the interrupt response packet 500, and the end of the interrupt response packet 500 is completed == tens place for the genus day slice to have eight peripheral functions. Set. Each bit in the block 520 _, 7 represents the interrupt value of the specific peripheral function split 2: the interrupt status of the device. The shoulders are not described below, and the interrupt mode, the write mode, the active item fetch mode, and the wake mode of the method of the transmission method of the present invention are explained one by one. Axis turn, reset mode and call first, interrupt mode: Please refer to the sixth figure' This figure is the wafer system flow chart. For the related system architecture, please refer to the second step of the figure. The method starts from the main control 9θ /^ stands for “. As shown in the sixth figure, it is based on the periphery of the interrupt control::=: :02) Connect the interrupt command packet (step S6G4) ^^ set (four) 'compose a control peripheral function F ^ This wipes the command packet transmission to _. The slave wafer is transmitted according to the genus W 14 (step interrupt response packet transmission to the main controller a 7. Interrupt value, composition-packet reception (step S608). After 12' in response to the interrupt command sealing state (step S600). 才 The air conditioner chip 12 is returned to the idle first, write right For the following figure, please refer to the seventh figure, which is a flowchart. As shown in the seventh figure, when the write mode of the system 10 is in the idle state (step S700), the "/ begins with the main control. The firmware of the firmware 12 is based on the control of the firmware, and the production is required (step S702). Then, according to the peripheral function to be written, a write control command packet is formed (step S704), and the input is made. The control command packet is transferred to the slave wafer step S706). Thereafter, the master controller chip 12 Return to the idle state (step S7〇〇). ', 12 constitutes the writer control command packet transmission to the 曰 曰 Μ , , , , , , , , , , , , 根据 根据 根据 根据 根据 根据 根据 根据 根据The interrupt response packet of this week == is controlled, and it is determined whether or not the composition of the write control is transmitted to the slave wafer 14. Third, the active read mode: This is the image of the wafer system 10 The flow chart of the steps of the active reading mode. As shown in the eighth figure, firstly, the main control crying film 12 is in an idle state (step sη士子工利口日日片12 take-up length, base firmware control, generate A read and take C step S802). Then, φ batch, 丨MA u take the peripheral function 妒 set " for the 曰 曰 12 will be set according to the S80d face f to read a control command packet (step And transfer this control command packet to the slave 14 14 (^牛骤S806). After that, you 遛曰μ 刿攸 刿攸 刿攸 Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η Η The command packet is judged to be received by the step S8 〇 f6 卩 7 packets (step S808). The slice 12 enters two? as: 'When returning to step S_, the main controller crystal chip 14 is composed - life: back::: the judgment of the _ is * 'the sub-sliding leak.) Thereafter, 12 (step S8 〇〇 〇TJ〇°曰片12 re-enters the idle state (step slave sub-chip 14 曰片12 constitutes read-write control command packet transmission to just ': step according to the interrupt mode, for the 1352296 peripheral function device to be read Interrupt control, interrupted by the slave wafer, returning to the deer sealing spoon to control the peripheral function device's command packet transmission to the slave chip. 2. Wide decision to determine whether to form the read control. Fourth, passive read mode: Passive read mode is slave crystal

After the interrupt command packet is received, the component-towel ^ receives the main controller chip transmission response packet transmission to the main controller chip, responds to the packet, and responds to the interrupt according to the contents of the interrupt packet: the master 2: the main controller The wafer 12 is in the form of a packet; thereafter, the slave crystal responds to the receipt of the interrupt L command packet, and the component response command packet is transmitted to the main controller chip 12. Fifth: Reset Mode: The exclusive serial communication protocol disclosed in the present invention defines the reset of the master control chip 12 for all slave chips H1 to MN (Rese〇 control

Please refer to the ninth figure, which is a reset mode timing diagram of the signal transmission method disclosed in the present invention, showing the timing relationship between the clock signal and the reset signal. The clock signal and the reset signal are transmitted through the clock line m2 and the data line 164, respectively. The reset mode step forms a reset signal for the master controller chip 12 and transmits the reset signal to the slave wafer 14. If the normal state of the data line is a high level state, the reset signal may be a low level signal of a continuous clock period, where N is an integer greater than one. In the specific embodiment of the ninth embodiment, the data line 164 is in a high-level state in a normal state. When the main controller chip 12 resets the slave wafer, the low-level signal of 512 to 1024 clock cycles is continuously generated. The 141~14N identification signal type is 16 !352296 reset signal, and the wafer reset procedure is executed. Sixth · Awakening mode: Please refer to the tenth figure'. This figure is a system architecture diagram of the clock generation system of the main controller chip 12. As shown in the tenth figure, the clock generation system includes a multiplexer 121 and a frequency divider 123. The multiplexer 121 can rotate the ~~ clock signals CLK1 and CLK2. For example, the clock frequency is 32MHz (high frequency mode) and 32KHz (low frequency mode), and the clock signals CLK1 and CLK2 of the input multiplexer 121 are based on the logic value of the uniform energy signal EN, and the output is selected to The frequency divider 123 performs further frequency division to generate a clock signal CLK output to the clock line 162. The exclusive serial communication protocol defines that the main controller chip 12 has a normal mode and a power saving mode, and the main controller chip 12 can enter a power saving state after being idle for a period of time to save power consumption. In the normal state, Xigong is the 121 system based on the logic value of the enable signal εν, and selects the clock signal CLK1 output of the high frequency mode; in the power saving mode, the enable signal £1^ will change the logic value 'to control more The processor 121 selects the clock signal CLK2 output of the low frequency mode. The awake mode is first performed by the slave wafer 14 composing a wake-up signal to the master controller chip 12, and the master controller chip 12 is woken up in the power-saving mode to resume normal mode operation. Please also refer to the eleventh figure. «Haitu is the wake-up timing diagram of the signal transmission method disclosed in the present invention. In the wake-up mode, the clock signal CLK, the wake-up signal WAKE, the interrupt signal INT and the enable signal are not displayed. The timing relationship between the tigers EN, wherein the clock signal clk is output by the main controller chip 12 and is transmitted by the clock line 162; the wake-up signal WAKE is generated by the slave wafer 14 and transmitted by the data line to the main control of 17 1352296 The signal of the chip 12 is interrupted. The signal INT is generated by the internal controller chip 12 after receiving the wake-up signal WAKE. The enable signal EN is generated inside the chip π of the main controller.

As shown in FIG. 11 , the enable signal ΕΝ is at a high level. At this time, the multiplexer 121 selects the 32 ΚΗζ clock signal CLK2 to generate the clock signal CLK, so that the clock signal CLK is output in the low frequency mode. Saving power consumption' When the slave wafer 14 generates a wake-up signal WAKE that continues to a low level with a clock cycle to the main controller chip 12, the main controller chip, 12 internal system generates an interrupt signal INT interrupt power saving mode, The main controller chip 12 sub-responds to the interrupt signal INT, and the logic value of the enable signal EN is changed from the high level = low level to the low level. The transition of the logic value of the enable signal EN will control the multi-function 121 to select the 32MHz clock signal CLIC1 to generate the clock signal so that the clock signal CLK is output in the high frequency mode to support the master control; the normal mode operation of the chip 12 .

Further, in another embodiment, the main controller chip 12 interrupts the output of the clock signal in the power saving mode, and the slave chip 14 must use the self-generated clock signal to support the generation and transmission of the wake-up signal. As is clear from the above examples, when it is known that the wafer system of the present invention and its serial transmission method, the main (four) wafer and the slave wafer are combined according to the rules and regulations of the exclusive serial communication protocol, and the present invention is The Association & simplifies the structure of the packet signal, so that the main controller crystals can quickly form a packet signal and quickly process it, which can be based on the system clock of the main controller chip. The frequency to seal: the situation: the tiger's make the transfer rate of the wafer system greatly increased. In addition, the simplification b of the package will also greatly reduce the cost of the packet processing and the transmission (4) hardware design 18 1352296. However, the above description is only a detailed description of the specific embodiment of the present invention* and the drawings. It is not intended to limit the invention, and all of the scope of the present invention is intended to be limited to the following claims. Any change or modification that can be easily conceived in the field of the present invention can be covered by the following. The scope of the patent defined in the present application. [Simplified illustration of the drawings] The first diagram is a schematic diagram of the system architecture of the wafer system disclosed by the present invention; the second diagram is a schematic diagram of the structure of the control command packet disclosed by the present invention; The figure is a schematic structural diagram of an interrupt command packet disclosed by the present invention; the fourth figure is a schematic structural diagram of a command response packet disclosed by the present invention; • FIG. 5 is a schematic structural diagram of an interrupt response packet disclosed by the present invention. Figure 6 is a flow chart of the steps of the signal transmission method disclosed in the present invention. The seventh figure is the disclosure of the present invention. A flow chart of the steps of the active reading mode of the transmission method, 'the eighth figure is a flow chart of the steps of the interrupt mode of the signal transmission method disclosed by the present invention; ninth figure is the weight of the signal transmission method disclosed by the present invention Mode 19 is a timing diagram of a specific embodiment of a clock generation system of a main controller chip disclosed in the present invention; and FIG. 11 is a signal transmission disclosed in the present invention. The wake-up mode timing diagram of the round method. [Main component symbol description] 1 晶片. Wafer system 12: main controller chip 121: multiplexer 141~14N: slave wafer 162: clock line 200: control command packet 12: Pulse generation system 123: frequency divider 16. Transmission interface 164: data lines 210, 310, 410, 510: start bits 220, 230, 240, 320, 330, 420, 520: blocks 250, 340, 430 530: knot east bit 300: interrupt command packet 400: command response packet 500: interrupt response packet CLK, CLK1, CLK2: clock signal EN: enable signal INT: interrupt signal WAKE: wake-up signal 20

Claims (1)

13-52296, the scope of application for patents: (10) August 12th, revised replacement page wafer system, including seed-to-wafer, generates a clock signal, where the clock signal, ', Ί main controller chip - system clock The frequency is the same; >, a slave wafer is secreted at least by the peripheral function I, wherein the peripheral function device has an individual address; and/or a transmission interface is connected to the main controller chip and The 'shai transmission interface between the slave wafers includes: a data line _ is connected between the main controller chip and the slave wafer; and a clock line is connected between the main controller chip and the slave wafer, Transmitting the clock signal to the slave chip; wherein the master controller chip and the slave chip form a signal according to a dedicated serial communication protocol, and transmit a two-way transmission through the data line to "in accordance with the peripheral function device The address of the device controls the operation of the peripheral function device. 2, such as the cap patent range! The wafer system of claim 1, wherein the category of the community control field reduction includes an interrupt command packet and a control command packet according to the specific serial link tfl agreement. 3. The wafer system of claim 2, wherein the interrupt command packet is 12 bits according to the exclusive serial communication protocol, and is divided into a start bit, an end bit, and a second block. Bits, these fields are used to define the interrupt command and accept the destination address of the interrupt. 4. The wafer card described in claim 2, wherein the control command packet is 2 bits according to the exclusive serial communication protocol, and is distinguished by 21 1352296; A start bit, an end bit, and three fields are used to define a control mode, a destination to accept the command, and command data. 5. The wafer system of claim 2, wherein the control command packet is 12 bits according to the exclusive serial communication protocol, and is divided into a start bit, an end bit, and two columns. Bits, the two blocks are used to define a system control mode and the type of the system control mode, respectively. 6. The wafer system as claimed in claim 1 wherein, according to the proprietary serial communication protocol, the class of signals formed by the slave chip includes an interrupt response packet and a command response packet. 7. The wafer system of claim 6, wherein the command response packet is 10 bits according to the exclusive serial communication protocol, and is divided into a start bit, an end bit, and a field. This field is used to fill in the information. 8. The wafer system of claim 6, wherein the interrupt response packet is 10 bits according to the exclusive serial communication protocol, and is divided into a start bit, an end bit, and a field. The field is used to fill in the interrupt value of the peripheral function device to which the slave wafer is coupled. 9. The wafer system of claim 1, wherein the master controller wafer and the slave wafer have separate packet processing mechanisms and finite state machines, and the master controller wafer and the slave wafer are individually packaged. The mechanism and the finite state machine control the signal composition format and signal transmission procedure between the main controller chip and the slave chip according to the exclusive serial communication protocol. ' 22 10, 8August 12th, Rev. 11 Please refer to the wafer system described in ninth patent. The main control: the signal transmission category between the chip and the slave chip includes an interrupt mode input mode, an active read. Take mode, a passive read mode, - reset mode, and an awake mode. ―, the signal transmission method 剌 is in the application of the patent scope of the 1G item, the wafer wipe mode of the towel mode (four) transmission, the job transmission method comprises the following steps: 忒 the main control state wafer constitutes an interrupt command packet; The master controller crystal # transmits the wipe command packet to the slave; and 12 the slave wafer constitutes an interrupt response packet transmitted to the master controller chip to respond to the receipt of the interrupt command packet. The I?::: method is applicable to the application of the patent scope of the first item == the signal transmission of the write mode 'the signal transmission method, the main controller chip constitutes a write control command packet; and the side = system The device wafer transmits the write control command packet to the signal transmission method described in Item 12 of the subordinate 11 Γι patent, in the basin, before the step of composing the write control command packet, The main controller chip consists of a middle-aged eight-eight A packet transmitted to the slave packet 'and the interrupt command, which belongs to the chip-interrupt response packet transmission slice' to return the interrupt command packet; and / Wang control benefits 23 1352296 August 12, 2014 Correction replacement page The main controller chip according to the middle _ should be packaged, whether k constitutes i~~ write control command seal - the slave wafer. 14. The transmission method of No.1 is the first in the film system mentioned in the application of patent (4) H). The signal transmission method of the active item selection mode includes the following steps: the main controller chip composes a read control command packet; and the main controller chip transmits the read control command packet to the slave wafer. 15. The signal transmission method of claim 14, wherein after the main controller chip transfers the read control command packet to the slave wafer, the method further comprises the following steps: the slave wafer is controlled according to the read The command packet determines whether it is necessary to respond to the receipt of the buy control command packet; and if the result of the determination is yes, the master controller chip forms a command response packet to be transmitted to the main controller chip. The signal transmission method of claim 14, wherein before the step of forming the read control command packet by the main controller chip, the method further comprises the following steps: the main controller chip forms an interrupt command packet, And transmitting the interrupt command packet to the slave wafer; and the slave wafer is configured to transmit an interrupt response packet to the master controller chip to respond to the interrupt command packet. 17. The signal transmission method is applicable to the signal transmission in the passive reading mode in the wafer system described in claim 1 of the patent application. The signal transmission method comprises the following steps: · 24 1352296. August 12, 100 The master controller replaces the page to form an interrupt command packet; the master controller chip transmits the interrupt command packet to the slave wafer; the slave wafer constitutes an interrupt response packet transmitted to the master controller chip The reception of the command packet should be interrupted; and the master controller chip is configured to transmit a read control command packet to the slave wafer in response to the receipt of the interrupt response packet. 18. The signal transmission method of claim 17, wherein after the main controller chip transmits the read control command packet to the slave wafer, the method further comprises the following steps: the slave wafer is controlled according to the read The command packet determines whether it is necessary to read back the reception of the control command packet; and if the result of the determination is yes, the slave wafer constitutes a command response packet transmitted to the main controller chip. 19. A signal transmission method for signal transmission in the reset mode in a wafer system according to claim 10, the signal transmission method comprising the steps of: the main controller chip composing a reset signal; The master controller chip transmits the reset signal to the slave wafer. 20. The signal transmission method according to claim 19, wherein the normal state of the data line is a high level state, and the reset signal is a low level signal for a duration of N clock cycles, wherein N is a An integer greater than one. 21. The signal transmission method of claim 20, wherein the N value is between 512 and 1024. 22. A signal transmission method, which is applicable to the signal transmission of the awake mode in the stencil system described in claim 10, to wake up the main controller 25 23 24 25 26 from a power saving mode : Correction of the replacement page on August 12, 100. The signal transmission includes the following subordinate wafers consisting of a wake-up signal; the slice transmits the wake-up signal to the main controller chip; and 弋 == the slice returns to - positive f mode operation' In response to the receipt of the wake-up signal. The signal transmission method according to Item 22 of the patent scope, wherein in the 2 $ type, the main controller chip system controls the clock signal to be a high frequency ^ power saving "^ type, the main control (four) is controlled by the dragon Under the clock signal, the core is converted to the low frequency mode. When the main controller chip returns to the hanging plate operation, the clock signal is controlled from the low frequency mode to the frequency. = Apply for the 23rd pick-up method, which is the capital; the normal evil of the line is the high-level state, and the wake-up signal is a low-level signal that lasts for N clock cycles. An integer greater than one. The signal transmission method of claim 22, wherein the main controller is configured to generate the clock signal in the power saving mode, and the controller responds when the controller returns to the normal mode operation. The clock signal is a normal transmission wheel. 2 Please use the shouting method described in item 25, which generates a clock signal from the next day to support the composition and transmission of the wake-up signal. = The signal transmission method described in item 5% of the patent application, wherein the $ state of the data line is a south level state, and the wake-up signal is a low level signal for a continuous N clock period 'N. An integer greater than 丨. 26 27