200907693 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種晶片系統，尤指—種根據一專屬串 列通訊協定來組成訊號與傳輸訊號的晶片系統及豆訊號 輸方法。 【先前技術】 電子產品的小型化與整合化係為時下業者 : ㈣求的目標。—般而言，電子產品係以可程 核^ L制為曰曰片的韌體編程，來控制核心控制器晶片的各 - 個週邊裝置，以達到產品的功能要求。以往，核心控制； ' ㈣控制多項裝置時，各個裝置的位址線與控制線均須^ 接於核心控制器的接腳，利用不同接腳的控制資源來對各 個，置作控制或資料存取。由於核心控制器所控制的週邊 功能日益增加，所佔用的控制器接腳資源也隨之增加。為 了解決此一問題，適合短距傳輸的晶片間同步串列通信介 面（Inter-chip synchronous serial communicati〇n ―也⑹ 從而問世。 所述之同步串列介面包括有數條分別傳送時脈訊號與 串列貧料的傳輸線，核心控制器與執行週邊功能的從屬晶 片的相關接腳係同時耦接於該些傳輸線，按照個別位址來 完成晶片間的控制功能或資料存取。如此一來，便可大幅 減>主從控制器間的連接線數量。目前，微控制器所泛用 的晶片間同步串列通信介面包括有I2C ( Inter integrated circuit)、SPI ( Serial peripheral interface )與微線介面 (Microwire interface)等三種。 6 200907693 為- i ^ ί通=面中，i2c通信介面係被廣泛採用。此 為一、，泉式傳輪，包括一串列資料 ^ ^( Senal clock llne, SCL)〇 J > ic具有三種錢m財鮮料（/ =疋 可達100Kbps)、快i亲握4 寻输遠羊 盥古、'、式（封匕傳輸速率可達4〇〇Kbps) ”呵速杈式（封包傳輸速率可達3 4Mbps)。 有鑑於半導體製程與資料處理技術係日 ΐ處理器與微控制器的資料處理效能也隨之心而= 亦持續提升’因此，對於 速率要求係更進-步。由於！2目 j醫制—虎 的時序邏輯達到通訊效果，硬體電路 輪速率，提升電子產品的效能：==命令_ 本案。本發㈣提出織傳輸 ^ Λί系提7 ，式一_)與封包處理二：： Γ:ΓΓ與處理’俾使晶片系統的傳輪速率：幅‘ 升。此外，由於封包格式的簡化，使得處理傳 理封包的硬體設計成本大為降低。 、、处 【發明内容】 因此，本發明之目的係在於提供一種晶 方法’其藉由規範主控制器晶片與從屬晶片根據二 專屬串列軌協定組成訊號與傳輪訊號 器晶片與從屬晶片的訊號傳輸速率大幅提升。便件主匕制 。。曰t發明係揭示-種晶片系統，晶片系統包括—主控制 “片、至少-從屬晶片以及—傳輸介面。主控制器晶片 200907693 係產生一％脈訊號，從屬晶片 址之週邊功能以跡人 具有個別位 從屬晶片之間接於主控制器晶… 資料雜纽 有一資料線以及-時脈線， 貝枓線係耦接於主控制器晶片以及 f接於主控制器晶片以及從屬晶片：:;：二; 於、，以#據^疋組成訊號’並透過資料線雙向傳輸訊 裝置個別的位址，控制週邊功能裝置 戍理：控制ϋ晶片以及該從屬晶片具有個別的封包 =勺卞限狀減，主控制器晶片與從屬晶片個別之 =二幾制與有限狀態機係根據專屬串列通訊協定，控 =^工心晶片與從屬晶片間之訊號組成格式與訊號傳輸 二片與從屬晶片間之訊號傳輸類別包括有 μ ^、、—寫入模式、—主動讀取模式、-被動讀取 吴式、一重置模式以及一喚醒模式。 td金月再揭不一H虎傳輪方法，係適用於所述之晶 片糸統中該中斷模式的訊號傳輸。中斷模式之訊號傳輸方 驟係首先’主控制器晶片組成一中斷命令封包；其 :::艾組成一中斷回應封包傳輸至主控制器晶片，以回 應中斷命令封包的接收。 /本ι明再揭不—種訊號傳輸方法，係翻於所述之晶 ^系統中該寫人模式的訊號傳輸。寫人模式之訊號傳輸方 的步驟係首先，主控制器日日日片組成-寫人控制命令封 !:严主 =制器晶片將中斷命令封包傳輸至從屬晶片；最後， 200907693 =片其-人’主控制ϋ晶片將寫人控制命令封包傳輸至從屬 $明再揭示—種訊號傳輸方法，係適用於所述之曰 片糸射紅_取模式的域傳輸。主_取 曰曰 法的步驟係首先，主控繼晶片組成—讀^控: 二屬U次，主控制器晶片將讀取控制命令封包_ 本發明再揭示-種訊號傳輪方法，係適用於所述之曰 片糸統巾該被動讀取模式的職傳輸。被動讀取模s曰 號傳輸方法的㈣係首先，主控_晶片組成-中斷命1 次’主控制器晶片將中斷命令封包傳輸至從屬^ 片。、後’從屬晶片組成一中斷回應封包傳輪至主控制哭 晶片’以回應中斷命令封包的接收；最後，域制器晶片 組成-讀取控制命令封包傳輸至從屬晶片，以回應中斷回 應封包的接收。 本發明再揭示一種訊號傳輪方法，係適用於所述之晶 片系統中該重置模式的訊號傳輸。重置模式之訊號傳輸方 法的步驟係首先，主控㈣晶片組成_重置訊號傳輸至從 屬晶片；其次，主控制器晶片將重置訊號傳輸至從屬晶片。 本發明再揭示一種訊號傳輪方法，係適用於所述之晶 片系統中該喚醒模式的訊號傳輸。喚醒模式之訊號傳輸方 法的步驟係錢’從屬晶片組成—喚醒訊號；其次，從屬 晶片將喚醒訊號傳輸至主控制II晶片；最後，主控制器晶 片回復為正常模式操作’以回應於喚醒訊號的接收。 以上之概述與接下來的詳細說明及附圖，皆是為了能 9 200907693 進:步說明本發明為達成預定目的所採取之方式 、手段及 功效。而有關本發_其他目的及優點，將在後續的說明 及圖式中加以闇述。 [實施方式】 本，明所揭示之晶片系統及其訊號傳輸方法，係規範 主控制器晶片以及週邊從屬晶片根據—專屬串列通訊協定 組成訊號與傳輪訊號，以達成通訊之目的。 首先，請參閱第-圖，該圖係為本發明所揭示晶片系 統10之糸統架構示意圖。如第—圖所示，晶片系統1〇包 括有一主控制器晶片12、複數個從屬晶片141〜14N以及一 傳輸面16:傳輸介面16包括有—時脈線⑽） 曰:及)164，主控制器晶片12與從 別連接傳輪介面16之時脈線⑹以 及貝枓線164。主控制器晶片12係 示)，所述之主機係作為晶片系統1〇的主要二:圖中= =，於-電腦系統中，主機係指電腦之舉 =)器晶片12係指中央處理單元週邊之:：:，， 般而吕’主控制器晶片12當祜醋旱夕控制态，一 晶片141〜l4N可為主控制器 夕:制功能，而從屬 埠擴充晶片、馬達_ ° S日 所控制的通用輪出入 ，，-'動日日片與月光板驅動晶片等。 ασ八 n線164係雙向傳輸串列封包 與從屬晶片141〜14N根據控制 =端，以發送封包訊號到資料線164=:傳送 線164接收封句兮D备、， ス及攸貢料 匕錢，亚對接收到的封包訊號作回應。^ 200907693 片系統10中，主控制器晶片12係產生一時脈訊號，藉時 脈線162傳輸。於一具體實施例中，時脈訊號的頻率係與 主控制器晶片12系統時脈的頻率相同。舉例來說，倘若主 控制器晶片12的系統時脈頻率為16MHz，則時脈訊號的 頻率便為16MHz ’而時脈週期約為62‘5ns。從而，晶片系 統10的封包訊號傳輸速率便可提高為系統時脈頻率，而主 控制器晶片12與從屬晶片141〜14N之間的控制便得以更 形流暢與迅速。 —主控制器晶片12與從屬晶片141〜l4N内部均具有協 义引擎（Protocol engine)。所述之協定引擎係由韌體配合 ，體資源所共同構成，並根據—專屬串列通信協定的規 ，，來作封包的編、解碼，將晶片内部的命令訊號組成封 包心虎’及將接收到的封包訊號處理轉換為晶片内部的命 令訊號。 主控制器晶片12與每一從屬晶片141〜14N具有個別 你封^處理故制與有限狀態機（Finite §她臟咖狀，FSM ) 艮據此專屬串列通信龄的時序邏輯，控制主控制器晶 =2與從屬晶片141〜刚按照預定的訊框格式組成訊號 ^輸訊號。從屬日日日片⑷〜刚分別_並控制—或多個 功忐裝置’每-週邊功能裝置具有個別的位址 ddress)主控制||晶片12係對各個從屬晶片⑷〜刚 邊功症裝置定址，以便辨識封包訊號的正確來 履’，確保封包職送達正確目的地。 門沾曰曰It'充1〇中’主控制器晶片12與從屬晶片141〜14N 的訊號傳輪_包括有中斷模式、寫人模式、主動讀取 200907693 模式、被動讀取模式、重置模式與喚醒模式，其中主動讀 取模式為主控制器晶片12主動對從屬晶片141〜14N作讀 取動作；而被動讀取模式則是由從屬晶片141〜14N對主控 制器晶片12發送中斷要求，再由主控制器晶片12對從屬 晶片141〜14N作讀取，或由從屬晶片141〜14N直接對主控 制器晶片12作讀取。 以下便逐一介紹本發明之各種封包訊號格式。主控制 器晶片12所組成訊號的類別包括有中斷命令封包以及控 制命令封包。藉以對從屬晶片141〜14N及其個別所耦接之 週邊功能裝置下達中斷及讀寫控制。 請參閱第二圖，該圖係為主控制器晶片12端之控制命 令封包200之結構示意圖。如第二圖所示，控制命令封包 200為20位元。控制命令封包200包括有一起始位元（Start bit)210、一結束位元（Endbit)25〇 以及三攔位 22〇、23〇、 240。其中，起始位元21〇與結束位元250分別位於控制命 令封包200的第一位元與第二十位元，用以識別控制命令 封包200的完整性。攔位22〇為命令攔，以2位元來表示 控制模式為主動讀取模式或為寫入模式。於一具體實施 例，襴位220為〇 1表示控制命令封包2〇〇為一讀取控制命 7封包，攔位220為1〇表示控制命令封包2〇〇為一寫入控 制命令封包。欄位230為位址欄，以8位元來表示接受封 包訊號之目的地位址。攔位24〇為資料攔，以8位元來填 入控制命令資料。 〃 八％參閱第二圖，該圖係為主控制器晶片12端的中斷命 令封包300結構示意圖。如第三圖所示，中斷命令封包3卯 12 200907693 ^ 12位元。中斷命令封包300包括有一起始位元3i0、_ 位兀340以及二攔位320、330。其中，起始位元31〇 二、、’°束位元340分別位於中斷命令封包300的第一位元與 ' 〃位元’用以識別中斷命令封包300的完整性。搁j立 3為 令攔，攔位挪為2位元，用以定義控制模式 包係作中I於一具體實施例’欄位3 W〇即表示此封 甲斷控制。攔位330為位址攔，以8位元來表示中 令二t封包300的目的地位址。附帶一提的是，此中斷命 二似I 3〇〇的訊框格式亦可彈性作為主控制器晶片u對; 位141〜14N下達系統命令的訊框格式。若是將攔 令種類為〇〇解釋為系統命令，則攔位330則轉變為系統命 ^屬晶片141〜14N所組成的訊號類別包括有中斷回魔 所命令回應封包等訊號格式’以回應主控制器晶片「2 儀发〜的讀寫控制命令與中斷命令。請參閱第四圖，該圖 所二從屬晶片的命令回應封包4⑽結構示意圖。如第四圖 =，命令回應封包400為10位元。命令回應封包4〇〇包 始了起始位元410、一結束位元43〇以及—攔位42〇。起 第=疋410與結束位元43〇分別位於命令回應封包4〇〇的 〜位元與第十位元，用以識別命令回應封包400的完整 唑，而攔位420為資料攔，以8位元來填入資料。 加明參閱第五圖，該圖係為從屬晶片的中斷回應封包 〇〇之結構示意圖。如第五圖所*，中斷回應封包5〇〇為 0位元。中斷回應封包500包括有一起始位元510、一結 位兀530以及一欄位520。起始位元51〇與結束位元53〇 13 200907693 分別位於中斷回應封包500的第一位元與第十位元，用以 識別中斷回應封包500的完整性。於一具體實施例，每一 從屬晶片可具有八個週邊功能裝置。欄位520中每一位元 IRQ0〜IRQ7係代表一特定週邊功能裝置的中斷值，以顯示 裝置的中斷狀態。 以下便逐一說明本發明之訊號傳輸方法的中斷模式、 寫入模式、主動讀取模式、被動讀取模式、重置模式及喚 醒模式之步驟流程。 第一、中斷模式： 請參閱第六圖，該圖係為晶片系統10之中斷模式之步 驟流程圖。其中相關之系統架構請同時參閱第一圖，按， 以下從屬晶片的標號係以14作為代表標號。如第六圖所 示，該方法係始於主控制器晶片12於閒置狀態（步驟S 600 ) 時，基於韌體的控制，產生一中斷需求（步驟S602)。接 著，便根據欲進行中斷控制之週邊功能裝置位址，組成一 中斷命令封包（步驟S604)，並將此中斷命令封包傳輸到 控制此欲中斷之週邊功能裝置的從屬晶片14 (步驟 S606)。從屬晶片14根據週邊功能裝置的中斷值，組成一 中斷回應封包傳輸至主控制器晶片12,以回應中斷命令封 包的接收（步驟S608)。其後，主控制器晶片12再回到閒 置狀態（步驟S600)。 第二、寫入模式： 請參閱第七圖，該圖係為晶片系統10之寫入模式之步 驟流程圖。如第七圖所示，該方法係始於主控制器晶片12 於閒置狀態（步驟S700)時，基於韌體的控制，產生一寫 14 200907693 (步驟s則。接著，便根據欲寫人之週邊功 ^址，組成—寫人控制命令封包（步驟讓），並將此 =入控制命令封包傳輸到從屬晶片14(步驟讓）。 主控制器晶片12再回到閒置狀態（步驟議）。 從屬^ ^主控制器晶片12組成寫人控制命令封包傳輸至 j曰日片Η前，將根據中斷模式的步驟流程，對欲寫 以=置：中斷控制’以根據控制此週邊功能裝置之 命令料傳輸至從屬晶片14。心疋否組成寫入控制 第三、主動讀取模式： 請參閱第八圖，該圖係為晶片系統1〇之主 之步驟流程圖。如第八圖所示：核式 取!f j (步驟簡）時，基於韋刃體的控制，產生—讀 取兩求（步驟S802)。接著，主控制哭曰 °貝 取之週邊功能裝置位址，组成—日日片12便根據欲讀 S804)，並將巧取控制命令封包（步驟 «ss〇6) 斷是否須回應讀取二命令封包，判 若步驟S808的判斷^目，的接收（步驟S8〇8 )。倘 “靖為否，則回到步驟咖 片U進入閒置狀態；偶若步驟 控制為曰曰 ，組成-命令回應封包傳輪至主的二為二’則從屬 驟S810)。其後， 主，晶片U (步 S800)。 。〇日日片2再進入閒置狀態（步驟 又於主控制器晶片12組 從屬晶U4前，將根 令封包傳輸至 飞的步驟流程，對欲讀取之 15 200907693 叫以咖制此週邊功能裝置之 命令，傳輪至從屬决疋是否組成讀取控制 第四、被動讀取模式： 來之為從屬晶片14於收到主控制器晶片傳 回應封包成一:斷Γ崎 匕1寻翰至主控制器晶片12;接著，主曰 回應封包的内容與主動讀取模式的i驟=呈，= 控制命令封包傳輸至從屬晶片14，以回應中‘ 妾收；錢，從屬晶#14根據讀取控制命令封 i，判斷是否須回應讀取命令封包的接收，組成一命令回 應封包傳輪至主控制器晶片12。 σ 第五：重置模式： 本發明所揭示之專屬串列通訊協定係定義了主控制器 晶片12對所有從屬晶片141〜14Ν的重置（Reset)控制： 請參閱第九圖，該圖係為本發明所揭示之訊號傳輸方法之 重置模式時序圖，顯示出時脈訊號與重置訊號的時序關 係。時脈訊號與重置訊號係分別透過時脈線162與資料線 164傳輸，重置模式的步驟為主控制态晶片12組成一重置 訊號，並將此重置訊號傳輸至從屬晶片14。倘若資料線的 吊怨為而準位狀態’所述之重置§fl说可為持續N個時脈週 期的低準位訊號，其中Ν為一大於1的整數。第九圖的具 體實施例中，資料線164在常態為高準位狀態，當主控制 器晶片12重置從屬晶片時，係持續產生512至1024個時 脈週期的低準位訊號，從屬晶片141〜14N識別訊號型態為 16 200907693 重置訊號，便執行晶片重置程序。 第六：喚醒模式： /睛參閱第十圖’該圖係為主控制器晶片12的時脈產生 系統的系統架構示意圖。如第十圖所示，時脈產生系統12〇 包括有一多工器121及-除頻器Π3，多工器121可輸入 二時脈訊號咖卜CLK2。舉例來說，其時脈頻率分別為 32MHZ (高頻模式）及32KHz (低頻模式），輸入多工器 121的時脈訊號CLIU、CLK2係基於一致能訊號谢的邏 _，擇-輸出至除頻器]23作進一步頻率分割，以產生 一時脈訊號CLK輸出至時脈線162。 所述之專屬串列通訊協定係定義主控制器晶片具 有-正常模式及-省電模式，主控制器晶片12可於間置一 段時間後進人省電狀態，以節省電力消耗。於正常狀態下， 多工器121係基於致能訊號的邏輯值，選擇高頻模式 的時脈訊號CLK1輸出；於省電模式下，致能訊號厕將 轉變邏輯值，以控制多工H 121選擇低頻模式的時脈訊號 CLK2輸出。 喚醒模式之步驟首先係由從屬晶片14組成―喚醒訊 號傳輸到主控顧晶片12,社㈣器“ 12由省電模 式中喚S生，以回復正常模式操作。請同時參閱第十一圖， 該圖係為本發明所揭示之!孔號傳輪方法之喚醒時序圖，顯 示出喚醒模式下’時脈訊號CLK、喚醒訊號WAKE、中斷 訊號INT與致能訊號EN間的時序關係，其中時脈訊號CLK 由主控制器晶片12輸出，並藉時脈線162上傳輸；喚醒訊 號WAKE是由從屬晶片Η產生，並藉資料線164傳輸到 17 200907693 主控制器晶片12的訊號；中斷訊號INT為主控制器晶片 12内部接收到喚醒訊號WAKE後所產生中斷省電模=的 訊號；而致能訊號EN為主控制器晶片12内部所產生。 如第十一圖所示，致能訊號EN為高準位，此時，多 工器121將選擇32KHz的時脈訊號CLK2來產生時脈訊號 CLK，使得時脈訊號CLK以低頻模式輸出，以節省電力消 耗；當從屬晶片14產生持續一個時脈週期為低準位的喚醒 訊號WAKE輸出至主控制器晶片12後，主控制器晶片、12 内部係產生一中斷訊號INT中斷省電模式，主控制器晶片 12並回應令斷訊號1NT，將致能訊號£N的邏輯值由高準 4轉麦為低準位。致此訊號Εν邏輯值的轉變將控制^工 盗121選擇32ΜΗζ的時脈訊號CLK1來產生時脈訊號 (^LK，使得時脈訊號CLK以高頻模式輸出，以支援主控制 器晶片12的正常模式操作。 ^又，另一具體實施例中，主控制器晶片12於省電模式 下係中斷時脈訊號的輸出，從屬晶片14必須利用自行產生 的時脈訊號來支援喚醒訊號的產生與傳輸。 却以上實例詳述’當可知悉本發明之晶片系統及其 =傳輸方法中’主控制器晶片與從屬晶片係根據專屬串 蚊的規範來組成訊號與傳輸訊號，且本發明之專 化了封包訊號的結構，使得主控制器晶 虛★從屬晶片間得以快速地組成封包訊號，並快速地 傳二：3 :足而可依照主控制器晶片的系統時脈頻率來 使得晶片系統的傳輸速率大幅提升。此外， 、匕”㈣化亦將使得封包處理與傳輸機制的硬體設計 18 200907693 成本大為降低。 上所述，僅為本發_具體實施例之％ 及圖式而已，並非用以限制本發明，本笋之砰細說明 以下述之+料鄕圍鱗，任何熟錢 ^概園應 明之領域内，可輕易思及之變化或修飾皆可'、?：：在本發 案所界定之專利範圍。 自了涵盍在以下本 【圖式簡單說明】 圖；第-圖係為本發明所揭示之晶片系统之系統架構示意 圖；第二圖係為本發明所揭示之控制命令封包之結構示意 第三圖係為本發明所揭示之中斷命令封包之結構示意 圚， 第四圖係為本發明所揭示之命令回應封包之結構示意 圖； 第五圖係為本發明所揭示之中斷回應封包之結構示意 圖； 第六圖係為本發明所揭示之訊號傳輪方法之寫入模式 之步驟流程圖； '' ^第七圖係為本發明所揭示之訊號傳輪方法之主動讀取 模式之步驟流程圖； 苐八圖係為本發明所揭示之訊號傳輪方法之中斷模式 之步驟流程圖； 第九圖係為本發明所揭示之訊號傳輪方法之重置模式 19 200907693 時序圖； 式時序圖 〜抓示倂小思圃，以及 第十1係為本發明所齡之婦“傳輪方 醒模 【主要元件符號說明】 12〇 .時脈產生系統 123 :除頻器 16 .傳輪介面 164 1資料線 10:晶片系統 12:主控制器晶片 121 :多工器 起始位元 330 ' 420 520 :攔位 141〜MN :從屬晶片 162 :時脈線 200 .控制命令封包 210 、 310 、 410 、 510 220、230、240、320 250、340、430、530 :結束位元 300 :中斷命令封包 400 :命令回應封包 500 :中斷回應封包 CLK、CLK1、CLK2 :時脈訊號 EN :致能訊號 INT :中斷訊號 WAKE :喚醒訊號 20BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer system, and more particularly to a wafer system and a bean signal transmission method for composing signals and transmission signals according to a dedicated serial communication protocol. [Prior Art] The miniaturization and integration of electronic products is a current industry: (4) The goal sought. In general, electronic products are programmed with a firmware that can be used as a chip to control each peripheral device of the core controller chip to meet the functional requirements of the product. In the past, the core control; '(4) When controlling multiple devices, the address lines and control lines of each device must be connected to the pins of the core controller, and the control resources of different pins are used to control or store the data. take. As the peripheral functions controlled by the core controller increase, the controller pin resources occupied also increase. In order to solve this problem, an inter-chip synchronous serial communication interface (Inter-chip synchronous serial communication) is also available. The synchronous serial interface includes a plurality of separate transmission clock signals and strings. The transmission line of the column lean material, the core controller and the associated pin of the slave chip performing the peripheral function are simultaneously coupled to the transmission lines, and the control function or data access between the wafers is completed according to the individual address. It can greatly reduce the number of connections between the master and slave controllers. Currently, the inter-chip synchronous serial communication interface widely used by microcontrollers includes I2C (Inter Integrated Circuit), SPI (Serial Peripheral Interface) and microwire interface. (Microwire interface) and other three. 6 200907693 For - i ^ 通通 = face, i2c communication interface is widely used. This is a, spring pass, including a list of data ^ ^ ( Senal clock llne, SCL ) 〇J > ic has three kinds of money m rich materials (/ = 疋 up to 100Kbps), fast i pro-hold 4 to lose the distant sheep, ancient, ', type (sealing transmission rate up to 4 〇〇 Kbps) ” Fast-speed (packet transmission rate up to 34 Mbps). In view of the semiconductor processing technology and data processing technology, the data processing performance of the processor and microcontroller is also increasing. Therefore, for the rate requirement system More progress - step! Because 2 mesh j medical system - tiger's sequential logic to achieve communication effects, hardware circuit wheel speed, improve the efficiency of electronic products: == command _ this case. This issue (four) proposed woven transmission ^ Λ 系 7 , formula one _) and packet processing two:: Γ: ΓΓ and processing '俾 to make the wafer system transmission rate: amplitude ' liter. In addition, due to the simplification of the packet format, the hardware design cost of processing the transmission packet is greatly Therefore, the object of the present invention is to provide a crystal method by which a main controller chip and a slave wafer are configured to form a signal and a transmitter signal chip and a slave according to two exclusive serial rail protocols. The signal transmission rate of the wafer is greatly improved. The invention is disclosed. The invention system discloses a wafer system including a main control "chip, at least a slave wafer, and a transmission". interface. The main controller chip 200907693 generates a % pulse signal, and the peripheral function of the slave wafer address is connected to the main controller crystal by the individual bit slave wafers... The data has a data line and a clock line, the Bellow line The main controller chip is coupled to the main controller chip and the slave chip is connected to the main controller chip and the slave chip::; 2; and the signal is formed by the data channel and the individual addresses are transmitted through the data line to control the periphery. Functional device processing: the control chip and the slave chip have individual packets = scoop limit reduction, the main controller chip and the slave chip are individually = two systems and the finite state machine is based on the exclusive serial communication protocol, control = ^ work The signal composition format between the heart chip and the slave chip and the signal transmission between the two chips and the slave chip include μ ^, - write mode, active read mode, - passive read mode, and reset Mode and a wake mode. The td golden moon re-discloses the H-Tiger transmission method, which is applicable to the signal transmission of the interrupt mode in the above-mentioned wafer system. The signal transmission method of the interrupt mode is first: the main controller chip constitutes an interrupt command packet; its ::: an interrupt response packet is transmitted to the main controller chip to respond to the reception of the interrupt command packet. / This ι 明 再 再 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - The steps of the signal transmission side of the write mode are first, the main controller is composed of day and day film-write control command seal!: strict master = controller chip transmits the interrupt command packet to the slave wafer; finally, 200907693 = slice it - The human master control chip transmits the write control command packet to the subordinate $re-disclosed-type signal transmission method, which is applicable to the domain transmission of the slice transmission red_take mode. The main _ 曰曰 method is the first step, the main control chip composition - read control: two sub-U times, the main controller chip will read the control command packet _ the present invention re-disclosed - the signal transmission method, is applicable The transmission of the passive reading mode in the said cymbal cymbal. (4) of the passive read mode s 传输 传输 transmission method First, the master _ chip composition - interrupt life 1 'master controller chip transmits the interrupt command packet to the slave chip. After the 'subordinate wafers form an interrupt response packet transfer to the main control crying chip' in response to the receipt of the interrupt command packet; finally, the domain controller chip composition-read control command packet is transmitted to the slave wafer in response to the interrupt response packet. receive. The invention further discloses a signal transmission method suitable for signal transmission in the reset mode in the wafer system. The signal transmission method of the reset mode is first, the master (4) wafer composition_reset signal is transmitted to the slave wafer; secondly, the master controller chip transmits the reset signal to the slave wafer. The invention further discloses a signal transmission method suitable for signal transmission in the awake mode in the wafer system. The step of the signal transmission method of the awake mode is the 'subordinate wafer composition-wake-up signal; secondly, the slave wafer transmits the wake-up signal to the main control II chip; finally, the main controller chip returns to the normal mode operation' in response to the wake-up signal. receive. The above summary and the following detailed description and drawings are intended to illustrate the manner, means, and effects of the present invention in order to achieve the intended purpose. The other objects and advantages of the present invention will be further described in the following description and drawings. [Embodiment] The present invention discloses a wafer system and a signal transmission method thereof, which are characterized in that a main controller chip and a peripheral slave chip form a signal and a transmission signal according to a dedicated serial communication protocol to achieve a communication purpose. First, please refer to the first figure, which is a schematic diagram of the architecture of the wafer system 10 disclosed in the present invention. As shown in the first figure, the wafer system 1 includes a main controller chip 12, a plurality of slave chips 141 to 14N, and a transmission surface 16: the transmission interface 16 includes a clock line (10) 曰: and 164, the main The controller chip 12 is connected to the clock line (6) of the transfer interface 16 and the bellows line 164. The main controller chip 12 is shown), the main system is the main two of the wafer system 1: in the figure ==, in the computer system, the host refers to the computer = the device chip 12 refers to the central processing unit Peripheral:::,,General Lv' main controller chip 12 when the vinegar is in a dry state control state, a wafer 141~l4N can be the main controller eve: the function, and the subordinate 埠 expansion chip, motor _ ° S day The controlled universal wheel access, - 'moving the sun and the moon plate to drive the chip. Σσ8 n line 164 is a bidirectional transmission serial packet and the slave chips 141~14N are sent according to the control=end to send the packet signal to the data line 164=: the transmission line 164 receives the closed sentence 兮D,, ス and 攸 匕 匕, Asia responds to the received packet signal. ^ 200907693 In the slice system 10, the main controller chip 12 generates a clock signal, which is transmitted by the pulse line 162. In one embodiment, the frequency of the clock signal is the same as the frequency of the system clock of the main controller chip 12. For example, if the system clock frequency of the main controller chip 12 is 16 MHz, the frequency of the clock signal is 16 MHz' and the clock period is about 62 '5 ns. Thereby, the packet signal transmission rate of the wafer system 10 can be increased to the system clock frequency, and the control between the main controller chip 12 and the slave wafers 141 to 14N can be made smoother and faster. - The main controller chip 12 and the slave chips 141 to l4N each have a protocol engine. The protocol engine is composed of a firmware and a body resource, and according to the rules of the exclusive serial communication protocol, the coding and decoding of the packet are made, and the command signal inside the chip is composed of a package heart and a The received packet signal processing is converted into a command signal inside the chip. The main controller chip 12 and each of the slave chips 141 to 14N have individual timing processing and finite state machine (Finite § her dirty coffee, FSM), according to the serial logic of the exclusive serial communication age, control main control The transistor = 2 and the slave wafer 141 ~ have just formed a signal ^ signal in accordance with a predetermined frame format. Subordinate day and day film (4) ~ just separately _ and control - or multiple power devices - each peripheral function device has a separate address ddress) main control | | wafer 12 is for each slave wafer (4) ~ rigid edge device Addressing, in order to identify the correct access to the packet signal, to ensure that the package is delivered to the correct destination. The door is filled with the 'signal wheel of the main controller chip 12 and the slave chips 141~14N' including the interrupt mode, the write mode, the active read 200907693 mode, the passive read mode, and the reset mode. And the awake mode, wherein the active read mode is that the master controller chip 12 actively performs the read operation on the slave chips 141 to 14N; and the passive read mode is that the slave chips 141 14 14N send the interrupt request to the master controller chip 12, The slave controller wafers 12 are read by the master controller wafer 12 or the master controller wafers 12 are directly read by the slave wafers 141 to 14N. The various packet signal formats of the present invention are described below. The categories of signals composed by the main controller chip 12 include interrupt command packets and control command packets. Interrupt and read/write control is performed on the slave peripheral devices 141 to 14N and their respective peripheral functional devices. Please refer to the second figure, which is a schematic structural diagram of the control command packet 200 of the main controller chip 12 end. As shown in the second figure, the control command packet 200 is 20 bits. The control command packet 200 includes a start bit 210, an end bit 25 〇, and three blocks 22 〇, 23 〇, 240. The start bit 21 〇 and the end bit 250 are respectively located in the first bit and the twentieth bit of the control command packet 200 for identifying the integrity of the control command packet 200. The block 22 is a command bar, and the bit mode is 2 bits to indicate that the control mode is the active read mode or the write mode. In a specific embodiment, the clamp 220 is 〇1, and the control command packet 2 is a read control packet. The buffer 220 is 1 indicates that the control command packet 2 is a write control command packet. Field 230 is the address field, which represents the destination address of the packet signal in 8-bit units. Block 24 is a data block, and 8 bits are used to fill in the control command data.八 Eight% refers to the second figure, which is a schematic diagram of the structure of the interrupt command packet 300 on the 12th end of the main controller chip. As shown in the third figure, the interrupt command packet is 3卯 12 200907693 ^ 12 bits. The interrupt command packet 300 includes a start bit 3i0, a _ bit 340, and two stop bits 320, 330. The start bit 31 〇 2, and the '° bundle bit 340 are respectively located at the first bit and the 'bit' of the interrupt command packet 300 to identify the integrity of the interrupt command packet 300. The delay is 3, and the block is moved to 2 bits to define the control mode. In the case of a specific embodiment, the field 3 W 表示 indicates that the control is broken. Block 330 is the address block, and the destination address of the medium 2 t packet 300 is represented by 8 bits. Incidentally, the frame format of the interrupted I3 is also flexible as the main controller chip u pair; the bits 141~14N issue the frame format of the system command. If the interception type is interpreted as a system command, the intercept 330 is converted into a signal type consisting of the system 141~14N, including a signal format such as an interrupted echo command response packet, in response to the main control. The chip "2" sends and receives the read/write control command and the interrupt command. Please refer to the fourth figure, which shows the structure of the command response packet 4 (10) of the slave chip. As shown in the fourth figure, the command response packet 400 is 10 bits. The command response packet 4 packet starts the start bit 410, an end bit 43〇, and the -block 42. The first = 410 and the end bit 43 are respectively located in the command response packet 4 The bit and the tenth bit are used to identify the complete azole of the command response packet 400, and the block 420 is the data block, and the data is filled with octets. See Figure 5 for the slave wafer. The structure of the interrupt response packet is as shown in the fifth figure. The interrupt response packet 5 is 0. The interrupt response packet 500 includes a start bit 510, a node 530, and a field 520. Start bit 51〇 and end bit 53〇13 200907693 is located in the first and tenth bits of the interrupt response packet 500, respectively, for identifying the integrity of the interrupt response packet 500. In one embodiment, each slave wafer may have eight peripheral functional devices. Field 520 Each bit IRQ0~IRQ7 represents the interrupt value of a specific peripheral function device to display the interrupt status of the device. The following describes the interrupt mode, write mode, active read mode, passive mode of the signal transmission method of the present invention one by one. Step flow of read mode, reset mode and wake mode. First, interrupt mode: Please refer to the sixth figure, which is a flow chart of the interrupt mode of the wafer system 10. Please refer to the related system architecture. In the figure, the label of the following slave wafer is denoted by 14 as a representative label. As shown in the sixth figure, the method starts from the firmware control based on the firmware of the main controller wafer 12 in the idle state (step S600). An interrupt request is generated (step S602). Then, an interrupt command packet is formed according to the peripheral function device address to be interrupt-controlled (step S604). And transmitting the interrupt command packet to the slave chip 14 controlling the peripheral function device to be interrupted (step S606). The slave chip 14 is configured to transmit an interrupt response packet to the main controller chip 12 according to the interrupt value of the peripheral function device, to Responding to the receipt of the interrupt command packet (step S608). Thereafter, the main controller chip 12 returns to the idle state (step S600). Second, the write mode: Please refer to the seventh figure, which is the wafer system 10 A flow chart of the steps of the write mode. As shown in the seventh figure, the method starts when the main controller chip 12 is in the idle state (step S700), and based on the firmware control, generates a write 14 200907693 (step s. Then, according to the peripheral location of the person to be written, the composition-write control command packet (step is made), and the = control command packet is transmitted to the slave wafer 14 (step let). The main controller chip 12 is returned to the idle state (step negotiation). The slave ^ ^ master controller chip 12 is composed of a write control command packet transmitted to the j 曰 Η , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The material is transferred to the slave wafer 14. The heartbeat does not constitute the write control. Third, the active read mode: Please refer to the eighth figure, which is a flow chart of the steps of the wafer system. As shown in the eighth figure: when the nucleus takes !f j (step simplification), based on the control of the blade body, the read-and-see two requests are made (step S802). Then, the main control cries the location of the peripheral function device, which consists of - the day film 12 is based on the S804), and the control command packet (step «ss〇6) is broken to respond to the read command. The packet is received as determined by the judgment of step S808 (step S8〇8). If "Jing Wei is no, then return to step coffee U to enter the idle state; even if the step control is 曰曰, the composition - command response packet transmission to the main two is two" then subordinates S810). Thereafter, the main, The wafer U (step S800). The next day, the film 2 is re-entered into an idle state (the step is to transfer the root packet to the fly before the slave controller U4 of the main controller chip, and the process to be read is 15 200907693 Calling the command of the peripheral function device, whether the slave to the slave decides whether to form the read control fourth or passive read mode: the slave chip 14 receives the response packet from the master controller chip into one: Rugged 1 search for the main controller chip 12; then, the main response packet content and active read mode i = =, = control command packet is transmitted to the slave wafer 14, in response to the 'received; money, The slave crystal #14 determines whether it is necessary to respond to the reception of the read command packet according to the read control command seal i, and constitutes a command response packet transfer to the main controller chip 12. σ Fifth: reset mode: disclosed in the present invention Exclusive serial communication protocol Reset control of the master controller chip 12 to all the slave chips 141~14Ν: Please refer to the ninth figure, which is a reset mode timing diagram of the signal transmission method disclosed in the present invention, showing the clock The timing relationship between the signal and the reset signal. The clock signal and the reset signal are transmitted through the clock line 162 and the data line 164, respectively. The reset mode step forms a reset signal for the main control state chip 12, and the weight is added. The signal is transmitted to the slave wafer 14. If the data line is blamed, the reset state §fl is said to be a low level signal for N clock cycles, where Ν is an integer greater than one. In the specific embodiment of the ninth embodiment, the data line 164 is in a high-level state in the normal state. When the main controller chip 12 resets the slave wafer, the low-level signal of 512 to 1024 clock cycles is continuously generated, and the slave is slave. The wafers 141 to 14N recognize the signal type as 16 200907693 reset signal, and execute the wafer reset procedure. Sixth: wake mode: / eye refers to the tenth figure 'This figure is the clock generation system of the main controller chip 12 System architecture diagram As shown in the tenth figure, the clock generation system 12A includes a multiplexer 121 and a frequency divider Π3, and the multiplexer 121 can input two clock signals CLK2. For example, the clock frequency is respectively For 32 MHz (high frequency mode) and 32 KHz (low frequency mode), the clock signals CLIU and CLK2 of the input multiplexer 121 are based on the logic signal of the uniform energy signal, and the output is output to the frequency divider] 23 for further frequency division. The output of the clock signal CLK is output to the clock line 162. The exclusive serial communication protocol defines that the main controller chip has a normal mode and a power saving mode, and the main controller chip 12 can enter the space after being placed for a period of time. Power saving state to save power consumption. In the normal state, the multiplexer 121 selects the clock signal CLK1 output of the high frequency mode based on the logic value of the enable signal; in the power saving mode, the enable signal toilet will change the logic value to control the multiplex H 121 Select the clock signal CLK2 output of the low frequency mode. The step of waking up mode is firstly composed of the slave wafer 14 - the wake-up signal is transmitted to the master control chip 12, and the social (four) device "12 calls the S mode in the power saving mode to resume the normal mode operation. Please also refer to the eleventh figure. The figure is a wake-up timing diagram of the hole number transmission method, and shows the timing relationship between the clock signal CLK, the wake-up signal WAKE, the interrupt signal INT and the enable signal EN in the awake mode, wherein The pulse signal CLK is output from the main controller chip 12 and transmitted on the clock line 162; the wake-up signal WAKE is generated by the slave chip and transmitted to the signal of the main controller chip 12 by the data line 164; the interrupt signal INT The main controller chip 12 internally receives the wake-up signal WAKE and generates a signal for interrupting the power-saving mode =; and the enable signal EN is generated inside the main controller chip 12. As shown in FIG. 11, the enable signal EN At a high level, at this time, the multiplexer 121 will select the 32KHz clock signal CLK2 to generate the clock signal CLK, so that the clock signal CLK is output in the low frequency mode to save power consumption; when the slave wafer 14 is generated After the wake-up signal WAKE with a low clock period is output to the main controller chip 12, the main controller chip and the 12 internal system generate an interrupt signal INT interrupt power saving mode, and the main controller chip 12 responds with a disconnection signal 1NT. The logic value of the enable signal £N is changed from the Micro Motion 4 to the low level. The transition of the signal Εν logic value will control the work thief 121 to select the 32 ΜΗζ clock signal CLK1 to generate the clock signal (^LK The clock signal CLK is output in a high frequency mode to support the normal mode operation of the main controller chip 12. Further, in another embodiment, the main controller chip 12 interrupts the clock signal in the power saving mode. Output, the slave chip 14 must use the self-generated clock signal to support the generation and transmission of the wake-up signal. However, the above example details 'when the wafer system and the method of transmitting the same are known, the master controller chip and the slave wafer are known. The signal and the transmission signal are composed according to the specification of the exclusive mosquito, and the structure of the packet signal is specialized in the invention, so that the main controller is imaginary and the slave wafer can quickly form a packet signal. And quickly pass two: 3: enough to follow the system clock frequency of the main controller chip to greatly increase the transfer rate of the wafer system. In addition, 匕" (four) will also make the hardware of the packet processing and transmission mechanism Design 18 200907693 The cost is greatly reduced. The above is only the % and the drawings of the present invention, and is not intended to limit the present invention, and the details of the bamboo shoots are described below. In the field of cooked money, the park should be able to easily think about changes or modifications. '::: The scope of patents defined in this case. Since the following is a brief description of the drawings; The first diagram is a schematic diagram of the system architecture of the wafer system disclosed in the present invention; the second diagram is the structure diagram of the control command packet disclosed by the present invention. The third diagram is a schematic diagram of the structure of the interrupt command packet disclosed in the present invention. The fourth figure is a schematic structural diagram of the command response packet disclosed by the present invention; the fifth figure is a schematic structural diagram of the interrupt response packet disclosed by the present invention; the sixth figure is the disclosure of the present invention. Flowchart of the step of writing mode of the transfer method; ''The seventh figure is a flow chart of the steps of the active read mode of the signal transmission method disclosed by the present invention; FIG. 8 is a signal disclosed by the present invention Step-by-step flowchart of the interrupt mode of the transmission method; The ninth diagram is the reset mode of the signal transmission method disclosed in the present invention 19 200907693 Timing diagram; the timing diagram ~ grasping the small thinking, and the tenth For the woman of the age of the invention, the transmission wheel wake-up mode [main component symbol description] 12〇. Clock generation system 123: frequency divider 16. Transmission interface 164 1 data line 10: wafer system 12: main controller chip 121: Multiplexer start bit 330 '420 520: Block 141~MN: slave wafer 162: clock line 200. Control command packets 210, 310, 410, 510 220, 230, 240, 320 250, 340, 430, 530: End bit 300: Interrupt command packet 400: Command response packet 500: Interrupt response packet CLK, CLK1, CLK2: Clock signal EN: Enable signal INT: Interrupt signal WAKE: Wake signal 20