CN107634001B - 一种ldmos器件的制造方法 - Google Patents

一种ldmos器件的制造方法 Download PDF

Info

Publication number
CN107634001B
CN107634001B CN201710716395.9A CN201710716395A CN107634001B CN 107634001 B CN107634001 B CN 107634001B CN 201710716395 A CN201710716395 A CN 201710716395A CN 107634001 B CN107634001 B CN 107634001B
Authority
CN
China
Prior art keywords
region
layer
transistor
gate
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710716395.9A
Other languages
English (en)
Other versions
CN107634001A (zh
Inventor
柳志亨
乔伊·迈克格雷格
艾瑞克·布劳恩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Monolithic Power Systems Co Ltd
Original Assignee
Chengdu Monolithic Power Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu Monolithic Power Systems Co Ltd filed Critical Chengdu Monolithic Power Systems Co Ltd
Publication of CN107634001A publication Critical patent/CN107634001A/zh
Application granted granted Critical
Publication of CN107634001B publication Critical patent/CN107634001B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0882—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明提出了一种制造半导体器件的方法，包括：在半导体衬底内的具有第一掺杂类型的阱区上形成阻隔层，所述阻隔层具有用于定义位于阱区上层部分的第一区域的窗口，且具有位于窗口两边的侧壁；通过阻隔层的窗口向阱区内注入具有第二掺杂类型的杂质，形成第一区域；采用大角度倾斜的杂质注入，向第一区域内注入具有第一掺杂类型的杂质，形成用于第一晶体管的第二区域，及用于第二晶体管的第三区域；以及形成位于第二区域和第三区域之间的、用于第一晶体管与第二晶体管的第四区域。

Description

一种LDMOS器件的制造方法
技术领域
本发明涉及半导体器件，更具体地说，本发明涉及减小半导体器件源极区的方法。
背景技术
LDMOS器件因其高击穿电压、大电流及良好的温度特性而广泛应用于笔记本电脑、服务器和DC/DC电压转换电路。
LDMOS器件通常包含若干对晶体管。图1示出了LDMOS器件的剖面图，包含一对形成于N型阱区16内部的晶体管T1和T2。每个晶体管都包含漏极接触区11、源极区12、栅极13，同时这对晶体管共享了同一个体区14和体接触区15。出于对性能和成本的考虑，现在许多应用场合都要求封装更小的功率器件。为了得到更小的功率器件，大量的研究关注于减小漏极区尺寸的工艺，例如降低表面电场RESURF(Reduced Surface Field)及梯度掺杂漏极(Graded Dope Drain)等。而有一部分研究则关注于减小源极区的工艺。如图1所示，源极/体区内包含位于中心的体接触区15和分布在体接触区两边的源极区12，从而形成一个N+/P+/N+区域，减小该N+/P+/N+区域可减小源极区。但N+/P+/N+的最小面积通常会受到光掩模设备性能的限制。
发明内容
本发明的目的是提供一种工艺，该工艺采用大角度倾斜的杂质注入，取代传统的光掩模工序，以形成较小的源极区。在大角度倾斜的杂质注入过程中，注入方向与垂直于LDMOS器件栅极水平面的方向之间形成一定的夹角。因此，本发明减小了LDMOS器件的源极区。
本发明的实施例旨在提供一种制造半导体器件的工艺流程，包括：在半导体衬底内形成具有第一掺杂类型的阱区；在阱区上形成栅极绝缘层；在栅极绝缘层上形成栅极层；在栅极层上形成掩膜层，所述掩膜层具有一个窗口，所述窗口用于定义位于阱区上层部分的体区；通过掩膜层的窗口，对栅极层进行刻蚀至栅极层被穿通，栅极层在被刻蚀后具有位于体区上方的侧壁；通过掩膜层的窗口，向阱区注入具有第二掺杂类型的杂质，形成体区；采用大角度倾斜的杂质注入工序，且栅极层和掩膜层作为此过程中的阻隔层，向体区注入具有第一掺杂类型的杂质，形成第一晶体管与第二晶体管各自的源极区；移除掩膜层；形成第一晶体管与第二晶体管各自的栅极；形成第一晶体管与第二晶体管各自的漏极接触区；以及形成第一晶体管与第二晶体管各自的体接触区。
本发明的实施例旨在提供一种制造半导体器件的方法，包括：在半导体衬底内的具有第一掺杂类型的阱区上形成阻隔层，所述阻隔层具有用于定义位于阱区上层部分的第一区域的窗口，且具有位于窗口两边的侧壁；通过阻隔层的窗口向阱区内注入具有第二掺杂类型的杂质，形成第一区域；采用大角度倾斜的杂质注入，向第一区域内注入具有第一掺杂类型的杂质，形成用于第一晶体管的第二区域，及用于第二晶体管的第三区域；以及形成位于第二区域和第三区域之间的、用于第一晶体管与第二晶体管的第四区域。
本发明的实施例旨在提供一种制造LDMOS器件的工艺流程，所述LDMOS器件包含第一晶体管与第二晶体管，包括：在半导体衬底内形成阱区；在阱区上形成栅极绝缘层；在栅极绝缘层上形成栅极层；在栅极层上形成栅极密封层顶部；在栅极密封层顶部形成第一掩膜层；通过第一掩膜层的窗口，对栅极密封层顶部和栅极层进行刻蚀至其穿通，以暴露出位于阱区上层部位的体区的区域表面，其中栅极层具有位于体区上方的侧壁；通过第一掩膜层的窗口，将P型杂质注入至阱区，在阱区上层部位形成体区；采用大角度倾斜的杂质注入工序，将N型杂质注入体区，形成第一晶体管与第二晶体管各自的源极区，此过程中栅极绝缘层、栅极层、栅极密封层顶部与第一掩膜层作为阻隔层；移除第一掩膜层；在半导体衬底上形成第二掩膜层；通过第二掩膜层的窗口，对栅极层进行蚀刻，形成用于第一晶体管的第一栅极，及用于第二晶体管的第二栅极；移除第二掩膜层；在半导体衬底上形成第三掩膜层；通过第三掩膜层的窗口，向阱区注入N型杂质，形成用于第一晶体管的第一漏极接触区，及用于第二晶体管的第二漏极接触区；移除第三掩膜层；在半导体衬底上形成第四掩膜层；通过第四掩膜层的窗口，向阱区注入P型杂质，形成用于第一晶体管与第二晶体管的体接触区；以及移除第四掩膜层。
附图说明
为了更好的理解本发明，将根据以下附图对本发明的实施例进行描述。这些附图仅用于示意说明，相似的部分具有相似的数字标号。附图仅示出器件的部分特征，并且不一定按照比例进行绘制，附图的尺寸和比例可能与实际的尺寸和比例不一致。
图1示出了现有的LDMOS器件的剖面图；
图2示出了现有的制造LDMOS器件的工艺流程概要图；
图3a-3b示出了采用传统光掩模工艺所形成的源极区12a和12b以及体接触区15的剖面图；
图4a-4g示出了根据本发明一实施例的制造具有小源极区的LDMOS器件的工艺流程；
图5示出了根据本发明一实施例的制造图4a-4g所示出的LDMOS器件的工艺流程概要图。
具体实施方式
下面将详细描述本发明的具体实施例。应当理解的是，这些实施例只用于举例说明，并不用于限制本发明。相反地，本发明应当涵盖替代、修改和等效等方式，这些方式可能在附加的权利要求所定义的精神和范围之内。另外，在以下描述中，为了提供对本发明的透彻理解，阐述了大量特定细节。然而，对于本领域普通技术人员显而易见的是：不必采用这些特定细节来实行本发明。在其他实例中，为了避免混淆本发明，未具体描述公知的电路、材料或方法。
说明书和权利要求书中表示方位的用语，例如“左““右”“里”“外”“前”“后”“上”“下”“顶部”“底部”“正上方”“正下方”等，只用于描述，并不意味着这些相对位置是永久不变的。应当理解的是，以上术语在适当的情况下是可以互换的，从而使得相应的实施例可以在其它方向上正常工作。
图2示出了现有的制造LDMOS器件的工艺流程概要图。该现有工艺可包括以下步骤：前端工序、薄栅氧层形成、多晶硅层淀积、栅极区掩膜工序、多晶硅层刻蚀、掩膜层移除、多晶硅栅氧化、体区掩膜工序、体区注入、掩膜层移除、N+区掩膜工序、源极/漏极区注入、掩膜层移除、P+区掩膜工序、体接触区注入、掩膜层移除和后端工序。前端工序可包括：准备初始衬底、形成N型埋层、生长外延层和定义有源区。在一些应用中，前端工序还包括形成厚栅氧层。后端工序可包括：形成源极区电极、形成漏极区电极、形成体接触区电极、形成栅极电极和分布金属层。本领域普通技术人员应当知道，掩膜工序，也称作光掩膜工序，意味着形成具有若干窗口的掩膜层，这些窗口对应于半导体衬底上表面的特定区域。例如，体区掩膜工序包括以下步骤：在半导体衬底上形成掩膜层；对掩膜层进行显影，暴露出通向体区的窗口。掩膜可包括光刻胶。
由图2可知，体区、体接触区和源极/漏极区通过传统的光掩模和杂质注入工艺形成。因此，源极/体区的窗口大小，即图1中所示出的N+/P+/N+区显然会受到光掩膜设备性能的限制。更不利的是，光掩模工艺不能精确控制被注入的区域。图3a与图3b示出了采用传统光掩模工艺所形成的源极区12a和12b以及体接触区15的剖面图。在图3a中，具有开口17a与17b的掩膜层17形成于半导体衬底之上。由于对准误差，开口17a与开口17b可能沿方向R偏离于位于栅极13中央的轴线X-X’，因而相对于轴线X-X’是不对称的。如图3a所示，通过开口17a与17b将杂质注入体区14之后，源极区12a的宽度w1大于源极区12b的宽度w2。如图3b所示，在用于定义体接触区15的光掩膜工序中，用于定义体接触区15的开口18a可能沿与方向R相反的方向L偏离于轴线X-X’，杂质注入后，所形成的的体接触区15会偏离于栅极13，并且比预期狭窄。这是由于开口18a与源极区12a有所重叠，且重叠区域表现为N型。
图4a-4g示出了根据本发明一实施例的制造具有较小源极区的LDMOS器件的工艺流程，其中包含一道大角度倾斜的杂质注入的工序，以形成位于体区两侧的两个源极区。本领域普通技术人员在阅读本发明后，可以利用该工艺流程制造任何其他具有类似结构的半导体器件。
图4a示出了半导体衬底401。半导体衬底401包含初始衬底418、N型掩埋层(NBL)419、外延层420与阱区421，其中阱区421也被称为漏极漂移区。初始衬底418可以为N型、P型或本征半导体材料。N型掩埋层419可以用其他结构替代。外延层420可以为N型、P型或本征半导体材料。阱区421可以为轻掺杂的高压阱区。所述LDMOS器件形成于阱区421之内。半导体衬底401还可能集成其他电路、器件或系统。例如，在BCD(Bipolar-CMOS-DMOS)工艺中，双极型晶体管(BJT，Bipolar Junction Transistor)、互补型金属氧化物半导体器件(CMOS，Complementary Metal Oxide Semiconductor)等其他多种器件可能与LDMOS器件一起集成于同一衬底内。在一些实施例中，半导体衬底401可能具有其他构造，或不具有上述的部分区域。在图4a中，栅极绝缘层402形成于半导体衬底401之上，并被用作介质层。栅极绝缘层402可包含硅氧化物，并由氧化工序或氧化物淀积工序所形成。接下来，多晶硅层通过淀积形成于栅极绝缘层402之上，此多晶硅层即为栅极层403，在后续工序中，栅极层403将被刻蚀为LDMOS器件的栅极。接下来，栅极密封层顶部404T通过多晶硅氧化工序或者氧化物淀积工序形成于栅极密封层403之上。之后，第一掩膜层406通过光刻工序形成于栅极密封层顶部404T之上。第一掩膜层406包含至少一个通向栅极密封层顶部404T上表面的窗口OP1，以定义N阱421中的体区。窗口OP1也被称为体区窗口，可通过对第一掩膜层406进行曝光后溶解第一掩膜层406上特定的区域而形成。在一个实施例中，窗口OP1的宽度d1为0.3微米到0.5微米。为清晰起见，在图4b-4g中，初始衬底418、N型埋层419与外延层420并未示出。
图4b中，栅极层403在窗口OP1下的部分被刻蚀，从而暴露出由栅极绝缘层402所覆盖着的阱区421中对应体区的区域表面。之后，P型杂质通过窗口OP1被注入至阱区421的上层部分，以形成第一区域，即体区407。从图4b可以看出，被刻蚀后的栅极层403具有位于体区407上方的侧壁403S。
图4c中，紧接着以上工序，大角度倾斜的杂质注入工序被依次实施，以形成第二区域与第三区域，即第一晶体管T1的源极区411a与第二晶体管T2的源极区411b，这里第一晶体管T1和第二晶体管T2是组成LDMOS器件的若干晶体管中的一对晶体管。如图4c所示，在每道大角度倾斜的杂质注入工序中，N型杂质的注入方向与侧壁403S形成夹角α。该角度α也称为倾斜角，这是由于角度α是通过倾斜整片晶圆同时保持注入方向垂直于水平方向形成的。
在大角度倾斜的杂质注入工序中，栅极层403和第一掩膜层406组成了一层阻止杂质注入的阻隔层。栅极密封层顶部404T非常薄，因此可以忽略不计。在一个实施例中，包含栅极层403和第一掩膜层406的阻隔层的厚度、窗口OP1的宽度d1和角度α被定义，使得每个源极区的宽度d2小于0.15微米。在一个实施例中，包含栅极层403和第一掩膜层406的阻隔层的厚度、窗口OP1的宽度d1和角度α被定义，使得每个源极区的宽度d2在0.1微米和0.15微米之间。
在一个实施例中，包含栅极层403和第一掩膜层406的阻隔层可能还有其他层。在其他实施例中，该阻隔层可能包含任意一层用于杂质注入的硬质掩膜。该硬质掩膜阻隔层具有一个预先定义好的窗口，以阻止杂质注入到未定义的区域。
在一个实施例中，角度α在15度和30度之间。在包含栅极层403和第一掩膜层406的阻隔层的厚度，以及窗口OP1的宽度d1不变的情况下，角度α越大，源极区411a和411b的宽度就越小。换言之，源极区411a与411b的宽度d2可以通过改变角度α来进行调整。在一些实施例中，源极区411a与411b并不一定具有相同的宽度，这是因为形成源极区411a和411b的大角度倾斜的杂质注入工序可以采用不同的倾斜角度α。
该大角度倾斜的杂质注入工序精确控制源极区，并且没有对准误差。另外，可以通过改变角度α来控制源极区的宽度，因此相较于传统光掩模工艺所形成的源极区，大角度倾斜的杂质注入工艺所形成的的源极区要窄得多。
图4d中，第一掩膜层406被移除。第二掩膜层412形成于半导体衬底401之上。如图4d所示，第二掩膜层412具有若干通向栅极层403的窗口，来定义晶体管T1和T2的栅极。
图4e中，栅极层403中位于第二掩膜层412的窗口下的部分被刻蚀穿通，形成晶体管T1和T2的栅极422。之后，第二掩膜层412被移除，同时一道氧化工序可能被实施，以完整形成如图4f所示的栅极密封层404，从而包裹住栅极422，其中栅极密封层顶部404T是栅极密封层404的一部分。
图4f中，形成第三掩膜层413。第三掩膜层413包含位置确定的窗口OP2，以定义晶体管T1和T2的漏极接触区414。通过窗口OP2，N型杂质被注入至阱区421，形成漏极接触区414。之后，第三掩膜层413被移除。
图4g中，形成第四掩膜层418。第四掩膜层418包含位置确定的窗口OP3，以定义第四区域，即晶体管T1和T2的体接触区409。通过窗口OP3，P型杂质被注入至体区407，形成体接触区409。之后，第四掩膜层418被移除。
如图4g所示，用于定义体接触区409的窗口OP3与源极区411a与411b重叠。本领域普通技术人员应当知道，当半导体区域中同时掺杂有浓度相近的N型和P型杂质，该区域最终表现为N型半导体。因此，体接触区409是由其一旁的源极区所决定，只要精确形成源极区，且窗口OP3与源极区411a与411b重叠，体接触区409便可无误差自行对齐。
图5示出了根据本发明一实施例的制造图4a-4g所示出的LDMOS器件的工艺流程概要图。相较于图2所示出的现有技术，本发明采用大角度倾斜的杂质注入工艺，将栅极层和掩膜层用作阻隔层，来形成源极区。因此，相对于图2所示的现有技术，不同区域的形成顺序有所调整。通过调整晶圆的倾斜角度，或者调整杂质注入的方向，本发明所形成的源极区的宽度可以被控制在0.1微米和0.15微米之间，此宽度相较于现有技术所制造的LDMOS器件的源极区宽度要窄得多。
应当知道的是，本发明的掩膜层可以包含任何合适的材料层，例如光刻胶层。本领域普通技术人员应当知道，LDMOS器件可以包含不止一对晶体管，可以在制作晶体管T1与T2的同时，以相同的工序制作其他晶体管。
尽管图4a-4g示出的是制造LDMOS器件的工艺流程，本发明也适用于形成任何其他合适的半导体器件，其中包含通过阻隔层的窗口进行大角度倾斜的杂质注入的步骤。
本领域普通技术人员应当知道，每个区域的掺杂类型可以替换，例如N型掺杂区可以用P型掺杂区替代，与此同时P型掺杂区用N型掺杂区替代。在如权利要求书所述的一个实施例中，第一掺杂类型为N型而第二掺杂类型为P型。在另一个实施例中，第一掺杂类型为P型而第二掺杂类型为N型。
N型杂质可在以下物质中择一：氮、磷、砷、锑、铋以及它们的组合。同时，P型杂质可在以下物质中择一：硼、铝、镓、铟、铊以及它们的组合。
根据以上教导，本发明的许多更改和变型方式显然也是可行的。因此，应当理解的是，在权利要求所限定的范围内，本发明可以不用按照上述特定的描述来实施。同样应当理解的是，上述公开只涉及到本发明一些优选实施例，在不脱离本发明权利要求所限定的精神和范围的前提下，可以对本发明作出更改。当只有一个优选实施例被公开，本领域普通技术人员不难想到改型并将其付诸于实施，而不脱离于本发明权利要求所限定的精神与范围。

Claims (10)

1.一种制造半导体器件的工艺流程，包括：
在半导体衬底内形成具有第一掺杂类型的阱区；
在阱区上形成栅极绝缘层；
在栅极绝缘层上形成栅极层；
在栅极层上形成掩膜层，所述掩膜层具有一个窗口，所述窗口用于定义位于阱区上层部分的体区；
通过掩膜层的窗口，对栅极层进行刻蚀至栅极层被穿通，栅极层在被刻蚀后具有位于体区上方的侧壁；
通过掩膜层的窗口，向阱区注入具有第二掺杂类型的杂质，形成体区；
采用大角度倾斜的杂质注入工序，且栅极层和掩膜层作为此过程中的阻隔层，向体区注入具有第一掺杂类型的杂质，形成第一晶体管与第二晶体管各自的源极区，其中，控制所述大角度倾斜的杂质注入工序，使得第一晶体管与第二晶体管各自的源极区相互不重叠；
移除掩膜层；
形成第一晶体管与第二晶体管各自的栅极；
形成第一晶体管与第二晶体管各自的漏极接触区；以及
形成第一晶体管与第二晶体管各自的体接触区。
2.如权利要求1所述的制造半导体器件的工艺流程，其中大角度倾斜的杂质注入工序被依次实施以形成第一晶体管与第二晶体管各自的源极区，且在每道大角度倾斜的杂质注入工序中，注入方向与栅极层的侧壁之间的夹角在15度到30度之间。
3.如权利要求1所述的制造半导体器件的工艺流程，在大角度倾斜的杂质注入工序中，阻隔层的厚度、用于定义体区的窗口的宽度以及注入方向与栅极层的侧壁之间的夹角都被定义，使得每个源极区的宽度都小于0.15微米。
4.如权利要求1所述的制造半导体器件的工艺流程，在大角度倾斜的杂质注入工序中，阻隔层的厚度、用于定义体区的窗口的宽度以及注入方向与栅极层的侧壁之间的夹角都被定义，使得每个源极区的宽度都在0.1微米与0.15微米之间。
5.如权利要求1所述的制造半导体器件的工艺流程，其中大角度倾斜的杂质注入工序被依次实施以形成第一晶体管与第二晶体管各自的源极区，且在先后两次大角度倾斜的杂质注入工序中，注入方向与栅极的侧壁之间的夹角不相同。
6.一种制造半导体器件的方法，包括：
在半导体衬底内的具有第一掺杂类型的阱区上形成阻隔层，所述阻隔层具有用于定义位于阱区上层部分的第一区域的窗口，且具有位于窗口两边的侧壁；
通过阻隔层的窗口向阱区内注入具有第二掺杂类型的杂质，形成第一区域；
采用大角度倾斜的杂质注入，向第一区域内注入具有第一掺杂类型的杂质，形成用于第一晶体管的第二区域，及用于第二晶体管的第三区域，其中，控制所述大角度倾斜的杂质注入工序，使得所述第二区域与第三区域相互不重叠；以及
形成位于第二区域和第三区域之间的、用于第一晶体管与第二晶体管的第四区域。
7.如权利要求6所述的方法，其中：
第一晶体管与第二晶体管包含横向扩散型金属氧化物半导体器件，且第一区域包含体区，第二区域与第三区域包含源极区，第四区域包含体接触区。
8.如权利要求6所述的方法，其中大角度倾斜的杂质注入工序被依次实施，以形成用于第一晶体管的第二区域，及用于第二晶体管的第三区域，且在每道大角度倾斜的杂质注入工序中，注入方向与栅极层的侧壁之间的夹角在15度到30度之间。
9.一种制造LDMOS器件的工艺流程，所述LDMOS器件包含第一晶体管与第二晶体管，包括：
在半导体衬底内形成阱区；
在阱区上形成栅极绝缘层；
在栅极绝缘层上形成栅极层；
在栅极层上形成栅极密封层顶部；
在栅极密封层顶部形成第一掩膜层；
通过第一掩膜层的窗口，对栅极密封层顶部和栅极层进行刻蚀至其穿通，以暴露出位于阱区上层部位的体区的区域表面，其中栅极层具有位于体区上方的侧壁；
通过第一掩膜层的窗口，将P型杂质注入至阱区，在阱区上层部位形成体区；
采用大角度倾斜的杂质注入工序，将N型杂质注入体区，形成第一晶体管与第二晶体管各自的源极区，此过程中栅极绝缘层、栅极层、栅极密封层顶部与第一掩膜层作为阻隔层，其中，控制所述大角度倾斜的杂质注入工序，使得第一晶体管与第二晶体管各自的源极区相互不重叠；
移除第一掩膜层；
在半导体衬底上形成第二掩膜层；
通过第二掩膜层的窗口，对栅极层进行蚀刻，形成用于第一晶体管的第一栅极，及用于第二晶体管的第二栅极；移除第二掩膜层；
在半导体衬底上形成第三掩膜层；
通过第三掩膜层的窗口，向阱区注入N型杂质，形成用于第一晶体管的第一漏极接触区，及用于第二晶体管的第二漏极接触区；
移除第三掩膜层；
在半导体衬底上形成第四掩膜层；
通过第四掩膜层的窗口，向阱区注入P型杂质，形成用于第一晶体管与第二晶体管的体接触区；以及
移除第四掩膜层。
10.如权利要求9所述的制造LDMOS器件的工艺流程，在大角度倾斜的杂质注入工序中，注入方向与栅极层的侧壁之间的夹角在15度到30度之间。
CN201710716395.9A 2016-11-18 2017-08-18 一种ldmos器件的制造方法 Active CN107634001B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/356,515 2016-11-18
US15/356,515 US9941171B1 (en) 2016-11-18 2016-11-18 Method for fabricating LDMOS with reduced source region

Publications (2)

Publication Number Publication Date
CN107634001A CN107634001A (zh) 2018-01-26
CN107634001B true CN107634001B (zh) 2020-10-30

Family

ID=61101239

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710716395.9A Active CN107634001B (zh) 2016-11-18 2017-08-18 一种ldmos器件的制造方法

Country Status (2)

Country Link
US (1) US9941171B1 (zh)
CN (1) CN107634001B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102359373B1 (ko) * 2018-06-11 2022-02-08 에스케이하이닉스 시스템아이씨 주식회사 고전압 반도체소자의 제조방법
CN111430243B (zh) * 2020-05-11 2023-05-16 杰华特微电子股份有限公司 半导体器件的制造方法及半导体器件
US11069777B1 (en) 2020-06-09 2021-07-20 Monolithic Power Systems, Inc. Manufacturing method of self-aligned DMOS body pickup
CN111987165B (zh) * 2020-08-25 2022-09-20 杰华特微电子股份有限公司 横向双扩散晶体管的制造方法
US11282959B2 (en) 2020-07-17 2022-03-22 Monolithic Power Systems, Inc. FET device insensitive to noise from drive path
CN112151618B (zh) * 2020-09-27 2022-09-20 杰华特微电子股份有限公司 横向超结结构的制造方法
CN114361244B (zh) * 2022-03-18 2022-05-27 北京芯可鉴科技有限公司 Ldmosfet器件、制作方法及芯片

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7713853B2 (en) * 2005-07-08 2010-05-11 Stmicroelectronics S.R.L. Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices
CN102097327A (zh) * 2009-12-02 2011-06-15 万国半导体股份有限公司 双通道沟槽ldmos晶体管和bcd工艺

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5817551A (en) * 1995-08-25 1998-10-06 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
US6049104A (en) * 1997-11-28 2000-04-11 Magepower Semiconductor Corp. MOSFET device to reduce gate-width without increasing JFET resistance
US6252278B1 (en) 1998-05-18 2001-06-26 Monolithic Power Systems, Inc. Self-aligned lateral DMOS with spacer drift region
US6825543B2 (en) * 2000-12-28 2004-11-30 Canon Kabushiki Kaisha Semiconductor device, method for manufacturing the same, and liquid jet apparatus
US6756637B2 (en) * 2001-07-06 2004-06-29 International Business Machines Corporation Method of controlling floating body effects in an asymmetrical SOI device
EP2259327B1 (en) * 2002-11-14 2014-04-02 STMicroelectronics Srl Insulated gate power semiconductor device with Schottky diode and manufacturing method thereof
US6900101B2 (en) * 2003-06-13 2005-05-31 Texas Instruments Incorporated LDMOS transistors and methods for making the same
US7125777B2 (en) * 2004-07-15 2006-10-24 Fairchild Semiconductor Corporation Asymmetric hetero-doped high-voltage MOSFET (AH2MOS)
KR100629605B1 (ko) * 2004-12-31 2006-09-27 동부일렉트로닉스 주식회사 엘디모스 채널 형성 방법
JP4956351B2 (ja) * 2007-09-28 2012-06-20 オンセミコンダクター・トレーディング・リミテッド Ｄｍｏｓトランジスタの製造方法
US7732863B2 (en) * 2008-05-13 2010-06-08 Texas Instruments Incorporated Laterally diffused MOSFET
CN101593703B (zh) * 2009-04-22 2013-12-04 上海宏力半导体制造有限公司 金属氧化物半导体场效应晶体管的制造方法及其器件
JP2011066158A (ja) * 2009-09-16 2011-03-31 Toshiba Corp 半導体装置およびその製造方法
US8546879B2 (en) * 2011-08-18 2013-10-01 Monolithic Power Systems, Inc. High density lateral DMOS with recessed source contact
US9159795B2 (en) 2013-06-28 2015-10-13 Monolithic Power Systems, Inc. High side DMOS and the method for forming thereof
US9087774B2 (en) * 2013-09-26 2015-07-21 Monolithic Power Systems, Inc. LDMOS device with short channel and associated fabrication method
US9502251B1 (en) 2015-09-29 2016-11-22 Monolithic Power Systems, Inc. Method for fabricating low-cost isolated resurf LDMOS and associated BCD manufacturing process
US9935176B1 (en) * 2016-11-18 2018-04-03 Monolithic Power Systems, Inc. Method for fabricating LDMOS using CMP technology

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7713853B2 (en) * 2005-07-08 2010-05-11 Stmicroelectronics S.R.L. Method for manufacturing electronic devices integrated in a semiconductor substrate and corresponding devices
CN102097327A (zh) * 2009-12-02 2011-06-15 万国半导体股份有限公司 双通道沟槽ldmos晶体管和bcd工艺

Also Published As

Publication number Publication date
CN107634001A (zh) 2018-01-26
US9941171B1 (en) 2018-04-10

Similar Documents

Publication Publication Date Title
CN107634001B (zh) 一种ldmos器件的制造方法
TWI392086B (zh) 具有堆疊異質摻雜邊緣及漸進漂移區域之改良式減少表面場的高壓ｐ型金屬氧化半導體裝置
US8772871B2 (en) Partially depleted dielectric resurf LDMOS
US20200146945A1 (en) Lateral mosfet with buried drain extension layer
US12074215B2 (en) Semiconductor device and semiconductor device manufacturing method
KR101099907B1 (ko) 금속 산화물 반도체 장치와 그의 형성 방법 및 집적 회로
US5684319A (en) Self-aligned source and body contact structure for high performance DMOS transistors and method of fabricating same
US20150279969A1 (en) Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A Stacked Gate "BUMP" Structure
US20160087083A1 (en) Semiconductor device and method of fabricating same
US9893170B1 (en) Manufacturing method of selectively etched DMOS body pickup
JP2010040975A (ja) 半導体装置およびその製造方法
US20050236677A1 (en) Semiconductor device layout and channeling implant process
CN106653612B (zh) 一种采用化学机械抛光技术制造ldmos器件的方法
US8748980B2 (en) U-shape RESURF MOSFET devices and associated methods of manufacturing
US9105712B1 (en) Double RESURF LDMOS with separately patterned P+ and N+ buried layers formed by shared mask
US20090170259A1 (en) Angled implants with different characteristics on different axes
KR101987811B1 (ko) 고 전압 mosfet과 이의 제조방법
US20190207001A1 (en) Semiconductor device and method of manufacturing the same
US9793375B2 (en) High voltage lateral DMOS transistor with optimized source-side blocking capability
US9543149B2 (en) High voltage lateral extended drain MOS transistor with improved drift layer contact
US10396174B2 (en) STI-diode structure
US11069777B1 (en) Manufacturing method of self-aligned DMOS body pickup
JP7252094B2 (ja) 半導体装置及びトランジスタ
CN111725319B (zh) 半导体器件及其制造方法
US10727063B2 (en) Methods of fabricating high voltage semiconductor devices

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB03 Change of inventor or designer information
CB03 Change of inventor or designer information

Inventor after: Liu Zhiheng

Inventor after: Joey McGregor

Inventor after: Ai Ruike.bulaoen

Inventor before: Liu Zhiheng

Inventor before: Joey McGregor

GR01 Patent grant
GR01 Patent grant