CN107622948A - A kind of FinFET and preparation method, electronic installation - Google Patents
A kind of FinFET and preparation method, electronic installation Download PDFInfo
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Abstract
The present invention relates to a kind of FinFET and preparation method, electronic installation.Methods described includes providing Semiconductor substrate, formed with Seed Layer in the Semiconductor substrate；Repeatedly alternate in the Semiconductor substrate and the Seed Layer to form semiconductor material layer and the oxide skin(coating) with opening, the semiconductor material layer fills the opening in the oxide skin(coating) below, wherein the opening is alignd with the Seed Layer；Etching catalyst layer is formed in said opening；Chemical etching is performed by auxiliary of the catalyst layer, removes the semiconductor material layer below the catalyst layer, oxide stratotype fin is inserted to be formed.Methods described can ensure that the I FinFETs of the more large ratio of height to width (High aspect ratio) are against damages, insertion oxide skin(coating) fin in the I FinFETs for making to be prepared has good profile, so as to improve the performance of the semiconductor devices and yield.
Description
Technical field
The present invention relates to technical field of semiconductors, is filled in particular to a kind of FinFET and preparation method, electronics
Put.
Background technology
With the continuous development of semiconductor technology, the raising of performance of integrated circuits is mainly by constantly reducing integrated circuit
The size of device is to improve its speed to realize.At present, due to the demand of high device density, high-performance and low cost, half
Conductor industry has advanced to nanometer technology process node, and the preparation of semiconductor devices is limited by various physics limits.
With the continuous diminution of cmos device size, the challenge from manufacture and design aspect has promoted three dimensional design such as fin
The development of gate fin-fet (FinFET).Relative to existing planar transistor, FinFET is to be used for 20nm and following work
The advanced semiconductor device of skill node, its can effectively control device it is scaled caused by the short channel for being difficult to overcome effect
Answer, the density of the transistor array formed on substrate can also be effectively improved, meanwhile, the grid in FinFET is around fin
(fin-shaped channel) is set, therefore can control electrostatic from three faces, and the performance in terms of Electrostatic Control is also more prominent.
Oxide FinFET (Inserted-oxide FinFET, I FinFET) device is wherein inserted in off-state current
(Ioff) be proved to better performance in terms of absolute value, therefore how it is significantly more efficient prepare the I FinFETs into
To solve the problems, such as at present.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In order to overcome the problem of presently, there are, the invention provides a kind of preparation method of FinFET, methods described
Including：
Semiconductor substrate is provided, formed with Seed Layer in the Semiconductor substrate；
It is repeatedly alternate in the Semiconductor substrate and the Seed Layer to form semiconductor material layer and there is opening
Oxide skin(coating), the opening in the oxide skin(coating) of semiconductor material layer filling below, wherein the opening with
The Seed Layer alignment；
Etching catalyst layer is formed in said opening；
Chemical etching is performed by auxiliary of the catalyst layer, removes the semi-conducting material below the catalyst layer
Layer, oxide stratotype fin is inserted to be formed.
Alternatively, the semiconductor material layer includes III-V semiconductor material layer.
Alternatively, the semiconductor material layer is formed by the method for transversal epitaxial growth.
Alternatively, the Seed Layer selects layer of InP.
Alternatively, the Seed Layer is removed simultaneously in the chemical etching.
Alternatively, methods described still further comprises after removing the semiconductor material layer below the catalyst layer
The step of removing the catalyst layer.
Alternatively, methods described still further comprises the step of reducing the oxide skin(coating) lateral dimension, so that the oxygen
The lateral dimension of compound layer is less than the lateral dimension of the semiconductor material layer.
Alternatively, the first semiconductor material layer, first are alternately formed in the Semiconductor substrate and the Seed Layer
Oxide skin(coating), the second semiconductor material layer, the second oxide skin(coating), the 3rd semiconductor material layer and trioxide layer.
Alternatively, forming the method for the Seed Layer includes：
The Semiconductor substrate is provided, forms the mask layer with opening on the semiconductor substrate；
Using the mask layer as Semiconductor substrate described in mask etch, to form groove；
The Seed Layer is formed in the trench.
Present invention also offers a kind of FinFET, the device is prepared by the above method, the device bag
Include Semiconductor substrate and the insertion oxide stratotype fin in the Semiconductor substrate；
The insertion oxide stratotype fin includes semiconductor material layer and oxide skin(coating) that multilayer is alternatively formed.
Alternatively, the top of the insertion oxide stratotype fin is the oxide skin(coating).
Alternatively, the bottom of the insertion oxide stratotype fin is the oxide skin(coating).
Alternatively, the lateral dimension of the oxide skin(coating) is less than the lateral dimension of the semiconductor material layer.
Present invention also offers a kind of electronic installation, the electronic installation includes above-mentioned FinFET.
In order to solve problem present in current technique, the invention provides one kind to insert oxide skin(coating) FinFET
The preparation method of (Inserted-oxide FinFET, I-FinFET), sequentially forms the oxidation with opening in the process
Nitride layer and semiconductor material layer, wherein having opening in the oxide skin(coating), the semiconductor material layer filling opening is simultaneously
The oxide skin(coating) of lower section is covered, then passes through metal assisted chemical etch method (Metal-Assisted Chemical
Etching method) removes the semiconductor material layer in the opening, wherein the metal assisted chemical etch method
(Metal-Assisted Chemical Etching) has the selectivity of height, so as to which more large ratio of height to width be prepared
(High-aspect-ratio) I-FinFET devices, it is often more important that pass through the metal assisted chemical etch method
(Metal-Assisted Chemical Etching) can also ensure the more large ratio of height to width (High-aspect-ratio)
I-FinFET devices it is against damages, there is the insertion oxide skin(coating) fin in the I-FinFET devices that are prepared good
Profile, so as to improve the performance of the semiconductor devices and yield.
The insertion oxide skin(coating) FinFET of the present invention, as a result of above-mentioned manufacture method, thus equally have upper
State advantage.The electronic installation of the present invention, as a result of above-mentioned insertion oxide skin(coating) FinFET, thus equally have above-mentioned
Advantage.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 shows the preparation technology flow chart of insertion oxide skin(coating) FinFET of the present invention；
Fig. 2 a-2h show that the preparation method of insertion oxide skin(coating) FinFET of the present invention is implemented to be obtained successively
The diagrammatic cross-section of structure；
Fig. 3 shows the schematic diagram of electronic installation according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be element or layer between two parties.On the contrary, when element be referred to as " on directly existing ... ", " with ... direct neighbor ", " be directly connected to
To " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although art can be used
Language first, second, third, etc. describe various elements, part, area, floor and/or part, these elements, part, area, floor and/or portion
Dividing to be limited by these terms.These terms are used merely to distinguish an element, part, area, floor or part and another
Element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, part, area,
Floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with it is other
The relation of element or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of with
The different orientation of device in operation.For example, if the device upset in accompanying drawing, then, is described as " below other elements "
Or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to explain this
Invent the technical scheme proposed.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this hair
It is bright to have other embodiment.
In order to solve above mentioned problem present in current technique, the invention provides one kind to insert oxide skin(coating) FinFET devices
The preparation method of part, methods described include：
Semiconductor substrate is provided, formed with Seed Layer in the Semiconductor substrate；
It is repeatedly alternate in the Semiconductor substrate and the Seed Layer to form semiconductor material layer and there is opening
Oxide skin(coating), the opening in the oxide skin(coating) of semiconductor material layer filling below, wherein the opening with
The Seed Layer alignment；
Etching catalyst layer is formed in said opening；
Chemical etching is performed by auxiliary of the catalyst layer, removes the semi-conducting material below the catalyst layer
Layer, oxide stratotype fin is inserted to be formed.
Wherein, the chemical etching in the present invention is metal assisted chemical etch method (Metal-Assisted
Chemical Etching), i.e., Seed Layer is formed in the bottom of etching, then sequentially form material to be etched, eventually form
Metal level, chemical etching, the metal assisted chemical etch method are carried out on the premise of the metal level is as catalyst
(Metal-Assisted Chemical Etching) has the selectivity of height, so as to which more large ratio of height to width be prepared
(High-aspect-ratio) I-FinFET devices, it is often more important that pass through the metal assisted chemical etch method
(Metal-Assisted Chemical Etching) can also ensure the more large ratio of height to width (High-aspect-ratio)
I-FinFET devices it is against damages, there is the insertion oxide skin(coating) fin in the I-FinFET devices that are prepared good
Profile, so as to improve the performance of the semiconductor devices and yield.
Specifically, the Seed Layer selects layer of InP in the present invention, but is not limited to the example.
Wherein, the catalyst layer includes metal level, such as can select Au, but be not limited to that the example.
Wherein, the metal assisted chemical etch method (Metal-Assisted Chemical Etching) is to described
Seed Layer and the Semiconductor substrate and the metal level have very big etching selectivity, are removing the mistake of the Seed Layer
The Semiconductor substrate and the metal level will not be had any impact in journey.
H can be selected in this step2SO4And H2O2In one or more reacted as reaction solution, to remove
State the semiconductor material layer in opening.
Wherein, the etching of the metal assisted chemical etch method (Metal-Assisted Chemical Etching)
Temperature can be room temperature.
System can be made by the metal assisted chemical etch method (Metal-Assisted Chemical Etching)
The depth-width ratio (High-aspect-ratio) of the fin of standby obtained insertion oxide skin(coating) reaches 45:More than 1, but also can be with
Ensureing the fin profile of the insertion oxide skin(coating) has good performance, and profile defects will not occur, described so as to improve
The performance and yield of semiconductor devices.
Alternatively, the semiconductor material layer includes III-V semiconductor material layer.
Wherein described III-V semiconductor material layer has the following advantages that：
(1) process costs are relatively small, inexpensively many compared to SOI pieces；
(2) due to using germanium, III-V substrate, so the mobility ratio of device is higher, therefore larger open can be obtained
State electric current, wherein the ratio of the ON state current and off-state current can reach 106More than；
(3) can effective adjusting means threshold voltage.
Wherein described III-V semiconductor material layer refers to include the 3rd main group IIIA and the 5th in the periodic table of chemical element
Main group VA semi-conducting material, such as InGaAs etc., but the species of specific semi-conducting material and composition can be according to realities
Border needs to be selected.
Wherein, the semiconductor material layer can be crystal structure, and the scope of its lattice constant is not limited to a certain number
It is worth scope.
Further, the semiconductor material layer can be formed by the method for transversal epitaxial growth (ELOG).
Wherein, the performance of the III-V semiconductor material layer formed by the transversal epitaxial growth (ELOG) is more
It is excellent, it can further improve the performance and yield of the semiconductor devices.
In order to solve above mentioned problem present in current technique, the invention provides one kind to insert oxide skin(coating) FinFET devices
The preparation method of part (Inserted-oxide FinFET, I-FinFET), sequentially forms the oxidation of patterning in the process
Nitride layer and semiconductor material layer, wherein having opening in the oxide skin(coating), the semiconductor material layer filling opening is simultaneously
The oxide skin(coating) of lower section is covered, then passes through metal assisted chemical etch method (Metal-Assisted Chemical
Etching method) removes the semiconductor material layer in the opening, wherein the metal assisted chemical etch method
(Metal-Assisted Chemical Etching) has the selectivity of height, so as to which more large ratio of height to width be prepared
(High-aspect-ratio) I-FinFET devices, it is often more important that pass through the metal assisted chemical etch method
(Metal-Assisted Chemical Etching) can also ensure the more large ratio of height to width (High-aspect-ratio)
I-FinFET devices it is against damages, there is the insertion oxide skin(coating) fin in the I-FinFET devices that are prepared good
Profile, so as to improve the performance of the semiconductor devices and yield.
The insertion oxide skin(coating) FinFET of the present invention, as a result of above-mentioned manufacture method, thus equally have upper
State advantage.The electronic installation of the present invention, as a result of above-mentioned insertion oxide skin(coating) FinFET, thus equally have above-mentioned
Advantage.
Embodiment one
The preparation method of the insertion oxide skin(coating) FinFET of the present invention is done in detail below with reference to Fig. 1 and Fig. 2 a-2h
Description, Fig. 1 show the preparation technology flow chart of insertion oxide skin(coating) FinFET of the present invention；Fig. 2 a-2h are shown
The preparation method of insertion oxide skin(coating) FinFET of the present invention implements the diagrammatic cross-section of obtained structure successively.
The present invention provides a kind of preparation method for inserting oxide skin(coating) FinFET, as shown in figure 1, the preparation method
Key step includes：
Step S1：Semiconductor substrate is provided, formed with Seed Layer in the Semiconductor substrate；
Step S2：It is repeatedly alternate in the Semiconductor substrate and the Seed Layer to form semiconductor material layer and have
The oxide skin(coating) of opening, the semiconductor material layer fills the opening in the oxide skin(coating) below, wherein described
Opening is alignd with the Seed Layer；
Step S3：Etching catalyst layer is formed in said opening；
Step S4：Chemical etching is performed by auxiliary of the catalyst layer, removes described half below the catalyst layer
Conductor material layer, oxide stratotype fin is inserted to be formed.
Below, to the present invention insertion oxide skin(coating) FinFET preparation method embodiment do it is detailed
Explanation.
First, step 1 is performed, there is provided Semiconductor substrate 201, on the semiconductor substrate formed with opening
Mask layer 202.
Specifically, as shown in Figure 2 a, the Semiconductor substrate can be in the following material being previously mentioned in this step
It is at least one：Silicon, silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, is laminated SiGe (S- on insulator
SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Semiconductor substrate selects silicon in this embodiment.
Hard mask layer is formed on the semiconductor substrate, wherein, the hard mask, which is used to schedule in subsequent step, to be formed
The formation of Seed Layer 203.
The hard mask layer selects oxide skin(coating), and the oxide skin(coating) can select conventional oxide, such as SiO2。
The hard mask layer is patterned to form bottom opening, such as forms the photoresist layer of patterning, with photoresist layer
For hard mask layer described in mask etch, N can be selected in this step2In conduct etching atmosphere, it can also be added simultaneously
Its a small amount of gas such as CF4、CO2、O2, the etching pressure can be 50-200mTorr, preferably 100-150mTorr, power
For 200-600W, the etching period is 5-80s, more preferably 10-60s in the present invention, while in the present invention from larger
Gas flow, alternatively, in N of the present invention2Flow be 30-300sccm, for example, 50-100sccm.
Step 2 is performed, using the mask layer as Semiconductor substrate described in mask etch, to form groove, in the groove
Middle formation Seed Layer 203.
Specifically, as shown in Figure 2 b, the Seed Layer 203 selects layer of InP in the present invention, but is not limited to described show
Example.
The metal assisted chemical etch method (Metal- that wherein described Seed Layer 203 is used in subsequent step
Assisted Chemical Etching)。
Wherein, the metal assisted chemical etch method (Metal-Assisted Chemical Etching) is to described
Seed Layer and the Semiconductor substrate and the metal level have very big etching selectivity, are removing the mistake of the Seed Layer
The Semiconductor substrate and the metal level will not be had any impact in journey.
System can be made by the metal assisted chemical etch method (Metal-Assisted Chemical Etching)
The depth-width ratio (High-aspect-ratio) of the fin of standby obtained insertion oxide skin(coating) reaches 45:More than 1, but also can be with
Ensureing the fin profile of the insertion oxide skin(coating) has good performance, and profile defects will not occur, described so as to improve
The performance and yield of semiconductor devices.
Step 3 is performed, semiconductor material layer is formed on the mask layer and the Seed Layer 203, to be covered described in covering
Film layer and the Seed Layer.
Specifically, as shown in Figure 2 c, formed on the mask layer and the Seed Layer and cover the mask layer and described
The semiconductor material layer of Seed Layer.
Alternatively, the semiconductor material layer includes III-V semiconductor material layer.
Wherein described III-V semiconductor material layer has the following advantages that：
(1) process costs are relatively small, inexpensively many compared to SOI pieces；
(2) due to using germanium, III-V substrate, so the mobility ratio of device is higher, therefore larger open can be obtained
State electric current, wherein the ratio of the ON state current and off-state current can reach more than 106；
(3) can effective adjusting means threshold voltage.
Wherein described III-V semiconductor material layer refers to include the 3rd main group IIIA and the 5th in the periodic table of chemical element
Main group VA semi-conducting material, such as InGaAs etc., but the species of specific semi-conducting material and composition can be according to realities
Border needs to be selected.
Wherein, the semiconductor material layer can be crystal structure, and the scope of its lattice constant is not limited to a certain number
It is worth scope.
Further, the semiconductor material layer can be formed by the method for transversal epitaxial growth (ELOG).
Wherein, the performance of the III-V semiconductor material layer formed by the transversal epitaxial growth (ELOG) is more
It is excellent, it can further improve the performance and yield of the semiconductor devices.
Step 4 is performed, is repeatedly alternatively formed the oxide skin(coating) with opening and the semiconductor material layer, wherein, it is described
The semiconductor material layer filling opening simultaneously covers the corresponding oxide skin(coating).
Specifically, the first semiconductor material layer 204, the first oxide are sequentially formed in the Seed Layer in the present invention
Layer 205, as shown in Figure 2 d.
Then, be subsequently formed the second semiconductor material layer 206, the second oxide skin(coating) 207, the 3rd semiconductor material layer 208,
Trioxide layer 209, as shown in Figure 2 e.
Wherein, first semiconductor material layer 204, the second semiconductor material layer 206 and the 3rd semiconductor material layer 208
Select III-V semiconductor material layer.
Wherein described III-V semiconductor material layer refers to include the 3rd main group IIIA and the 5th in the periodic table of chemical element
Main group VA semi-conducting material, such as InGaAs etc., but the species of specific semi-conducting material and composition can be according to realities
Border needs to be selected.
Wherein, the semiconductor material layer can be crystal structure, and the scope of its lattice constant is not limited to a certain number
It is worth scope.
Step 5 is performed, etching catalyst layer 210 is formed in the oxide at top and the opening.
Specifically, as shown in figure 2f, wherein, the catalyst layer 210 includes metal level, such as can select Au, still
It is not limited to the example.
Wherein, the metal assisted chemical etch method (Metal-Assisted Chemical Etching) is to described
Seed Layer and the Semiconductor substrate and the metal level have very big etching selectivity, are removing the mistake of the Seed Layer
The Semiconductor substrate and the metal level will not be had any impact in journey.
Step 6 is performed, chemical etching is performed by auxiliary of the catalyst layer, it is (i.e. described to remove below catalyst layer
In opening) the semiconductor material layer, formed insertion oxide skin(coating) fin.
Specifically, as shown in Figure 2 g, etching removes the semi-conducting material in the opening in the chemical etching
Layer and the Seed Layer, while the catalyst layer in the opening is displaced downwardly in the Semiconductor substrate.
Wherein, the chemical etching in the present invention is metal assisted chemical etch method (Metal-Assisted
Chemical Etching), i.e., Seed Layer is formed in the bottom of etching, then sequentially form material to be etched, eventually form
Metal level, chemical etching, the metal assisted chemical etch method are carried out on the premise of the metal level is as catalyst
(Metal-Assisted Chemical Etching) has the selectivity of height, so as to which more large ratio of height to width be prepared
(High-aspect-ratio) I-FinFET devices, it is often more important that pass through the metal assisted chemical etch method
(Metal-Assisted Chemical Etching) can also ensure the more large ratio of height to width (High-aspect-ratio)
I-FinFET devices it is against damages, there is the insertion oxide skin(coating) fin in the I-FinFET devices that are prepared good
Profile, so as to improve the performance of the semiconductor devices and yield.
Specifically, the Seed Layer selects layer of InP in the present invention, but is not limited to the example.
Wherein, the catalyst layer includes metal level, such as can select Au, but be not limited to that the example.
Wherein, the metal assisted chemical etch method (Metal-Assisted Chemical Etching) is to described
Seed Layer and the Semiconductor substrate and the metal level have very big etching selectivity, are removing the mistake of the Seed Layer
The Semiconductor substrate and the metal level will not be had any impact in journey.
H can be selected in this step2SO4And H2O2In one or more reacted as reaction solution, to remove
State the semiconductor material layer in opening.
Wherein, the etching of the metal assisted chemical etch method (Metal-Assisted Chemical Etching)
Temperature can be room temperature.
System can be made by the metal assisted chemical etch method (Metal-Assisted Chemical Etching)
The depth-width ratio (High-aspect-ratio) of the fin of standby obtained insertion oxide skin(coating) reaches 45:More than 1, but also can be with
Ensureing the fin profile of the insertion oxide skin(coating) has good performance, and profile defects will not occur, described so as to improve
The performance and yield of semiconductor devices.
Step 7 is performed, removes the catalyst layer.
Specifically, as shown in fig. 2h, the minimizing technology, which can be selected, with the Semiconductor substrate there is larger etching to select
Select than method.
Perform step 8, the step of reducing the oxide skin(coating) size so that the size of the oxide skin(coating) be less than it is described
The size of semiconductor material layer.
Specifically, as shown in fig. 2h, etch-back is carried out to the oxide skin(coating), to trim the oxide skin(coating), and then subtracted
The step of small oxide skin(coating) size, so that the size of the oxide skin(coating) is less than the size of the semiconductor material layer.
Methods described still further comprises the step to form all around gate after the fin of the insertion oxide skin(coating) is formed
Suddenly.
So far, the correlation step of the preparation method of the insertion oxide skin(coating) FinFET of the embodiment of the present invention is completed
Introduce.The step of methods described can also include forming transistor and other correlation steps, here is omitted.Also, remove
Outside above-mentioned steps, the preparation method of the present embodiment can also include among above-mentioned each step or between different steps
Other steps, these steps can realize that here is omitted by the various techniques in current technique.
In order to solve above mentioned problem present in current technique, the invention provides one kind to insert oxide skin(coating) FinFET devices
The preparation method of part (Inserted-oxide FinFET, I-FinFET), sequentially forms the oxidation of patterning in the process
Nitride layer and semiconductor material layer, wherein having opening in the oxide skin(coating), the semiconductor material layer filling opening is simultaneously
The oxide skin(coating) of lower section is covered, then passes through metal assisted chemical etch method (Metal-Assisted Chemical
Etching method) removes the semiconductor material layer in the opening, wherein the metal assisted chemical etch method
(Metal-Assisted Chemical Etching) has the selectivity of height, so as to which more large ratio of height to width be prepared
(High-aspect-ratio) I-FinFET devices, it is often more important that pass through the metal assisted chemical etch method
(Metal-Assisted Chemical Etching) can also ensure the more large ratio of height to width (High-aspect-ratio)
I-FinFET devices it is against damages, there is the insertion oxide skin(coating) fin in the I-FinFET devices that are prepared good
Profile, so as to improve the performance of the semiconductor devices and yield.
The insertion oxide skin(coating) FinFET of the present invention, as a result of above-mentioned manufacture method, thus equally have upper
State advantage.The electronic installation of the present invention, as a result of above-mentioned insertion oxide skin(coating) FinFET, thus equally have above-mentioned
Advantage.
Embodiment two
Present invention also offers one kind to insert oxide skin(coating) FinFET, the insertion oxide skin(coating) FinFET bag
Include：
Semiconductor substrate；
Oxide stratotype fin is inserted, positioned at the semiconductor substrate；
The insertion oxide skin(coating) fin includes the oxide skin(coating) and semiconductor material layer of alternating deposit.
Wherein, the insertion oxide skin(coating) fin includes spaced several columns.
Wherein, the insertion oxide skin(coating) FinFET includes Semiconductor substrate 201, and the Semiconductor substrate can be
At least one of material being previously mentioned below：Silicon, silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, on insulator
It is laminated SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..In the embodiment
Middle Semiconductor substrate 201 selects silicon.
Wherein, the semiconductor material layer includes III-V semiconductor material layer.
Wherein described III-V semiconductor material layer has the following advantages that：
(1) process costs are relatively small, inexpensively many compared to SOI pieces；
(2) due to using germanium, III-V substrate, so the mobility ratio of device is higher, therefore larger open can be obtained
State electric current, wherein the ratio of the ON state current and off-state current can reach more than 106；
(3) can effective adjusting means threshold voltage.
Wherein described III-V semiconductor material layer refers to include the 3rd main group IIIA and the 5th in the periodic table of chemical element
Main group VA semi-conducting material, such as InGaAs etc., but the species of specific semi-conducting material and composition can be according to realities
Border needs to be selected.
Wherein, the semiconductor material layer can be crystal structure, and the scope of its lattice constant is not limited to a certain number
It is worth scope.
Further, the semiconductor material layer can be formed by the method for transversal epitaxial growth (ELOG).
Wherein, the performance of the III-V semiconductor material layer formed by the transversal epitaxial growth (ELOG) is more
It is excellent, it can further improve the performance and yield of the semiconductor devices.
Chemical etching is performed by auxiliary of the catalyst layer in the present invention, to form the fin for inserting oxide skin(coating).
Wherein, the chemical etching in the present invention is metal assisted chemical etch method (Metal-Assisted
Chemical Etching), i.e., Seed Layer is formed in the bottom of etching, then sequentially form material to be etched, eventually form
Metal level, chemical etching, the metal assisted chemical etch method are carried out on the premise of the metal level is as catalyst
(Metal-Assisted Chemical Etching) has the selectivity of height, so as to which more large ratio of height to width be prepared
(High-aspect-ratio) I-FinFET devices, it is often more important that pass through the metal assisted chemical etch method
(Metal-Assisted Chemical Etching) can also ensure the more large ratio of height to width (High-aspect-ratio)
I-FinFET devices it is against damages, there is the insertion oxide skin(coating) fin in the I-FinFET devices that are prepared good
Profile, so as to improve the performance of the semiconductor devices and yield.
Specifically, the Seed Layer selects layer of InP in the present invention, but is not limited to the example.
Wherein, the catalyst layer includes metal level, such as can select Au, but be not limited to that the example.
Wherein, the metal assisted chemical etch method (Metal-Assisted Chemical Etching) is to described
Seed Layer and the Semiconductor substrate and the metal level have very big etching selectivity, are removing the mistake of the Seed Layer
The Semiconductor substrate and the metal level will not be had any impact in journey.
H can be selected in metal assisted chemical etch2SO4And H2O2In one or more carried out as reaction solution it is anti-
Should, to remove the semiconductor material layer in the opening.
Wherein, the etching of the metal assisted chemical etch method (Metal-Assisted Chemical Etching)
Temperature can be room temperature.
System can be made by the metal assisted chemical etch method (Metal-Assisted Chemical Etching)
The depth-width ratio (High-aspect-ratio) of the fin of standby obtained insertion oxide skin(coating) reaches 45:More than 1, but also can be with
Ensureing the fin profile of the insertion oxide skin(coating) has good performance, and profile defects will not occur, described so as to improve
The performance and yield of semiconductor devices.
In order to solve above mentioned problem present in current technique, the invention provides one kind to insert oxide skin(coating) FinFET devices
Part (Inserted-oxide FinFET, I-FinFET), the insertion oxide skin(coating) FinFET (Inserted-oxide
FinFET, I-FinFET) preparation process in sequentially form the oxide skin(coating) and semiconductor material layer of patterning, wherein the oxygen
There is opening, the semiconductor material layer filling oxide skin(coating) for being open and covering lower section, Ran Houtong in compound layer
The method for crossing metal assisted chemical etch method (Metal-Assisted Chemical Etching) is removed in the opening
The semiconductor material layer, wherein metal assisted chemical etch method (the Metal-Assisted Chemical
Etching) there is the selectivity of height, so as to which more large ratio of height to width (High-aspect-ratio) I-FinFET be prepared
Device, it is often more important that pass through the metal assisted chemical etch method (Metal-Assisted Chemical Etching)
It can also ensure that the I-FinFET devices of the more large ratio of height to width (High-aspect-ratio) are against damages, make to be prepared
I-FinFET devices in insertion oxide skin(coating) fin there is good profile, so as to improve the property of the semiconductor devices
Energy and yield.
The insertion oxide skin(coating) FinFET of the present invention, as a result of above-mentioned manufacture method, thus equally have upper
State advantage.The electronic installation of the present invention, as a result of above-mentioned insertion oxide skin(coating) FinFET, thus equally have above-mentioned
Advantage.
Embodiment three
An alternative embodiment of the invention provides a kind of electronic installation, and it includes inserting oxide skin(coating) FinFET, should
It is the insertion oxide skin(coating) FinFET in previous embodiment two to insert oxide skin(coating) FinFET, or according to embodiment one
Insertion oxide skin(coating) FinFET obtained by the preparation method of described insertion oxide skin(coating) FinFET.
The electronic installation, can be mobile phone, tablet personal computer, notebook computer, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment or have
The intermediate products of above-mentioned insertion oxide skin(coating) FinFET, such as：Cell phone mainboard with the integrated circuit etc..
Due to including insertion oxide skin(coating) FinFET part there is higher performance, the electronic installation equally has upper
State advantage.
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 304, loudspeaker 305, microphone 306 etc..
Wherein described mobile phone handsets include foregoing insertion oxide skin(coating) FinFET, or according to the institute of embodiment one
Insertion oxide skin(coating) FinFET obtained by the preparation method for the insertion oxide skin(coating) FinFET stated, the insertion oxygen
Patterning is sequentially formed in the preparation process of compound layer FinFET (Inserted-oxide FinFET, I-FinFET)
Oxide skin(coating) and semiconductor material layer, wherein having opening in the oxide skin(coating), opened described in the semiconductor material layer filling
Mouth and the oxide skin(coating) for covering lower section, then pass through metal assisted chemical etch method (Metal-Assisted
Chemical Etching) method remove the semiconductor material layer in the opening, wherein the metal assistant chemical
Engraving method (Metal-Assisted Chemical Etching) has the selectivity of height, so as to which bigger height be prepared
The wide I-FinFET devices than (High-aspect-ratio), it is often more important that pass through the metal assisted chemical etch method
(Metal-Assisted Chemical Etching) can also ensure the more large ratio of height to width (High-aspect-ratio)
I-FinFET devices it is against damages, there is the insertion oxide skin(coating) fin in the I-FinFET devices that are prepared good
Profile, so as to improve the performance of the semiconductor devices and yield.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (14)
1. a kind of preparation method of FinFET, it is characterised in that methods described includes：
Semiconductor substrate is provided, formed with Seed Layer in the Semiconductor substrate；
It is repeatedly alternate in the Semiconductor substrate and the Seed Layer to form semiconductor material layer and the oxidation with opening
Nitride layer, the opening in the oxide skin(coating) of semiconductor material layer filling below, wherein the opening with it is described
Seed Layer is alignd；
Etching catalyst layer is formed in said opening；
Chemical etching is performed by auxiliary of the catalyst layer, removes the semiconductor material layer below the catalyst layer,
Oxide stratotype fin is inserted to be formed.
2. according to the method for claim 1, it is characterised in that the semiconductor material layer includes III-V semi-conducting material
Layer.
3. method according to claim 1 or 2, it is characterised in that the semiconductor material layer passes through transversal epitaxial growth
Method formed.
4. according to the method for claim 1, it is characterised in that the Seed Layer selects layer of InP.
5. according to the method for claim 1, it is characterised in that remove the Seed Layer simultaneously in the chemical etching.
6. method according to claim 1 or 5, it is characterised in that remove the semiconductor below the catalyst layer
Methods described still further comprises the step of removing the catalyst layer after material layer.
7. according to the method for claim 1, it is characterised in that methods described, which still further comprises, reduces the oxide skin(coating)
The step of lateral dimension, so that the lateral dimension of the oxide skin(coating) is less than the lateral dimension of the semiconductor material layer.
8. according to the method for claim 1, it is characterised in that alternate in the Semiconductor substrate and the Seed Layer
Form the first semiconductor material layer, the first oxide skin(coating), the second semiconductor material layer, the second oxide skin(coating), the 3rd semiconductor material
The bed of material and trioxide layer.
9. according to the method for claim 1, it is characterised in that forming the method for the Seed Layer includes：
The Semiconductor substrate is provided, forms the mask layer with opening on the semiconductor substrate；
Using the mask layer as Semiconductor substrate described in mask etch, to form groove；
The Seed Layer is formed in the trench.
10. a kind of FinFET, it is characterised in that the device is prepared into by one of claim 1 to 9 methods described
Arrive, the device includes Semiconductor substrate and the insertion oxide stratotype fin in the Semiconductor substrate；
The insertion oxide stratotype fin includes semiconductor material layer and oxide skin(coating) that multilayer is alternatively formed.
11. FinFET according to claim 10, it is characterised in that the most top of the insertion oxide stratotype fin
Layer is the oxide skin(coating).
12. FinFET according to claim 10, it is characterised in that the most bottom of the insertion oxide stratotype fin
Layer is the oxide skin(coating).
13. FinFET according to claim 10, it is characterised in that the lateral dimension of the oxide skin(coating) is less than institute
State the lateral dimension of semiconductor material layer.
14. a kind of electronic installation, it is characterised in that the electronic installation includes the FinFET described in one of claim 10-13
Device.
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| CN104051536A (en) * | 2013-03-13 | 2014-09-17 | 国际商业机器公司 | III-V finfets on silicon substrate |
| US20140349452A1 (en) * | 2013-05-22 | 2014-11-27 | United Microelectronics Corp. | Method for manufacturing semiconductor devices |
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| CN104051536A (en) * | 2013-03-13 | 2014-09-17 | 国际商业机器公司 | III-V finfets on silicon substrate |
| US20140349452A1 (en) * | 2013-05-22 | 2014-11-27 | United Microelectronics Corp. | Method for manufacturing semiconductor devices |
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