CN107611048A - A kind of monitoring method of epitaxial structures growth technique - Google Patents
A kind of monitoring method of epitaxial structures growth technique Download PDFInfo
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- CN107611048A CN107611048A CN201710772393.1A CN201710772393A CN107611048A CN 107611048 A CN107611048 A CN 107611048A CN 201710772393 A CN201710772393 A CN 201710772393A CN 107611048 A CN107611048 A CN 107611048A
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Abstract
The present invention provides a kind of monitoring method of epitaxial structures growth technique, through hole is formed on test chip, the depth of through hole before acquisition epitaxial structures growth and after epitaxial structures growth respectively, the difference of secondary deep is the actual (real) thickness of epitaxial structure, by measuring the depth of through hole twice, the purpose of monitoring epitaxial structures growth is played.In this method, growth to 3D nand memory epitaxial structures by the way of offline is monitored, and can periodically carry out the monitoring, and whether react growth technique by the thickness of epitaxial structure abnormal, the process condition of timely feedback arrangement, be advantageous to improve the stability of production and the yield of product.
Description
Technical field
The present invention relates to 3D memories and its manufacturing field, more particularly to a kind of monitoring side of epitaxial structures growth technique
Method.
Background technology
Nand flash memory is a kind of storage device more more preferable than hard disk drive, with people pursue low in energy consumption, light weight and
The non-volatile memory product of excellent performance, is widely used in electronic product.At present, the nand flash memory of planar structure has been
The limit of nearly true extension, in order to further improve memory capacity, reduce the carrying cost per bit, it is proposed that 3D structures
Nand memory.
In 3D nand memory structures, by the way of vertical stacking multi-layer data memory cell, stack is realized
3D nand memory structures.In 3D NAND manufacturing process, the first shape in the alternately laminated lamination of silica and silicon nitride
Into raceway groove hole, then, pass through selective epitaxial growth (Selective Epitaxial Growth) formation in raceway groove bottom hole portion
Epitaxial silicon structure, the epitaxial silicon structure are commonly referred to as SEG；Then, memory block is formed in raceway groove hole, afterwards, by lamination
Silicon nitride remove, replace it with metal level.The epitaxial structure plays a part of connecting memory block to substrate common active regions, together
When, play a part of support stack layer in replacing process, the growth technique of epitaxial structure is most important.
However, the epitaxial growth technology is monitored currently without any directly effective method, merely by extension
Growing polycrystalline silicon in equipment, it is whether normal to monitor the temperature of epitaxial device and air pressure etc., and these can not be outside effective monitoring
Prolong technique, be unfavorable for improving the stability of production and the yield of product.
The content of the invention
In view of this, it is an object of the invention to provide a kind of monitoring method of epitaxial structures growth technique, monitored off-line
Epitaxial structures growth technique, improve the stability of production and the yield of product.
To achieve the above object, the present invention has following technical scheme：
A kind of monitoring method of epitaxial structures growth technique, including：
There is provided test chip, the test chip includes substrate, the coating of dielectric material and described on the substrate
The through hole of the exposure substrate in coating；
Measure the first depth of epitaxial structures growth front through hole；
In the via bottoms selective epitaxial growth epitaxial structure；
Second depth of through hole after measurement epitaxial structures growth.
Alternatively, in addition to：By the second depth and the first depth, the thickness of epitaxial structure is obtained.
Alternatively, using hole mask plate, the through hole is formed by etching the coating, the hole mask plate is 3D
It is used for the mask plate for forming raceway groove hole in nand memory manufacturing process.
Alternatively, the through hole for measurement is located in substrate different zones.
Alternatively, the different zones include the fringe region of central area and substrate.
Alternatively, the substrate is silicon substrate, and the epitaxial structure is epitaxial silicon.
Alternatively, the process conditions of selective epitaxial growth form extension with being used in 3D nand memory manufacturing process
The process conditions of structure are identical.
Alternatively, first depth and the second depth are obtained by AFM measuring apparatus.
The monitoring method of epitaxial structures growth technique provided in an embodiment of the present invention, through hole is formed on test chip, point
The depth of through hole that Huo get be before epitaxial structures growth and after epitaxial structures growth, the difference of secondary deep is epitaxial structure
Actual (real) thickness, by measuring the depth of two side through hole, play the purpose of monitoring epitaxial structures growth.In this method, using offline
Growth of the mode to 3D nand memory epitaxial structures be monitored, can periodically carry out the monitoring, pass through epitaxial structure
Thickness reaction growth technique it is whether abnormal, the process condition of timely feedback arrangement, be advantageous to improve stability and the production of production
The yield of product.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
These accompanying drawings obtain other accompanying drawings.
Fig. 1-Fig. 2 shows the cross-sectional view of memory during formation 3D nand memories in the prior art；
Fig. 3 is the schematic flow sheet for the detection method for showing epitaxial structure etching rate according to embodiments of the present invention；
Fig. 4 (a)-Fig. 4 (f) shows the cross-section structure signal to be formed during the epitaxial structure of the embodiment of the present invention
Figure；
Fig. 5-Fig. 6 shows the section during the detection method of epitaxial structure etching rate according to embodiments of the present invention
Structural representation.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with
It is different from other manner described here using other to implement, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.
Secondly, combination schematic diagram of the present invention is described in detail, when the embodiment of the present invention is described in detail, for purposes of illustration only, table
Show that the profile of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, and it should not herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
As the description in background technology, in the manufacturing process of 3D nand memories, without any directly effective side
Method monitors epitaxial growth technology, merely by the growing polycrystalline silicon in epitaxial device, come monitor the temperature of epitaxial device and
Whether air pressure etc. normal, and these can not effective monitoring epitaxy technique, be unfavorable for improving production stability and product it is good
Rate.Therefore, the invention provides a kind of monitoring method, to the life of 3D nand memory epitaxial structures by the way of offline
Length is monitored.
For a better understanding of the present invention, the manufacturing process of the 3D nand memories of correlation is described first.
Specifically, with reference to figure 1, when forming 3D nand memories, first, silicon nitride (SiN) is formed on the substrate 100
1101 and silica (SiO of layer2) layer 1102 stack layer 110.Wherein, the number of plies of stack layer is formed according to needed for vertical direction
The number of memory cell determines that the number of plies of stack layer is more, can more improve integrated level, the number of plies of stack layer for example can be 8
Layer, 32 layers, 64 layers etc..
Then, raceway groove hole (Channel hole) 120 is formed in stack layer 110, the raceway groove hole 120 is used for forming storage
Area, need to first pass through selective epitaxial growth (Selective Epitaxial Growth) formation extension in the bottom in raceway groove hole
Silicon structure 130, the structure 130 are commonly referred to as SEG, then form memory block in epitaxial silicon structure 130.The epitaxial silicon structure
It is to be formed on substrate by selective epitaxial growth, is the epitaxial layer of substrate, plays to memory block connection function, and it is right
Stack layer is played a supporting role.Memory block mainly includes electric charge capture layer and channel layer, and electric charge capture layer can be ONO layer, i.e.,
The lamination of oxide-nitride-oxide, channel layer can be polysilicon layer.
Afterwards, with reference to shown in figure 2, by grid line (gate line) (not shown), by the silicon nitride in stack layer 110
Layer 1102 removes, and the region for removing silicon nitride layer will be replaced into metal level 1102, the control gate as memory device.
For the growth technique of timely feedback extension structure, the present invention proposes a kind of monitoring of epitaxial structures growth technique
Method, with reference to shown in figure 3, including：
There is provided test chip, the test chip includes substrate, the coating of dielectric material and described on the substrate
The through hole of the exposure substrate in coating；
Measure the first depth of epitaxial structures growth front through hole；
In the via bottoms selective epitaxial growth epitaxial structure；
Second depth of through hole after measurement epitaxial structures growth.
In this method, test chip on form through hole, respectively obtain epitaxial structures growth before and epitaxial structures growth it
The depth of through hole afterwards, the difference of secondary deep is the actual (real) thickness of epitaxial structure, by measuring the depth of two side through hole, is played
Monitor the purpose of epitaxial structures growth.In this method, to the growth of 3D nand memory epitaxial structures by the way of offline
It is monitored, can periodically carries out the monitoring, reacts whether growth technique is abnormal, and feedback is tied in time by the thickness of epitaxial structure
The process condition of structure, be advantageous to improve the stability of production and the yield of product.
Technical scheme for a better understanding of the present invention and technique effect, below with reference to flow chart and accompanying drawing to tool
The embodiment of body is described in detail.
In step S01, there is provided test chip, the test chip include the covering of dielectric material on substrate, the substrate
The through hole of the exposure substrate in layer and the coating.
In embodiments of the present invention, it is non-volume production chip to test chip, and the test chip is mainly used in the life of epitaxial structure
It is long, to carry out the monitoring of technique.On the test chip, through hole is already formed with, through hole forms in coating 110 and sudden and violent
Expose the substrate 110, subsequently to carry out epitaxial growth.
In embodiments of the present invention, the coating 110 is dielectric material, for example, oxide or nitride or they
Combination, can be individual layer or laminated construction, in a preferred embodiment, the coating is oxide (oxide).Through hole 130 exposes
Substrate 100, the surface of substrate 100 can be only exposed, so, when growing epitaxial structure, the substrate surface from the bottom of through hole 130
Carry out epitaxial growth.The through hole 130 can also over etching section substrate, with reference to shown in figure 4 (f), so, growth epitaxial structure
When, epitaxial growth is carried out from the bottom surface of the substrate of the bottom of through hole 130 and side, there is the faster speed of growth.Herein can root
According to the technique of actual monitored, the through hole is set.
These through holes can be provided only in the different zones of substrate, can also be the same to actual production technology, spread all over
On substrate, when being actually used in measurement, as needed, select the through hole in one or more regions to measure, be easy to pair
The growth of the epitaxial structure of different zones is monitored respectively, obtains the speed of growth and the correlation in region.Preferably implementing
In example, the through hole for measurement is located at the fringe region of central area and substrate, and fringe region can include Waffer edge
One or more regions.
In order to make it easy to understand, the embodiment for forming through hole is described in detail below.
First, there is provided substrate 100, with reference to shown in figure 4 (a).
In embodiments of the present invention, substrate 200 is Semiconductor substrate, such as can be Si substrates, Ge substrates, SiGe linings
Bottom, SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator, Germanium On
Insulator) etc..In other embodiments, the Semiconductor substrate can also be to include other elements semiconductor or compound
The substrate of semiconductor, such as GaAs, InP or SiC etc., can also be laminated construction, such as Si/SiGe etc. can be with outside other
Prolong structure, such as SGOI (silicon germanium on insulator) etc..In the present embodiment, the substrate 200 is silicon substrate.
Then, the coating 110 of oxide is formed, with reference to shown in figure 4 (b).
By CVD (chemical vapor deposition) or other suitable deposition process, the coating of the oxide can be deposited
110, according to specific needs, the thickness of the coating is selected, usually, the thickness range of the coating can beThen, using hole mask plate, the through hole 130 of exposure substrate 100 is formed by etching the coating 110,
With reference to shown in figure 4 (e).
In order to preferably monitor the technique of actual 3D nand memories volume production chip, 3D nand memory systems can be used
Make and be used for the mask plate for forming raceway groove hole in technique, that is, the mask plate in actual batch production technique during formation raceway groove hole.This
Sample, actual production technique can be preferably matched, also without extra technique expense is increased, reduce testing cost.
Specifically, the spin coating photoresist layer 120 on coating 110, as shown in Fig. 4 (c)；Then, exposure imaging etc. is passed through
Pattern on the mask plate of hole is transferred to photoresist layer 120 by step, the photoresist layer 120 after being patterned, such as Fig. 4 (d) institutes
Show；Then, technique is performed etching, such as RIE (reactive ion etching) can be used, etches the coating 120, forms exposure
The through hole 130 of substrate, can be stop-layer with substrate 100, can also over etching section substrate 100, as shown in Fig. 4 (e)；Most
Afterwards, remove photoresist layer 120 and carry out the cleaning of chip, so, through hole 130 is formed, as shown in Fig. 4 (f).
In step S02, the first depth H 1 of measurement epitaxial structures growth front through hole 130, with reference to shown in figure 5.
It is understood that when obtaining the first height H1, test chip can have already passed through necessary cleaning step, clearly
It can remove the cleaning carried out during photoresist to wash step, can also additionally be cleaned.
First depth H 1 can be measured by AFM (Atomic Force Microscope) or other measuring apparatus, surveyed
The through hole that the through hole of amount can be the through hole of FX or some regions are chosen from chip.Outside different zones
The speed of growth for prolonging structure there may be difference, by the measurement of the height of different zones, can monitor the life of regional
Long situation, it is convenient for the analysis of area coherence.Typically, the through hole of wafer central region and fringe region can be chosen,
Measurement for depth.
In step S03, in the selective epitaxial growth epitaxial structure 140 of via bottoms 130, with reference to shown in figure 6.
The epitaxial structure is formed by selective epitaxial growth, epitaxial structure has and substrate identical from substrate growth
Lattice and material, when substrate is silicon substrate, epitaxial structure is epitaxial silicon.
When growing the epitaxial structure, can use with being used to form epitaxial structure in 3D nand memory manufacturing process
When identical process conditions, so as to reality production technology directly monitored.In one example, process conditions are such as
Under：Temperature range can be 700-900 DEG C, and pressure limit can be 5-20Torr, and hydrogen chloride gas range of flow can be
100-400sccm, dichlorosilane gas flow can be 100-300sccm, after reaction after a while, obtain epitaxy junction
The target growth thickness of structure is
The second depth of through hole after step S04, measurement epitaxial structures growth.
It is understood that when obtaining the second height H2, test chip can have already passed through necessary cleaning step.
Second depth H 2 can be measured by AFM (Atomic Force Microscope) or other measuring apparatus, surveyed
The through hole that the through hole of amount can be the through hole of FX or some regions are chosen from chip.First height H1 with
Second height H2 difference is the actual (real) thickness of epitaxial structure, passes through the difference between the two, it is possible to obtains the thickness of epitaxial structure.Obtain
The form of the thickness value obtained is unlimited, and the thickness can be scatterplot value, average value, variance yields etc., and scatterplot value each measures logical
The corresponding thickness in hole.
The thickness now obtained is the actual thickness of epitaxial structure, therefore, can by the average value of the thickness and
Distribution on wafer can reflect the state of arts of epitaxial growth in time, so as to detect technological parameter temperature, pressure, when
Between, whether the factor such as gas flow is abnormal.And by the analysis to technological parameter, timely adjusting process parameter, improve production
The yield of stability and product.
Above-mentioned detection method can be carried out periodically, such as can be carried out daily or per several days, realize and 3D NAND are stored
The monitoring of device epitaxial structures growth technique.
Described above is only the preferred embodiment of the present invention, although the present invention is disclosed as above, so with preferred embodiment
And it is not limited to the present invention.Any those skilled in the art, technical solution of the present invention ambit is not being departed from
Under, many possible changes and modifications are all made to technical solution of the present invention using the methods and technical content of the disclosure above,
Or it is revised as the equivalent embodiment of equivalent variations.Therefore, every content without departing from technical solution of the present invention, according to the present invention's
Technical spirit still falls within the technology of the present invention side to any simple modification, equivalent variation and modification made for any of the above embodiments
In the range of case protection.
Claims (10)
- A kind of 1. monitoring method of epitaxial structures growth technique, it is characterised in that including：Test chip, coating and the covering of the test chip including dielectric material on substrate, the substrate are provided The through hole of the exposure substrate in layer；Measure the first depth of epitaxial structures growth front through hole；In the via bottoms selective epitaxial growth epitaxial structure；Second depth of through hole after measurement epitaxial structures growth.
- 2. according to the method for claim 1, it is characterised in that also include：By the second depth and the first depth, obtain outer Prolong the thickness of structure.
- 3. according to the method for claim 1, it is characterised in that using hole mask plate, formed by etching the coating The through hole, the hole mask plate are the mask plate for being used to form raceway groove hole in 3D nand memory manufacturing process.
- 4. according to the method for claim 1, it is characterised in that the through hole for measurement is located in substrate different zones.
- 5. according to the method for claim 4, it is characterised in that the different zones include central area and the side of substrate Edge region.
- 6. according to the method for claim 1, it is characterised in that the substrate is silicon substrate, and the epitaxial structure is extension Silicon.
- 7. according to the method any one of claim 1-6, it is characterised in that the process conditions of selective epitaxial growth with The process conditions for being used to be formed epitaxial structure in 3D nand memory manufacturing process are identical.
- 8. according to the method any one of claim 1-6, it is characterised in that first depth and the second depth pass through AFM measuring apparatus obtains.
- 9. according to the method any one of claim 1-6, it is characterised in that the thickness range of the coating is
- 10. according to the method for claim 9, it is characterised in that the target thickness scope of the epitaxial structure is
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01223725A (en) * | 1988-03-02 | 1989-09-06 | Nec Corp | Evaluation of film thickness of semiconductor device |
| KR20080048703A (en) * | 2006-11-29 | 2008-06-03 | 동부일렉트로닉스 주식회사 | Measurement method of a thickness in an epitaxial process using a surface step |
| CN102005401A (en) * | 2010-09-10 | 2011-04-06 | 上海宏力半导体制造有限公司 | Epitaxial film thickness measurement method |
| CN102569041A (en) * | 2010-12-29 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Monitoring method of selective extension process |
| CN106548956A (en) * | 2016-12-07 | 2017-03-29 | 成都海威华芯科技有限公司 | A kind of thickness measurement method of hydatogenesis thin film |
-
2017
- 2017-08-31 CN CN201710772393.1A patent/CN107611048A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01223725A (en) * | 1988-03-02 | 1989-09-06 | Nec Corp | Evaluation of film thickness of semiconductor device |
| KR20080048703A (en) * | 2006-11-29 | 2008-06-03 | 동부일렉트로닉스 주식회사 | Measurement method of a thickness in an epitaxial process using a surface step |
| CN102005401A (en) * | 2010-09-10 | 2011-04-06 | 上海宏力半导体制造有限公司 | Epitaxial film thickness measurement method |
| CN102569041A (en) * | 2010-12-29 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Monitoring method of selective extension process |
| CN106548956A (en) * | 2016-12-07 | 2017-03-29 | 成都海威华芯科技有限公司 | A kind of thickness measurement method of hydatogenesis thin film |
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