CN107607853A - Adjustment method, device, storage medium and the processor of chip - Google Patents
Adjustment method, device, storage medium and the processor of chip Download PDFInfo
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- CN107607853A CN107607853A CN201710716024.0A CN201710716024A CN107607853A CN 107607853 A CN107607853 A CN 107607853A CN 201710716024 A CN201710716024 A CN 201710716024A CN 107607853 A CN107607853 A CN 107607853A
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Abstract
The invention discloses a kind of adjustment method of chip, device, storage medium and processor.This method includes：Selection first processing module corresponding with target debugging signal, wherein, target debugging signal is used to debug objective chip；Target is exported by first processing module and debugs signal；In the case where allowing target to debug signal output to objective chip, control targe debugs signal output to objective chip, wherein, objective chip is connected with target bus；Signal is debugged by target bus according to target to debug objective chip.By the present invention, the effect for the debugging efficiency for improving chip is reached.
Description
Technical field
The present invention relates to integrated circuit fields, in particular to a kind of adjustment method of chip, device, storage medium
And processor.
Background technology
At present, in the development process of large-scale integrated circuit, in circuit design early stage, it is necessary to add necessary debugging
Method, with the reliability of test chip, analysis and assessment circuit problem.Generally used adjustment method is increase die terminals at present
The number of mouth (IO), is exported to any chip internal signal on debugging (DEBUG) port by certain logical design, and lead to
The observation to the port signal is crossed, so that produced problem in actual test is analyzed and assessed.
For the above method, certain negative effect can be played to chip area by increasing the port number of chip, and complicated
Change the rear end flow during lsi development, cause the debugging efficiency of chip low；And in other multiplex bus
In the method that port is debugged, during being debugged to chip port, the occupancy of bus port result in herein
Period can not carry out the problem of necessary operation (including read-write register, the operation such as send instructions) to chip, so as to greatly reduce
The debugging efficiency of chip, or even limit the application scenarios debugged to multiplex bus port.
For the problem of efficiency of chip debugging is low in the prior art be present, effective solution is not yet proposed at present.
The content of the invention
It is a primary object of the present invention to provide a kind of adjustment method of chip, device, storage medium and processor, so that
Solve the problems, such as that the efficiency of chip debugging is low less.
To achieve these goals, according to an aspect of the invention, there is provided a kind of adjustment method of chip.This method
Including：Selection first processing module corresponding with target debugging signal, wherein, target debugging signal is used to debug objective chip；
Target is exported by first processing module and debugs signal；In the case where allowing target to debug signal output to objective chip, control
Target processed debugs signal output to objective chip, wherein, objective chip is connected with target bus；By target bus according to mesh
Mark debugging signal is debugged to objective chip.
Alternatively, selection first processing module corresponding with target debugging signal includes：Pass through configuration register control the
One selector selects first processing module corresponding with target debugging signal, wherein, configuration register is located at the interior of objective chip
Portion.
Alternatively, exporting target debugging signal by first processing module includes：Pass through the choosing of configuration register control second
The target debugging signal for selecting device selection first processing module is exported.
Alternatively, in the case where allowing target to debug signal output to objective chip, control targe debugging signal output
Include to objective chip：In the case where gate processing module allows target to debug signal output to objective chip, control targe
Signal output is debugged to objective chip.
Alternatively, before debugging signal according to target by target bus and objective chip is debugged, this method is also
Including：The operation count value for the operation carried out to objective chip that monitoring objective bus has performed；It is less than in operation count value
In the case of the first object value of configuration register configuration, control gate processing module is in first state, wherein, first state
Under gate processing module do not allow target to debug signal output to objective chip；Match somebody with somebody in operation count value equal to configuration register
In the case of the first object value put, control gate processing module is in the second state, wherein, the gate processing under the second state
Module allows target to debug signal output to objective chip.
Alternatively, control gate processing module includes in first state：The mark of output first, and shield target control letter
Number, wherein, first identifies and is less than first object value for identifying operation count value, and target control signal is for controlling gate to handle
Module is in the second state；In the mark of output first, and after shielding target control signal, control gate processing module is in the
One state；Control gate processing module, which is in the second state, to be included：The mark of output second, and enabled target control signal, wherein,
Second identifies and is equal to first object value for identifying operation count value；In the mark of output second, and enabled target control signal it
Afterwards, control gate processing module is in the second state.
Alternatively, after control gate processing module is in the second state, this method also includes：To register configuration
Two desired values；The operation count for the operation carried out to objective chip for determining to allow target bus to perform by the second desired value
Value.
Alternatively, carrying out debugging to objective chip according to target debugging signal by target bus includes：In target bus
After the operation that execution is carried out to objective chip terminates, signal is debugged according to target by target bus objective chip is adjusted
Examination.
To achieve these goals, according to another aspect of the present invention, a kind of debugging apparatus of chip is additionally provided.The dress
Put including：Selecting unit, for selecting first processing module corresponding with target debugging signal, wherein, target debugging signal is used
In debugging objective chip；Output unit, signal is debugged for exporting target by first processing module；Control unit, for
In the case of allowing target debugging signal output to objective chip, control targe debugs signal output to objective chip, wherein, mesh
Mark chip is connected with target bus；Debugging unit, objective chip is entered for debugging signal according to target by target bus
Row debugging.
Alternatively, selecting unit includes：Selecting module, for controlling first selector selection and mesh by configuration register
First processing module corresponding to mark debugging signal, wherein, configuration register is located at the inside of objective chip.
To achieve these goals, according to another aspect of the present invention, a kind of storage medium is additionally provided.The storage medium
Program including storage, wherein, equipment performs the chip of the embodiment of the present invention where controlling storage medium when program is run
Adjustment method.
To achieve these goals, according to another aspect of the present invention, a kind of processor is additionally provided, it is characterised in that
Processor is used for operation program, wherein, the adjustment method of the chip of execution embodiment of the present invention when program is run.
By the present invention, the corresponding first processing module of signal is debugged using selection and target, wherein, target debugs signal
For debugging objective chip；Target is exported by first processing module and debugs signal；Signal output is debugged to mesh allowing target
In the case of marking chip, control targe debugs signal output to objective chip, wherein, objective chip is connected with target bus；
Signal is debugged by target bus according to target to debug objective chip.Due to by selecting processing corresponding to debugging signal
Module, by selecting the debugging signal in processing module, chip is debugged according to debugging signal by target bus, so as to
Do not increase the port number of chip, alleviate influence of the port number to area, it also avoid in debugging process due to bus
Port takes and necessary operation can not be carried out to chip, solve the problems, such as that the efficiency of chip debugging is low, and then carries
The effect of the debugging efficiency of high chip.
Brief description of the drawings
The accompanying drawing for forming the part of the application is used for providing a further understanding of the present invention, schematic reality of the invention
Apply example and its illustrate to be used to explain the present invention, do not form inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is a kind of flow chart of the adjustment method of chip according to embodiments of the present invention；
Fig. 2 is a kind of structural representation of chip debugging according to embodiments of the present invention；
Fig. 3 is the schematic diagram of another chip debugging according to embodiments of the present invention；And
Fig. 4 is a kind of schematic diagram of the debugging apparatus of chip according to embodiments of the present invention.
Embodiment
It should be noted that in the case where not conflicting, the feature in embodiment and embodiment in the application can phase
Mutually combination.Describe the present invention in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
In order that those skilled in the art more fully understand application scheme, below in conjunction with the embodiment of the present application
Accompanying drawing, the technical scheme in the embodiment of the present application is clearly and completely described, it is clear that described embodiment is only
The embodiment of the application part, rather than whole embodiments.Based on the embodiment in the application, ordinary skill people
The every other embodiment that member is obtained under the premise of creative work is not made, it should all belong to the model of the application protection
Enclose.
It should be noted that term " first " in the description and claims of this application and above-mentioned accompanying drawing, "
Two " etc. be for distinguishing similar object, without for describing specific order or precedence.It should be appreciated that so use
Data can exchange in the appropriate case, so as to embodiments herein described herein.In addition, term " comprising " and " tool
Have " and their any deformation, it is intended that cover it is non-exclusive include, for example, containing series of steps or unit
Process, method, system, product or equipment are not necessarily limited to those steps clearly listed or unit, but may include without clear
It is listing to Chu or for the intrinsic other steps of these processes, method, product or equipment or unit.
Embodiment 1
The embodiments of the invention provide a kind of adjustment method of chip.
Fig. 1 is a kind of flow chart of the adjustment method of chip according to embodiments of the present invention.As shown in figure 1, this method bag
Include following steps：
Step S102, selection first processing module corresponding with target debugging signal.
In the technical scheme that the application above-mentioned steps S102 is provided, selection the first processing corresponding with target debugging signal
Module, wherein, target debugging signal is used to debug objective chip.
The embodiment can be used in the exploitation of integrated circuit, can be in circuit design early stage, using the tune of the embodiment
Method for testing.Under debugging mode (DEBUG), selection first processing module corresponding with target debugging signal.Target debugging letter
Number be for debugging the signal needed for objective chip, can be provided by corresponding first processing module, the first processing module can
Think the processing module where target debugging signal.Alternatively, the configuration register inside objective chip is passed through
(Register, referred to as REG) controls the first strobe block (mask1) selection the first processing mould corresponding with target debugging signal
Block, wherein, objective chip can be made up of two-stage.
Step S104, target is exported by first processing module and debugs signal.
In the technical scheme that the application above-mentioned steps S104 is provided, target debugging letter is exported by first processing module
Number.
After first processing module corresponding with target debugging signal is selected, target is exported by first processing module and adjusted
Trial signal, such as, control the second strobe block (mask2) to select the target in first processing module to debug letter by configuration register
Number, and export target debugging signal.
Step S106, in the case where allowing target to debug signal output to objective chip, control targe debugging signal is defeated
Go out to objective chip.
In the technical scheme that the application above-mentioned steps S106 is provided, signal output is debugged to objective chip allowing target
In the case of, control targe debugs signal output to objective chip, wherein, objective chip is connected with target bus.
After target is exported by first processing module and debugs signal, it is determined whether allow target to debug signal output extremely
Whether objective chip to be debugged to objective chip, debug signal can be with by the control target signal that can be exported by gating block
In output to objective chip, such as, when the signal level for gating block output is low level, then allow target to debug signal output
To objective chip, when the signal level for gating block output is high level, then target is not allowed to debug signal output to target
On chip.Objective chip is connected with target bus, and the target bus can be spi bus, I2C buses etc., it can also include
Other data/address bus, address bus, controlling bus, expansion bus etc., are not limited herein.
Alternatively, by configuration register and logical block is passed through, to control the output signal of the first strobe block whether can be with
It is output to by gating block on the port (PAD) of objective chip, and the input and output of objective chip port can be adjusted simultaneously
Property is output (oen).
Alternatively, in this embodiment, one or more bit positions corresponding to r_dbg_en signals, the r_dbg_en are configured
Signal is used to control gate block.Corresponding to configuration r_dbg_en signals after one or more bit positions, can by OR gate to
The rising edge that monitoring module sends a level is counted, then counts monitoring module and starts working, and monitoring objective bus, Ke Yijian
The operand being had occurred and that on control target bus, such as, the trans monitored on SPI is counted.As the behaviour of the target bus occurred
Count Configuration Values r_dbg_dly less than configuration register when, it can be the first mark flag to count monitoring module output, than
Such as, it is 0, and by masking above-mentioned r_dbg_en signals with door；When the operand of the target bus occurred is posted equal to configuration
During the Configuration Values r_dbg_dly of storage, the defeated second mark flag of monitoring module is counted, such as, it is 1, now enable signal r_
Dbg_en, can be by further enabling c_dbg_en signals with door.Thus, gate block 1 is controlled by c_dbg_en signals,
In the case of allowing target debugging signal output to objective chip, control targe debugs signal output to objective chip.
Alternatively, the embodiment can be by selecting the Configuration Values r_dbg_dly of configuration register, it is determined that may be used also
With the operand of the target bus of progress, and with the end of last operation, the actual beginning enabled as debugging.
Step S108, signal is debugged according to target by target bus objective chip is debugged.
In the technical scheme that the application above-mentioned steps S108 is provided, signal is debugged to mesh according to target by target bus
Mark chip is debugged.
After control targe debugs signal output to objective chip, signal is debugged to mesh according to target by target bus
Mark chip is debugged, can be with the reliability of test target chip, assessment, analysis circuit etc..
The embodiment debugs the corresponding first processing module of signal by selection with target, wherein, target debugging signal use
In debugging objective chip；Target is exported by first processing module and debugs signal；Signal output is debugged to target allowing target
In the case of chip, control targe debugs signal output to objective chip, wherein, objective chip is connected with target bus；It is logical
Target bus are crossed to debug objective chip according to target debugging signal.Due to by selecting to handle mould corresponding to debugging signal
Block, by selecting the debugging signal in processing module, chip is debugged according to debugging signal by target bus, so as to not
Increase the port number of chip, alleviate influence of the port number to area, it also avoid in debugging process due to bus end
Mouthful take and necessary operation can not be carried out to chip, solve the problems, such as that the efficiency of chip debugging is low, and then improve
The effect of the debugging efficiency of chip.
As an alternative embodiment, step S102, selection first processing module corresponding with target debugging signal
Including：First selector selection first processing module corresponding with target debugging signal is controlled by configuration register, wherein, match somebody with somebody
Register-bit is put in the inside of objective chip.
The adjustment method of the embodiment can be debugged by configuration register control selections device.Adjusted in selection and target
Corresponding to trial signal during first processing module, control first selector selection corresponding with target debugging signal by configuration register
First processing module, the configuration register is located at the inside of objective chip, wherein, first selector can be the first gating
Block.Under normal operating conditions, outside target bus can be by reading the configuration register inside objective chip
Write (r/w) and send instruction (cmd).
As an alternative embodiment, step S104, exporting target debugging signal by first processing module includes：
Control second selector to select the target of first processing module to debug signal by configuration register to be exported.
The target debugging signal of the embodiment may come from first processing module.Mesh is being exported by first processing module
During mark debugging signal, second selector can be controlled to select the target of first processing module to debug signal by configuration register.
After target debugging signal is chosen, output target debugs signal to target and debugs chip, to be carried out to target debugging chip
Debugging.
As an alternative embodiment, step S106, signal output is debugged to the feelings of objective chip allowing target
Under condition, control targe debugging signal output to objective chip includes：Target is allowed to debug signal output extremely in gate processing module
In the case of objective chip, control targe debugs signal output to objective chip.
The embodiment is when control targe debugs signal output to objective chip, the output signal of detection gate processing module
Target whether is allowed to debug signal output to objective chip, such as, when the output signal for gating processing module is high level, permit
Perhaps target debugs signal output to objective chip, when the output signal for gating processing module is low level, does not allow target to adjust
Trial signal is exported to objective chip.In the case where gate processing module allows target to debug signal output to objective chip, control
Target processed debugs signal output to objective chip.
Alternatively, by configuration register and pass through logic processing module, control the first strobe block output signal whether
It can be exported by gating processing module to chip port, while the input and output of the related port of adjustment objective chip
Property is output.
As an alternative embodiment, in step S108, signal is debugged to target according to target by target bus
Before chip is debugged, this method also includes：The behaviour for the operation carried out to objective chip that monitoring objective bus has performed
Make count value；In the case where operation count value is less than the first object value of configuration register configuration, control gate processing module
In first state, wherein, the gate processing module under first state does not allow target to debug signal output to objective chip；
In the case that operation count value is equal to the first object value of configuration register configuration, control gate processing module is in the second shape
State, wherein, the gate processing module under the second state allows target to debug signal output to objective chip.
The embodiment is monitored to target bus.Alternatively, it is come into force in configuration r_dbg_en one or more positions
Afterwards, the level of a rising edge is sent to counting monitoring module by OR gate.The electricity of rising edge is received in counting monitoring module
After flat, count monitoring module and start working, and monitoring objective bus, obtain the operation count of operation carried out to objective chip
Value, such as, obtain the SPI operands of spi bus.Alternatively, when monitor one be used for identify operation beginning flag, or
Person monitor one be used for identify operate at the end of flag, or target bus are pulled down into, it is determined that target bus are held
Go once-through operation, then increase operation count value.
Before debugging signal according to target by target bus and objective chip is debugged, monitoring objective bus is
The operation count value of the operation carried out to objective chip performed, judges whether operation count value is less than first object value, such as,
Judge whether operation count value is less than the value that r_dbg_dly is represented.If it is judged that operation count value is less than first object value, then
Control gate processing module is in first state, and the first state can be by low level control, the gate under first state
Processing module does not allow target to debug signal output to objective chip；If it is judged that operation count value is equal to first object value,
Then control gate processing module is in the second state, and second state can be controlled by high level, the door under first state
Controlling processing module allows target to debug signal output to objective chip, that is, being increased to and first object value in operation count value
In the case of equal, debugging is carried out to objective chip and come into force, reached the purpose that delay comes into force.
Alternatively, the first object value of the embodiment can be configured by configuration register, can arbitrarily be selected, not
Under same first object value, the operand target that target bus can be carried out is also different, and the embodiment is operated with last
Terminate, as the beginning debugged to objective chip, realize the debugging to objective chip.
As an alternative embodiment, control gate processing module includes in first state：The mark of output first,
And target control signal is shielded, wherein, first identifies and is less than first object value, target control signal for identifying operation count value
For controlling gate processing module to be in the second state；In the mark of output first, and after shielding target control signal, door is controlled
Control processing module is in first state；Control gate processing module, which is in the second state, to be included：The mark of output second, and enabled mesh
Control signal is marked, wherein, second identifies and is equal to first object value for identifying operation count value；In the mark of output second, and make
After energy target control signal, control gate processing module is in the second state.
The embodiment can pass through counter (count) output the when control gate processing module be in first state
One mark (flag), this first identifies and is less than first object value for identifying operation count value, and shields target control signal, can
So that by shielding target control signal with door, the target control signal can be r_dbg_en signals, processing mould is gated for controlling
Block is in the second state.In the mark of output first, and after shielding target control signal, control gate processing module is in first
State, that is, gate processing module does not allow target to debug signal output to objective chip.
The embodiment can export the second mark when control gate processing module is in the second state by counter
(flag), this second identifies and is equal to first object value for identifying operation count value, and enables target control signal, can pass through
Target control signal is enabled with door, and then gate processing module can be controlled to be in the second state.In the mark of output second, and make
After energy target control signal, control gate processing module is in the second state, that is, gate processing module allows target debugging
Signal output is to objective chip.
As an alternative embodiment, after control gate processing module is in the second state, this method is also wrapped
Include：To the desired value of register configuration second；Determine that allow target bus to perform is carried out to objective chip by the second desired value
Operation operation count value.
The embodiment, can be to the target of register configuration second after control gate processing module is in the second state
Value, that is, r_dbg_dly value can be reconfigured, by the determination permission target bus execution of the second desired value to target
The operation count value for the operation that chip is carried out, such as, can be determined by configuration to configuration register r_dbg_dly can be with
Number is operated to the SPI that objective chip is carried out.It is equal to the second desired value in the operation count value of the operation carried out to objective chip
In the case of, then allow target to debug signal output to objective chip.Chip is carried out according to debugging signal by target bus
Debugging, so as to not increase the port number of chip, influence of the port number to area is alleviated, it also avoid in debugging process
Necessary operation can not be carried out to chip, reached the debugging efficiency for improving chip because bus port takes.
As an alternative embodiment, step S108, signal is debugged to target core by target bus according to target
Piece, which carries out debugging, to be included：After the operation that target bus execution is carried out to objective chip terminates, by target bus according to mesh
Mark debugging signal is debugged to objective chip.
When being debugged by target bus according to target debugging signal to objective chip, performed in target bus to mesh
After the operation that mark chip is carried out terminates, signal is debugged according to target by target bus objective chip is debugged, that is,
With the end of last operation performed to objective chip, as the beginning debugged to objective chip.
In the chip adjustment method of the embodiment, it is not necessary to extra increase chip port number with meet chip testing,
The demand of debugging, reduce the exploitation R＆D costs of chip, and the complexity of rear end design；Can also solve to be adjusted in bus
The problem of examination function can not continue to operate chip after taking, extends the application scenarios of debugging function, greatly improves
Chip debugging efficiency.
It should be noted that can be in such as one group of computer executable instructions the flow of accompanying drawing illustrates the step of
Performed in computer system, although also, show logical order in flow charts, in some cases, can be with not
The order being same as herein performs shown or described step.
Embodiment 2
Technical scheme is illustrated with reference to preferred embodiment.It is specifically total by SPI of target bus
Line is illustrated.
Fig. 2 is a kind of structural representation of chip debugging according to embodiments of the present invention.As shown in Fig. 2 in normal work
Under state, outside SPI [3:0] bus the register of chip internal can be written and read by chip port PAD (r/w) with
And instruction cmd is sent, wherein, SPI [3:0] bus includes 0,1,2,3 four line.Under debugging mode (assuming that chip structure by
Two-stage is formed), strobe block 1 (mask1) selection desired signal place is controlled under control signal ctrl by configuration register REG
Processing module；Strobe block 2 (mask2_1) is controlled to select processing module under control signal ctrl by configuration register REG
Interior signal is exported；By register configuration REG and by logical block 1 (logic) under control signal ctrl, control choosing
Whether the output signal of logical block 1 can be exported to chip port PAD by gating block 1, while the correlation on adjustment PAD
The input and output property of port is output (oen).Wherein, FSM modules are used to represent state machine parameter of chip internal etc..
Fig. 3 is the schematic diagram of another chip debugging according to embodiments of the present invention.As shown in figure 3, mainly for Fig. 2 institutes
Show that the logical block 1 of embodiment is introduced.After being come into force in a configuration r_dbg_en multiple or bit position, configuration register REG
One rising edge is sent to monitoring module 1 is counted by OR gate 1, monitoring module 1 (monitor) is counted and starts working (start)
And spi bus is monitored, obtain the count value on SPI.When the SPI operands occurred are less than the Configuration Values r_ of configuration register
During dbg_dly, it is 0 to count the output of monitoring module 1, and by shielding r_dbg_en signals, the r_dbg_en with door 1~and door 4
Signal includes r_dbg_en [0], r_dbg_en [1], r_dbg_en [2], r_dbg_en [3]；When SPI operands occurred etc.
When register configuration values r_dbg_dly, count monitoring module 1 output be 1, now enable signal r_dbg_en can by with
Door 1~and door 4 enable c_dbg_en signals.Thus, can be by deposit after bus configuration register DEBUG is enabled
The SPI operation numbers that device r_dbg_dly any selection of configuration can also be carried out, and using the end of last operation as
Actual beginning enabled DEBUG.
The embodiment can provide one kind and reliably be answered by spi bus during being developed to integrated circuit
With the method for realizing chip debugging function, extra die terminals on the one hand so need not be increased by being multiplexed spi bus port
Mouth number negative effect caused by so as to alleviate port number opposite product, is reduced with meeting the needs of chip testing, debugging
The exploitation research and development of chip, cost；On the other hand, the embodiment can not after solving the debugged function occupancy in spi bus port
The problem of continuing to operate chip, the efficiency of chip debugging is improved, extend the application scenarios of debugging function, such as,
Need to test some waveform of spi bus after some instruction is sent within some period, be not limited herein.
Embodiment 3
The embodiment of the present invention additionally provides a kind of debugging apparatus of chip.It should be noted that the chip of the embodiment
Debugging apparatus can be used for the adjustment method for performing the chip of the embodiment of the present invention.
Fig. 4 is a kind of schematic diagram of the debugging apparatus of chip according to embodiments of the present invention.As shown in figure 4, the device bag
Include：Selecting unit 10, output unit 20, control unit 30 and debugging unit 40.
Selecting unit 10, for selecting first processing module corresponding with target debugging signal, wherein, target debugging signal
For debugging objective chip.
Output unit 20, signal is debugged for exporting target by first processing module.
Control unit 30, in the case where allowing target to debug signal output to objective chip, control targe to be debugged
Signal output to objective chip, wherein, objective chip is connected with target bus.
Debugging unit 40, objective chip is debugged for debugging signal according to target by target bus.
Alternatively, selecting unit 10 includes：Selecting module, for by configuration register control first selector selection with
First processing module corresponding to target debugging signal, wherein, configuration register is located at the inside of objective chip.
Alternatively, output unit 20 includes：First output module, for controlling second selector to select by configuration register
The target debugging signal for selecting first processing module is exported.
Alternatively, control unit 30 includes：First control module, for allowing target to debug signal in gate processing module
In the case of output to objective chip, control targe debugs signal output to objective chip.
Alternatively, the device also includes：Monitoring unit, the first control unit and the second control unit.Wherein, monitoring is single
Member, for before debugging signal according to target by target bus and being debugged to objective chip, monitoring objective bus to be
The operation count value of the operation carried out to objective chip performed；First control unit, for being less than configuration in operation count value
In the case of the first object value of register configuration, control gate processing module is in first state, wherein, under first state
Gate processing module does not allow target to debug signal output to objective chip；Second control unit, in operation count value etc.
In the case of the first object value of configuration register configuration, control gate processing module is in the second state, wherein, the second shape
Gate processing module under state allows target to debug signal output to objective chip.
Alternatively, the first control unit includes：Second output module and the second control module.Wherein, the second output module,
For exporting the first mark, and target control signal is shielded, wherein, first identifies and is less than the first mesh for identifying operation count value
Scale value, target control signal are used to control gate processing module to be in the second state；Second control module, in output first
Mark, and after shielding target control signal, control gate processing module is in first state；
Second control unit includes：3rd output module and the 3rd control module.Wherein, the 3rd output module, for defeated
Go out the second mark, and enabled target control signal, wherein, second identifies and is equal to first object value for identifying operation count value；
3rd control module, in the mark of output second, and after enabled target control signal, control gate processing module is in the
Two-state.
Alternatively, the device also includes：Dispensing unit and determining unit.Wherein, dispensing unit, at control gate
Reason module is in after the second state, to the desired value of register configuration second；Determining unit, for being determined by the second desired value
Allow the operation count value of the operation carried out to objective chip of target bus execution.
Alternatively, debugging unit 40 includes：Debugging module, for performing the operation carried out to objective chip in target bus
After end, signal is debugged according to target by target bus objective chip is debugged.
The embodiment selects first processing module corresponding with target debugging signal by selecting unit 10, wherein, target
Debugging signal is used to debug objective chip, and output unit 20 exports target by first processing module and debugs signal, passes through control
For unit 30 in the case where allowing target to debug signal output to objective chip, control targe debugs signal output to target core
Piece, wherein, objective chip is connected with target bus, and debugging unit 40 debugs signal to target by target bus according to target
Chip is debugged.Due to debugging processing module corresponding to signal by selection, by selecting the debugging signal in processing module,
Chip is debugged according to debugging signal by target bus, so as to not increase the port number of chip, alleviates port number
It influence of the mesh to area, it also avoid that necessary behaviour can not be carried out to chip because bus port takes in debugging process
Make, solve the problems, such as that the efficiency of chip debugging is low, and then improve the effect of the debugging efficiency of chip.
Embodiment 4
The embodiments of the invention provide a kind of storage medium.The storage medium includes the program of storage, wherein, transported in program
Equipment performs the adjustment method of the chip of the embodiment of the present invention where controlling storage medium during row.
Embodiment 5
The embodiments of the invention provide a kind of processor.The processor is used for operation program, wherein, program performs when running
The adjustment method of the chip of the embodiment of the present invention.
Obviously, those skilled in the art should be understood that above-mentioned each module of the invention or each step can be with general
Computing device realize that they can be concentrated on single computing device, or be distributed in multiple computing devices and formed
Network on, alternatively, they can be realized with the receivable program code of computing device, it is thus possible to which they are stored
Performed in the storage device by computing device, either they are fabricated to respectively each integrated circuit modules or by they
In multiple modules or step be fabricated to single integrated circuit module to realize.So, the present invention is not restricted to any specific
Hardware and software combines.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made any repaiies
Change, equivalent substitution, improvement etc., should be included in the scope of the protection.
Claims (12)
- A kind of 1. adjustment method of chip, it is characterised in that including：Selection first processing module corresponding with target debugging signal, wherein, the target debugging signal is used to debug target core Piece；The target is exported by the first processing module and debugs signal；In the case where allowing the target to debug signal output to the objective chip, the target debugging signal output is controlled To the objective chip, wherein, the objective chip is connected with target bus；Signal is debugged by the target bus according to the target to debug the objective chip.
- 2. according to the method for claim 1, it is characterised in that selection debugs signal corresponding described first with the target Processing module includes：The first selector selection first processing module corresponding with target debugging signal is controlled by configuration register, Wherein, the configuration register is located at the inside of the objective chip.
- 3. according to the method for claim 2, it is characterised in that the target is exported by the first processing module and debugged Signal includes：Control second selector to select the target of the first processing module to debug signal by the configuration register to enter Row output.
- 4. according to the method for claim 2, it is characterised in that debug signal output to the target allowing the target In the case of chip, target debugging signal output to the objective chip is controlled to include：In the case where gate processing module allows the target to debug signal output to the objective chip, the target is controlled Signal output is debugged to the objective chip.
- 5. according to the method for claim 4, it is characterised in that believe being debugged by the target bus according to the target Before number the objective chip being debugged, methods described also includes：Monitor the operation count value for the operation carried out to the objective chip that the target bus have performed；In the case where the operation count value is less than the first object value of configuration register configuration, control at the gate Reason module is in first state, wherein, the gate processing module under the first state does not allow the target debugging letter Number output is to the objective chip；In the case where the operation count value is equal to the first object value of configuration register configuration, the door is controlled Control processing module is in the second state, wherein, the gate processing module under second state allows the target to debug Signal output is to the objective chip.
- 6. according to the method for claim 5, it is characterised in thatControlling the gate processing module to be in the first state includes：The mark of output first, and target control signal is shielded, Wherein, described first identify and be less than the first object value for identifying the operation count value, the target control signal use Second state is in controlling the gate processing module；First mark is being exported, and is shielding the target control After signal, the gate processing module is controlled to be in the first state；Controlling the gate processing module to be in second state includes：The mark of output second, and enable the target control Signal, wherein, described second identifies and is equal to the first object value for identifying the operation count value；In output described second Mark, and after the enabled target control signal, control the gate processing module to be in second state.
- 7. according to the method for claim 5, it is characterised in that be in second shape controlling the gate processing module After state, methods described also includes：To the desired value of register configuration second；The behaviour for the operation carried out to the objective chip for determining to allow the target bus to perform by second desired value Make count value.
- 8. method as claimed in any of claims 1 to 7, it is characterised in that by the target bus according to institute Target debugging signal is stated to carry out debugging to the objective chip and include：After the operation that target bus execution is carried out to the objective chip terminates, by the target bus according to institute Target debugging signal is stated to debug the objective chip.
- A kind of 9. debugging apparatus of chip, it is characterised in that including：Selecting unit, for selecting first processing module corresponding with target debugging signal, wherein, the target debugging signal is used In debugging objective chip；Output unit, signal is debugged for exporting the target by the first processing module；Control unit, in the case where allowing the target to debug signal output to the objective chip, controlling the mesh Mark debugs signal output to the objective chip, wherein, the objective chip is connected with target bus；Debugging unit, the objective chip is debugged for debugging signal according to the target by the target bus.
- 10. device according to claim 9, it is characterised in that the selecting unit includes：Selecting module, for controlling first selector selection and target debugging signal corresponding described by configuration register First processing module, wherein, the configuration register is located at the inside of the objective chip.
- A kind of 11. storage medium, it is characterised in that the storage medium includes the program of storage, wherein, run in described program When control the storage medium where chip in equipment perform claim requirement 1 to 8 described in any one adjustment method.
- A kind of 12. processor, it is characterised in that the processor is used for operation program, wherein, right of execution when described program is run Profit requires the adjustment method of the chip described in any one in 1 to 8.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110708137A (en) * | 2018-07-09 | 2020-01-17 | 北京集创北方科技股份有限公司 | Single-wire transmission method, chip and communication system |
| CN115391132A (en) * | 2022-06-14 | 2022-11-25 | 北京中科昊芯科技有限公司 | Monitoring and diagnosing device and chip |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1288160A (en) * | 1999-09-14 | 2001-03-21 | 日本电气株式会社 | Semiconductor integrated circuit and method for testing characteristics |
| CN101694512A (en) * | 2005-02-03 | 2010-04-14 | 三星电子株式会社 | Test circuit and on-chip system |
| CN102073009A (en) * | 2010-11-29 | 2011-05-25 | 杭州中天微系统有限公司 | System chip JTAG (Joint Test Action Group) debugging control method based on chip flash memory |
| CN102809934A (en) * | 2012-08-20 | 2012-12-05 | 桂林电子科技大学 | Boundary scan test controller for mixed signal circuit |
| CN103136138A (en) * | 2011-11-24 | 2013-06-05 | 炬力集成电路设计有限公司 | Chip, chip debugging method and communication method for chip and external devices |
| CN103376400A (en) * | 2012-04-27 | 2013-10-30 | 华为技术有限公司 | Chip testing method and chip |
| CN103699465A (en) * | 2013-12-16 | 2014-04-02 | 大唐微电子技术有限公司 | Device and method for performing debugging control on 16-bit chip inner core |
| CN105095040A (en) * | 2014-05-08 | 2015-11-25 | 中国科学院微电子研究所 | Chip debugging method and apparatus |
| CN105786576A (en) * | 2016-03-17 | 2016-07-20 | 硅谷数模半导体（北京）有限公司 | Chip debugging method and device based on serial port |
| CN206039399U (en) * | 2016-07-26 | 2017-03-22 | 湖南省计量检测研究院 | Embedded hardware systems with debugging facility |
| CN106951587A (en) * | 2017-02-15 | 2017-07-14 | 芯启源（南京）半导体科技有限公司 | FPGA debugging systems and method |
-
2017
- 2017-08-18 CN CN201710716024.0A patent/CN107607853B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1288160A (en) * | 1999-09-14 | 2001-03-21 | 日本电气株式会社 | Semiconductor integrated circuit and method for testing characteristics |
| CN101694512A (en) * | 2005-02-03 | 2010-04-14 | 三星电子株式会社 | Test circuit and on-chip system |
| CN102073009A (en) * | 2010-11-29 | 2011-05-25 | 杭州中天微系统有限公司 | System chip JTAG (Joint Test Action Group) debugging control method based on chip flash memory |
| CN103136138A (en) * | 2011-11-24 | 2013-06-05 | 炬力集成电路设计有限公司 | Chip, chip debugging method and communication method for chip and external devices |
| CN103376400A (en) * | 2012-04-27 | 2013-10-30 | 华为技术有限公司 | Chip testing method and chip |
| CN102809934A (en) * | 2012-08-20 | 2012-12-05 | 桂林电子科技大学 | Boundary scan test controller for mixed signal circuit |
| CN103699465A (en) * | 2013-12-16 | 2014-04-02 | 大唐微电子技术有限公司 | Device and method for performing debugging control on 16-bit chip inner core |
| CN105095040A (en) * | 2014-05-08 | 2015-11-25 | 中国科学院微电子研究所 | Chip debugging method and apparatus |
| CN105786576A (en) * | 2016-03-17 | 2016-07-20 | 硅谷数模半导体（北京）有限公司 | Chip debugging method and device based on serial port |
| CN206039399U (en) * | 2016-07-26 | 2017-03-22 | 湖南省计量检测研究院 | Embedded hardware systems with debugging facility |
| CN106951587A (en) * | 2017-02-15 | 2017-07-14 | 芯启源（南京）半导体科技有限公司 | FPGA debugging systems and method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110708137A (en) * | 2018-07-09 | 2020-01-17 | 北京集创北方科技股份有限公司 | Single-wire transmission method, chip and communication system |
| CN110708137B (en) * | 2018-07-09 | 2022-05-20 | 北京集创北方科技股份有限公司 | Single wire transmission method |
| CN115391132A (en) * | 2022-06-14 | 2022-11-25 | 北京中科昊芯科技有限公司 | Monitoring and diagnosing device and chip |
| CN115391132B (en) * | 2022-06-14 | 2024-03-29 | 北京中科昊芯科技有限公司 | Monitoring and diagnosing device and chip |
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|---|---|
| CN107607853B (en) | 2020-03-17 |
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