CN115391132A - Monitoring and diagnosing device and chip - Google Patents
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Abstract
The embodiment of the application provides a device and a chip for monitoring and diagnosing, wherein the device comprises: an enhanced bus comparator unit configured to monitor a target data bit of a target bus according to configuration information and generate an output event, wherein the target bus belongs to a program counter bus, an address write bus, an address read bus, a data write bus, or a data read bus; the system event counter unit is configured to analyze the monitored system under the control of the output event to obtain an analysis result; and the cyclic redundancy check module is configured to perform CRC check according to the triggering of the output event when the self-checking code is executed. The embodiment of the application can monitor the processor and the bus in multiple modes (such as data read-write bus monitoring, operation code monitoring and address read-write bus monitoring) simultaneously, and the monitoring range is more comprehensive.
Description
Technical Field
The present application relates to the field of processor performance detection, and in particular, to an embedded on-chip monitoring and diagnosing apparatus and chip.
Background
In the related art, in order to achieve the target of processor debugging and system analysis (for example, for full-phase debugging and analysis, a link Joint Test Action Group JTAG (Joint Test Action Group) sets a breakpoint on a chip through a JTAG interface so as to debug and analyze), an analysis unit is generally configured inside a processor to monitor a program counter bus through the analysis unit, and the analysis unit also provides the breakpoint after a target event is detected.
For example, as shown in fig. 1, the monitoring apparatus (i.e., the analysis unit in the previous paragraph) is located on the on-chip processor, and the monitoring module is configured to monitor the program counter and provide a target event breakpoint after detecting the target event.
It will be understood that the existing analysis unit (i.e. the monitoring module of fig. 1) has the following drawbacks: first, the type of monitoring event and the number of concurrent simultaneous monitoring are limited (only program counters are monitored) and software applications are not flexible enough. Second, because the monitor module is located on the kernel (i.e., on the CPU), when the module is configured according to the Reduced Instruction Set Computer-V (Reduced Instruction Set Computer-V) standard, the kernel may be stopped to run, which may cause a security risk. Thirdly, an intrusive debugger must be employed to configure and apply the monitoring module. Fourth, existing analytical units are relatively simple in function and difficult to perform in complex tasks.
Therefore, how to improve the monitoring effect of the processor event becomes a technical problem to be solved urgently.
Disclosure of Invention
The embodiment of the present application provides a device and a chip for monitoring and diagnosing, where multiple modes of monitoring (for example, data read/write bus monitoring, operation code monitoring, and address read/write bus monitoring) can be performed on a processor and a bus simultaneously, a monitoring range is more comprehensive, and a specific bit of a certain bus can be monitored by using the embodiment of the present application, and an object that is better in universality and can be monitored is more flexible.
In a first aspect, an embodiment of the present application provides an apparatus for monitoring and diagnosing, where the apparatus includes: an enhanced bus comparator unit configured to monitor a target data bit of a target bus according to configuration information and generate an output event, wherein the target bus belongs to a program counter bus, an address write bus, an address read bus, a data write bus, or a data read bus; the system event counter unit is configured to be controlled by the output event to analyze the monitored system to obtain an analysis result; and the cyclic redundancy check module is configured to perform CRC check on the monitored interface according to the triggering of the output event when the self-test code is executed.
In some embodiments of the present application, more types of buses to be monitored are provided, and monitored buses and monitoring bits on the buses are configurable, so that a monitoring range is increased, and in the embodiments of the present application, a counting module (i.e., a system event counter unit) and a CRC module (i.e., a cyclic redundancy check module) are further provided while monitoring some data bits on the buses or buses, so as to perform statistics and checks of multiple modes on the monitored buses.
In some embodiments, the enhanced bus comparator unit comprises: a first data selector configured to select at least one of the target buses from a plurality of kinds of buses according to a monitoring target selection control signal; the time sequence adjusting module is configured to adjust the time sequence of the monitoring signal according to the target bus to obtain target time for monitoring each item of the target bus; the second data selector is configured to perform mask processing on each entry tag bus according to a mask control signal and screen out target monitoring bus bits corresponding to each entry tag bus; a third data selector configured to generate a signal to be compared and a comparison enable signal according to the monitoring target selection control signal; the fourth data selector is configured to perform mask processing on the input monitoring reference comparison value to obtain a first monitoring target bus bit; a fifth data selector configured to perform mask processing on an output of the program counter to obtain a second monitoring target bus bit; a first match comparison module configured to derive a first output signal from a match mode control signal, the first monitored target bus bit, and the second monitored target bus bit; a second matching comparison module configured to derive a second output signal according to the matching mode control signal and an output signal of the third data selector; a sixth data selector configured to derive the output signal from the monitoring target selection control signal, the first output signal, and the second output signal.
Some embodiments of the present application provide an enhanced bus comparator unit structure composed of a multiplexer module and a comparator module, which can perform a monitoring task for a system according to configuration information.
In some embodiments, the enhanced bus comparator unit further comprises: and the monitoring target configuration register is configured to receive the configuration information to obtain the monitoring target selection control signal.
Some embodiments of the present application further implement the configurable monitoring object by setting a corresponding configuration register, thereby improving the universality of the technical solution.
In some embodiments, the enhanced bus comparator unit further comprises: a matching model configuration register configured to receive the configuration information to obtain the matching mode control signal.
Some embodiments of the present application further implement the configurable monitoring object by setting a corresponding configuration register, thereby improving the universality of the technical solution.
In some embodiments, the enhanced bus comparator unit further comprises: a mask configuration register configured to receive the configuration information resulting in the mask control signal.
Some embodiments of the present application further implement the configurable monitoring object by setting a corresponding configuration register, thereby improving the universality of the technical solution.
In some embodiments, the enhanced bus comparator unit further comprises: and the reference comparison value configuration register is configured to obtain the monitoring reference comparison value according to the configuration information.
Some embodiments of the present application further implement the configurable monitoring object by setting a corresponding configuration register, thereby improving the universality of the technical solution.
In some embodiments, the system event counter unit is configured to derive a target output from a user register configuration signal and a hardware input signal, wherein the target output comprises: a maximum count record value, a count value match output, a count value, or a count value overflow event output.
In some embodiments, the user register configuration signal comprises: an enable signal, a reset signal, a mode control signal, a reference signal, an input processing configuration signal, and a counter write signal.
In some embodiments, the system event counter unit comprises at least one counter, wherein each counter of the at least one counter comprises the following operating modes: a persistent mode, an event mode, and a start-stop mode.
Some embodiments of the present application implement system event counting functionality through multiple counters.
In some embodiments, the cyclic redundancy check module is configured to check a target interface, wherein the target interface includes a processor interface, a program counter interface, an address read-write bus interface, a data read-write bus interface, or an instruction register value security attribute check interface.
In some embodiments, the cyclic redundancy check module comprises: the second time sequence adjusting module is configured to obtain a target monitoring bus signal and a counting effective signal according to the input read-write effective signal and the target monitoring bus; a multiplexer configured to derive a CRC valid signal according to the system event, the count valid signal, and a CRC control signal output by the system event counting module; and the calculation unit is configured to obtain a target calculation result according to the CRC control signal, the counting effective signal and the target monitoring bus signal.
Some embodiments of the present application provide an architecture for a cyclic redundancy check unit.
In a second aspect, some embodiments of the present application provide a chip comprising a processor and an apparatus as in any embodiment of the first aspect.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts. Cyclic redundancy check module 110, enhanced bus comparator unit 120, and system event counter unit 130
Fig. 1 is a schematic view of a monitoring apparatus provided in the related art;
FIG. 2 is a block diagram of a system-on-chip architecture provided by an embodiment of the present application;
FIG. 3 is a block diagram of an enhanced bus comparator unit according to an embodiment of the present disclosure;
FIG. 4 is an architecture diagram of a system event counter unit according to an embodiment of the present application;
fig. 5 is an architecture diagram of a cyclic redundancy check module according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
At least in order to solve the technical problems in the background section, some embodiments of the present application provide a monitoring and diagnosis apparatus including an enhanced bus comparator unit, a system event counter unit, and a cyclic redundancy check module, which can perform monitoring and diagnosis on multiple target buses simultaneously, and a detection target may be configured to include, but is not limited to: CPU program counter, CPU instruction operation code, chip internal data address bus read/write address, and chip internal data address bus read/write data. The monitoring type is comprehensive and can carry out multiple monitoring simultaneously. In other embodiments of the present application, the system event counter unit may be configured to perform a complex counting mode while monitoring with the monitoring and diagnostic device, which advantageously provides better system profiling, analysis and debugging functions. For example: the code segment Profiling code segments may be parsed by the output of the unit, the duration between specified memory reads and writes may be counted, system events (e.g., interrupts) may be counted, the duration between system events may be calculated, a system timer may be implemented, the number of wait states in a code segment may be measured, the maximum amount of time spent between a pair of events may be measured, measuring in multiple iterations may link counters to link events or create a larger counter. In other embodiments of the present application, dedicated Cyclic Redundancy Check (CRC) units are provided, each for monitoring a different CPU interface, which facilitates a simpler, non-intrusive and interruptible self-test mechanism through the Software Test Library (STL).
Referring to fig. 2, fig. 2 provides a system on chip according to an embodiment of the present application, on which the apparatus 100 for monitoring and diagnosing provided in the embodiment of the present application is disposed, where the apparatus 100 includes: a cyclic redundancy check module 110, an enhanced bus comparator unit 120, and a system event counter unit 130.
An enhanced bus comparator unit 120 configured to monitor a target data bit of a target bus according to the configuration information and generate an output event, wherein the target bus belongs to a program counter bus, an address write bus, an address read bus, a data write bus, or a data read bus.
For example, in fig. 2, the enhanced bus comparator unit 120 is connected to the address bus interface 201, the data bus interface 202 and the program counter interface 203 of the on-chip processor 200 to monitor the relevant bus, the output signal of the enhanced bus comparator unit 120 of fig. 2 includes an interrupt/trigger/stop control signal output to the on-chip processor and an output matching signal (belonging to the output event of the enhanced bus comparator unit), and the matching signal can be used as an input or control signal of the cyclic redundancy check module 110 and the system event counter unit 130.
A system event counter unit 130 configured to analyze the monitored system under the control of the output event, resulting in an analysis result.
The enhanced bus comparator unit 120 may monitor a target to be monitored (e.g., address bus read/write, data bus read/write, program counter) according to configuration information, and output a matching signal when the monitored target reaches a write-starvation condition through configuration, where the matching signal may be used to stop the processor, or may provide an interrupt to the processor, and may also be used as an input of a count analysis module included in the system event counter unit 130 to perform various operations such as statistics, timing, or accumulation of events.
For example, in fig. 2, the system event counting unit 130 is connected to the system event module 300, and receives a signal output by the system event module. It should be noted that the system event counting unit 130 is also called a multipurpose counting analysis module, and the purpose of the module is to perform various counting functions on the input signal of the module, and when the count reaches a matching value, a matching signal is output. This match value is configurable. For example, the inputs to the system event counter unit 130 of FIG. 2 also include the match signal output by the enhanced bus comparator unit 120 and the resulting counter match event itself. The system event counter unit 130 of fig. 2 also issues interrupt/stop control signals to the processor.
And the cyclic redundancy check module 110 is configured to perform CRC check on the monitored interface according to the triggering of the output event when the self-test code is executed.
That is to say, in some embodiments of the present application, the types of buses to be monitored are more, and the monitored buses and the monitoring bits on the buses and other contents can be configured, which improves the monitoring range, and in some embodiments of the present application, a counting module (i.e., a system event counter unit) and a CRC module (i.e., a cyclic redundancy check module) are also provided while monitoring the buses or some data bits on the buses, so as to perform statistics and checks in multiple modes on the monitored buses.
The modules included in the embedded on-chip monitoring and diagnosing apparatus 100 are exemplarily described below with reference to fig. 3, fig. 4, and fig. 5.
As shown in fig. 3, in some embodiments of the present application, enhanced bus comparator unit 120 includes: a first data selector (i.e., MUX 1), a timing adjustment module, a second data selector (i.e., MUX 2), a third data selector (i.e., MUX 3), a fourth data selector (i.e., MUX 4), a fifth data selector (i.e., MUX 5), a first match compare module, a second match compare module, and a sixth data selector (i.e., MUX 6).
A first data selector configured to select at least one of the target buses from among a plurality of kinds of buses according to a monitor target selection control signal. And the time sequence adjusting module is configured to adjust the time sequence of the monitoring signal according to the target bus to obtain target time for monitoring each entry marker bus (namely, the time sequence adjustment made to the monitoring signal aiming at a critical path (critical path) of the time sequence of the monitoring signal, so that the time sequence requirement can be met while the monitoring function is ensured). And the second data selector is configured to perform mask processing on each entry tag bus according to a mask control signal and screen out target monitoring bus bits corresponding to each entry tag bus. A third data selector configured to generate a signal to be compared and a comparison enable signal according to the monitoring target selection control signal. And the fourth data selector is configured to perform mask processing on the input monitoring reference comparison value to obtain a first monitoring target bus bit. And the fifth data selector is configured to mask the output of the program counter to obtain a second monitoring target bus bit. A first match comparison module configured to derive a first output signal from a match mode control signal, the first monitored target bus bit, and the second monitored target bus bit. A second match comparison module configured to derive a second output signal from the match mode control signal and the output signal of the third data selector. And a sixth data selector configured to derive the output signal from the monitoring target selection control signal, the first output signal, and the second output signal.
Some embodiments of the present application provide an enhanced bus comparator unit structure composed of a multiplexer module and a comparator module, which can perform a monitoring task for a system according to configuration information.
In some embodiments of the present application, the enhanced bus comparator unit further comprises: and the monitoring target configuration register is configured to receive the configuration information to obtain the monitoring target selection control signal.
Some embodiments of the present application further implement the configurable monitoring object by setting a corresponding configuration register, thereby improving the universality of the technical solution.
In some embodiments of the present application, the enhanced bus comparator unit further comprises: a matching model configuration register configured to receive the configuration information to obtain the matching mode control signal.
Some embodiments of the present application further implement the configurable monitoring object by setting a corresponding configuration register, thereby improving the universality of the technical solution.
In some embodiments of the present application, the enhanced bus comparator unit further comprises: a mask configuration register configured to receive the configuration information resulting in the mask control signal.
Some embodiments of the present application further implement the configurable monitoring object by setting a corresponding configuration register, thereby improving the universality of the technical solution.
In some embodiments of the present application, the enhanced bus comparator unit further comprises: and the reference comparison value configuration register is configured to obtain the monitoring reference comparison value according to the configuration information.
Some embodiments of the present application further implement the configurable monitoring object by setting a corresponding configuration register, thereby improving the universality of the technical solution.
The structure of the enhanced comparison unit and the contents of input and output signals are exemplarily described below in connection with the working process of the unit.
In some embodiments of the present application an enhanced bus comparator unit has the following functionality, i.e. the output events (or output signals) of the unit include the following types: generating a hardware breakpoint; generating a hardware observation point; generating a tracking tag for instruction acquisition matching and generating a system interrupt RTOSINT; reading an address bus through monitoring data, writing the address bus into the monitoring data, writing the monitoring data into the data bus, and generating a system interrupt RTOSINT; event outputs are generated that are available to other modules by monitoring any program address bus, virtual Program Counter (VPC), or program counter of the CPU.
As described above, the enhanced bus comparator unit may be configured by a configuration register in some embodiments of the present application. The types of configuration information (i.e., the contents written into the corresponding configuration registers) include:
a. a target to be monitored is selected. Targets include, but are not limited to, program counters, address write buses, address read buses, data write buses, data read buses.
b. And matching the pattern. The pattern includes an absolute matching pattern, a matching pattern equal to or greater than the absolute matching pattern, a matching pattern equal to or less than the absolute matching pattern, and a matching pattern equal to or less than the absolute matching pattern.
c. And (4) mask configuration. For masking out the non-concerned bits, the masked bits will not be compared in the absolute match mode.
d. And configuring the reference comparison value. For comparison with the bus that needs to be monitored. Depending on the matching pattern and the detection target, the enhanced bus comparator unit may generate a corresponding interrupt, breakpoint or watch point.
The architecture of the enhanced bus comparison unit is shown in fig. 3, a control signal of the MUX1 is a monitoring target selection control signal configured by the system, in practical applications, multiple sets of buses are used simultaneously, and more application scenarios are obtained, and the MUX1 is used for selecting an address, data, and control bus monitored by the corresponding enhanced bus comparison unit. These buses then enter the timing adjustment logic, which adjusts the timing of the monitoring signals needed to monitor the target bus (i.e., the bus obtained by MUX 1) at the correct time. The MUX2 masks the monitored bus according to a mask control signal configured by the system so as to shield off the bus bits which do not need to be monitored. The MUX3 selects a control signal according to a monitoring target configured by the system, and generates a required signal to be compared and a comparison enabling signal. Then, a comparison logic is entered, and according to the system matching mode control signal (including an absolute matching mode, an equal to or greater than matching mode, an equal to or less than matching mode, and an equal to or less than matching mode), when the comparison enable signal is valid, the signal to be compared (the signal is generated according to the MASK signal of the configuration of the monitoring target and the software configuration, for example, the address read bus is to be monitored, the target to be monitored is the address bus, and the enable of the comparison is the bus read operation signal) and the monitoring reference signal (the monitoring reference signal is generated according to the MASK signal of the software configuration, that is, the software configuration, and is the reference value to be monitored, for example, if the read operation of the address 0xAA is to be monitored on the read bus, the monitoring reference signal is configured to be 0 xAA). When matched, a corresponding match output is generated.
The monitoring reference comparison value is processed by masking through the MUX4 to mask off bus bits which do not need to be monitored, and a monitoring reference signal is generated and used by corresponding comparison logic to generate a matching signal.
Also the program counter bus is masked by MUX5 to mask out bits of the bus that do not need to be monitored. And then entering a matching logic (namely a matching comparison module connected with the output of the MUX 5), and comparing the signal to be compared with the monitoring reference signal when the comparison enabling signal is effective according to a matching mode control signal configured by the system. When matched, a corresponding match output is generated. For example, the matching output includes: the CPU is given a matching triggering event, a corresponding breakpoint is generated, the internal COUNTER is given a corresponding count or the internal CRC module is given a corresponding CRC check.
Finally, through MUX6, control signals are selected according to the monitoring of the system configuration (for example, the detection target can be configured to include but not limited to CPU program counter, CPU instruction operation code, chip internal data address bus read/write address, chip internal data address bus read/write data), and the matched bus output to be monitored by the system is output. The MUX6 is a matching signal of the monitored target, which can be used to output to the processor to stop the processor from working or provide an interrupt to the processor, or output to the multipurpose count analysis module to be further processed, or enter the CRC module (i.e., cyclic redundancy check module) to be used as an event trigger signal for triggering CRC calculation of the module. It can be understood that, because of different monitoring timings, a part of the monitoring signals need to be subjected to timing adjustment, and a part of the signals cannot be subjected to timing adjustment through any flip-flop, then according to the selection of the monitoring target, the monitoring comparison module will finally output a corresponding matching signal.
It should be noted that each enhanced new bus match unit has a corresponding control signal to generate different configurations and outputs independent matched outputs, which may be configured as interrupts, processor stop signals, system event counter unit control signals, cyclic redundancy check unit enable signals. The flexible configuration is used in a system or debugging application.
The enhanced bus comparator unit output processing module (not shown in the figure) is provided with a processing module for the output of the multi-path enhanced bus comparator unit, the output can be subjected to AND operation and OR operation through user configuration, and the output after logic operation can also be used as an interrupt output, a system event counter unit control signal and a cyclic redundancy check unit enabling signal.
In some embodiments of the present application, the system event counter unit 130 is configured to derive a target output according to the user register configuration signal and the hardware input signal, wherein the target output comprises: a maximum count record value, a count value match output, a count value, or a count value overflow event output.
Some embodiments of the present application provide core functionality of a system event counter unit.
In some embodiments of the present application, the user register configuration signal comprises: an enable signal, a reset signal, a mode control signal, a reference signal, an input processing configuration signal, and a counter write signal. In some embodiments of the present application, the system event counter unit includes at least one counter, wherein each counter of the at least one counter includes the following operation modes: a persistent mode, an event mode, and a start-stop mode. That is, some embodiments of the present application implement the system event counting function by multiple counters.
The structure and function of the system event counter will be described in detail below with reference to fig. 4.
In some embodiments of the present application, a system event counter unit, which includes a counter, provides better system profiling, analysis, and debugging functionality, which may enhance the debugging and analysis process in various types of system scenarios, such as: parsing a code segment profilengcode segments; counting the duration between a specified memory read and write; counting system events (e.g., interrupts); calculating a duration between system events; a system timer; measuring a number of wait states in the code segment; measuring a maximum amount of time spent between a pair of events, measured in a plurality of iterations; the counters are linked to link events or create larger counters.
It should be noted that, in other embodiments of the present application, the system event counter unit further has the following functions:
first, as a function of a counter capable of counting, specifically, the method includes:
any match events generated by the enhanced bus comparator unit are counted. Events generated by the enhanced bus comparator unit that can be used to start and stop counting. System event control, including interrupts, timer interrupts, and other system events. These system events can be used to start and stop counting. If the count reaches the reference value, an interrupt or observation point is generated.
Second, if the count reaches a reference value, an interrupt or observation point is generated.
Third, multiple counting modes.
For example, the architecture of the system event counter unit according to some embodiments of the present application is shown in fig. 5, where the input of the system event counter unit is divided into two parts:
one user register configuration signal:
unit enable signal: for starting the system event counter unit.
Unit reset signal: for resetting the system event counter unit.
Mode control signal: for controlling the behaviour of counters in the system event counter unit.
The specific counting mode of the counter.
The behavior of the counter when a match or stop event occurs while the counter is in a different mode.
When the counter is in different modes, the counter responds to the counting trigger signal, such as edge response and level response.
Reference REF signal: the counter unit generates a match signal for a system event, and a match is established when the count value of the counter equals the REF value.
Inputting a processing configuration signal: for configuring the tuning control of hardware inputs. Including but not limited to synchronization, reverse, etc., adjustment operations.
CNT _ WR counter write signal: used in conjunction with REG _ WR _ DATA, software is enabled to directly configure the value of the counter in the system event counter unit.
CNT _ MAX _ WR counter write signal: for use with REG _ WR _ DATA, software can directly configure the counter maximum count entry value.
Hardware input signal:
CNT _ INPUT _ SIG: used in event mode for counting as a counter in an event trigger unit.
CNT _ RESET _ SIG: is used in each mode for resetting the counter in the unit.
CNT _ START _ SIG: used in 'start-stop' mode for starting the counter in the unit for successive counts.
CNT _ STOP _ SIG: used in 'start-stop' mode for stopping the counting of the counters in the unit.
The outputs of the system event counter unit are:
the system event counter unit counter counts the maximum record value.
And secondly, counting the value of the counter of the system event counter unit.
And thirdly, matching and outputting the counter value of the system event counter unit.
And fourthly, outputting the counting value overflow event of the counter of the system event counter unit.
It should be noted that, in some embodiments of the present application, the counter in the system event counter unit includes the following operation modes:
a continuous mode: the counter counts processor cycles as long as the event is active.
Event mode: the counter counts when CNT _ INPUT _ SIG is active.
A start stop mode: in this mode, two events are allowed as start and stop indicators for the counter. The counter will only start counting when a defined start event occurs. The counter will then continue to count until a stop event occurs. After the first start event occurs, more start events will be ignored until a stop event occurs. He also has two submodes
Maximum mode: this mode allows the user to detect the maximum count occurring during the various count iterations in the start stop mode. For example, the user may set a counter in a start stop count mode to count the duration of a key code loop. Each time a stop event occurs and the counter stops, the counter value is checked against the current MAX _ COUNT in the register. If the new value is larger, the max count register is updated. The counter will always reset to zero at the stop event and be ready to start counting at the next start event. Thus, MAX _ COUNT will contain the maximum number of cycles that occur between the start and stop conditions in multiple iterations.
Accumulation counting mode: the system event counter unit may be operable to generate a cumulative count of a plurality of start and stop events. In this mode, unlike the maximum mode, the counter is not reset by a stop event. Conversely, when a start event occurs, it stops counting and resumes counting. In the accumulation COUNT mode, MAX _ COUNT is invalid.
The cyclic redundancy check module is exemplarily set forth below.
In some embodiments of the present application, the cyclic redundancy check module is configured to check a target interface, where the target interface includes a processor interface, a program counter interface, an address read/write bus interface, a data read/write bus interface, or an instruction register value security attribute check interface.
In some embodiments of the present application, the cyclic redundancy check module comprises: a second timing adjustment module (corresponding to the timing adjustment module in fig. 3) configured to obtain a target monitoring bus signal and a counting effective signal according to the input read-write effective signal and the target monitoring bus; a multiplexer (corresponding to MUX1 in fig. 3) configured to provide CRC calculation enable and data signals for each CRC unit calculation unit according to the system events outputted by the system event counting module (for example, there are 8 CRC units, each of which corresponds to a different calculation target, and they are respectively subjected to timing adjustment, and a multiplexer is further provided for each CRC unit, so as to select other events as the calculation enable signal of the CRC unit), the count valid signal, and the CRC control signal to obtain a CRC valid signal; a calculating unit (corresponding to the CRC calculating unit of fig. 5) configured to obtain a target calculation result according to the CRC control signal, the count valid signal, and the target monitoring bus signal.
Some embodiments of the present application provide an architecture for a cyclic redundancy check unit.
The architecture of the cyclic redundancy check unit of some embodiments of the present application is illustrated below with reference to fig. 5.
In some embodiments of the present application, a Cyclic Redundancy Check (CRC) unit monitors the processor bus and calculates the CRC when executing self-test code. This functionality facilitates a simpler, non-intrusive and interruptible self-test mechanism through the Software Test Library (STL). Each CRC unit is used to monitor a different processor interface. For example, CRC unit 1 is used to monitor the program counter, while CRC unit 2 is used to monitor the data read address bus. Table 1 shows the processor interface monitored by each CRC unit.
TABLE 1 processor interface for each CRC unit monitoring
| CRC unit | Processor interface |
| CRC1 | Program counter |
| CRC2 | Address read bus |
| CRC3 | Address writing bus |
| CRC4 | Data reading bus |
| CRC5 | Data write bus |
| CRC6 | Instruction register value (non-secure zone) |
| CRC7 | Instruction register value (safe zone 1) |
| CRC8 | Instruction register value (safe zone 2) |
The primary purpose of the CRC unit is to ensure that the functionality remains intact when the processor executes the same software test library in multiple iterations. This is achieved by comparing the CRC value calculated after each iteration with a pre-calculated standard value.
CRC7 and CRC8 in the above tables are used to calculate the instruction register values for execution of the secure enclave 1 and secure enclave 2 instructions. The calculated CRC value for a given security region is applicable only to accesses originating from that region.
The architecture of the Cyclic Redundancy Check (CRC) unit is shown in fig. 5, and the interface signals are as follows:
monitoring bus signals: as shown in Table 1, different CRC units correspond to different monitor buses
Corresponding to the monitoring read-write effective signal: CRC calculations are only enabled if valid.
Inputting system events: including external system events, enhanced new compare element match event logic processing outputs, and system event count element match events, which may be used to enable CRC element computation by configuring CRC computation enable select signals
A register configured CRC control signal. They include:
CRC calculation enable strobe signal: to select valid signals that enable CRC computations.
CRC seed signal: for configuring the initial value of the CRC calculation.
CRC function enable signal: a function enable signal.
CRC initialization signal: for the initial CRC segmentation calculation unit.
In some embodiments of the present application, each CRC unit has its own monitor signal, the monitor calculates the corresponding event, the monitor signal is adjusted in timing, and the CRC calculation can be enabled at the correct event. By default, all valid events on a given interface enable the CRC unit to perform the computation. However, by configuring the CRC calculation enable strobe signal, it can be used to strobe the CRC calculation when a valid event occurs. For example: the enhanced bus compare unit is capable of monitoring program counters, data writes and data reads. The CRC unit may use an enhanced bus comparison unit to decide when the check value should be calculated. For example, if the check value needs to be calculated only when the processor is performing a particular function, the user may set the enhanced bus compare unit to monitor the program counter and generate a CRC qualifier when performing that function. This allows the CRC unit to calculate the check value only when needed.
It is understood that some embodiments of the present application can monitor more system events and have more flexibility in application by using a dedicated enhanced comparator unit, a system event counting unit and a cyclic redundancy check unit. The device provided by the application can be used by a debugger and also can be used by application software. For many real-time systems, it is not always possible to connect a debugger and perform intrusive debugging. In these cases, the user code can set up and control the device to debug and evaluate the system without disturbing the interrupted application.
It should be noted that, the monitored bus may have different monitoring contents due to different processor models and different configurations of the internal bus of the chip, and the monitored contents are related to the architecture of the system. The system event counter can have different mode combinations, can modify and delete and add different functions, and the priority can also be changed. The CRC calculation unit changes the structure according to the bit width of the monitoring bus and is related to the architecture of the system. These embodiments are all included in the embodiments of the present application.
Some embodiments of the present application provide a chip comprising a processor and a means of monitoring diagnostics as described in the above embodiments, as illustrated in fig. 2.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, the technical solutions of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
Claims (11)
1. An apparatus for monitoring diagnostics, the apparatus comprising:
an enhanced bus comparator unit configured to monitor a target bus according to configuration information and generate an output event, wherein the target bus belongs to a program counter bus, an address write bus, an address read bus, a data write bus, or a data read bus;
the system event counter unit is configured to be controlled by the output event to analyze the monitored system to obtain an analysis result;
and the cyclic redundancy check module is configured to perform CRC check on the monitored interface according to the triggering of the output event when the self-test code is executed.
2. The apparatus of claim 1, wherein the enhanced bus comparator unit comprises:
a first data selector configured to select at least one of the target buses from a plurality of kinds of buses according to a monitoring target selection control signal;
the time sequence adjusting module is configured to adjust the time sequence of the monitoring signal according to the target bus to obtain target time for monitoring each item of the target bus;
the second data selector is configured to perform mask processing on each entry tag bus according to a mask control signal and screen out target monitoring bus bits corresponding to each entry tag bus;
a third data selector configured to generate a signal to be compared and a comparison enable signal according to the monitoring target selection control signal;
the fourth data selector is configured to perform mask processing on the input monitoring reference comparison value to obtain a first monitoring target bus bit;
a fifth data selector configured to perform mask processing on an output of the program counter to obtain a second monitoring target bus bit;
a first match comparison module configured to derive a first output signal from a match mode control signal, the first monitored target bus bit, and the second monitored target bus bit;
a second matching comparison module configured to derive a second output signal according to the matching mode control signal and an output signal of the third data selector;
a sixth data selector configured to derive the output signal from the monitoring target selection control signal, the first output signal, and the second output signal.
3. The apparatus of claim 2, wherein the enhanced bus comparator unit further comprises:
and the monitoring target configuration register is configured to receive the configuration information to obtain the monitoring target selection control signal.
4. The apparatus of claim 2, wherein the enhanced bus comparator unit further comprises:
a matching model configuration register configured to receive the configuration information to obtain the matching mode control signal.
5. The apparatus of claim 2, wherein the enhanced bus comparator unit further comprises:
a mask configuration register configured to receive the configuration information resulting in the mask control signal.
6. The apparatus of claim 2, wherein the enhanced bus comparator unit further comprises:
and the reference comparison value configuration register is configured to obtain the monitoring reference comparison value according to the configuration information.
7. The apparatus of any one of claims 1-6, wherein the system event counter unit is configured to derive a target output based on a user register configuration signal and a hardware input signal, wherein the target output comprises: a maximum count record value, a count value match output, a count value, or a count value overflow event output.
8. The apparatus of claim 7, wherein the user register configuration signal comprises: an enable signal, a reset signal, a mode control signal, a reference signal, an input processing configuration signal, and a counter write signal.
9. The apparatus of claim 8, wherein the system event counter unit comprises at least one counter, wherein each counter of the at least one counter comprises the following modes of operation: a persistent mode, an event mode, and a start-stop mode.
10. The apparatus of claim 8, wherein the cyclic redundancy check module comprises:
the second time sequence adjusting module is configured to obtain a target monitoring bus signal and a counting effective signal according to the input read-write effective signal and at least one bus;
a multiplexer configured to derive a CRC valid signal from a system event, the count valid signal, and a CRC control signal;
and the calculation unit is configured to obtain a target calculation result according to the CRC control signal, the counting valid signal and the target monitoring bus signal.
11. A chip comprising a processor and an apparatus according to any of claims 1-10.
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