CN115391132B - Monitoring and diagnosing device and chip - Google Patents
Monitoring and diagnosing device and chip Download PDFInfo
- Publication number
- CN115391132B CN115391132B CN202210668784.XA CN202210668784A CN115391132B CN 115391132 B CN115391132 B CN 115391132B CN 202210668784 A CN202210668784 A CN 202210668784A CN 115391132 B CN115391132 B CN 115391132B
- Authority
- CN
- China
- Prior art keywords
- bus
- signal
- monitoring
- target
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012544 monitoring process Methods 0.000 title claims abstract description 108
- 125000004122 cyclic group Chemical group 0.000 claims abstract description 27
- 238000004364 calculation method Methods 0.000 claims description 18
- 238000012545 processing Methods 0.000 claims description 11
- 238000012360 testing method Methods 0.000 claims description 6
- 238000003745 diagnosis Methods 0.000 abstract description 2
- 230000006870 function Effects 0.000 description 20
- 238000000034 method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 230000009471 action Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000001186 cumulative effect Effects 0.000 description 3
- 230000006399 behavior Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000012806 monitoring device Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 101100258328 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) crc-2 gene Proteins 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3027—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Computer Security & Cryptography (AREA)
- Debugging And Monitoring (AREA)
Abstract
The embodiment of the application provides a device and chip for monitoring diagnosis, wherein the device comprises: an enhanced bus comparator unit configured to monitor a target data bit of a target bus belonging to a program counter bus, an address write bus, an address read bus, a data write bus, or a data read bus according to configuration information and generate an output event; the system event counter unit is configured to analyze the monitored system under the control of the output event to obtain an analysis result; a cyclic redundancy check module configured to perform a CRC check upon triggering of the output event when executing a self-checking code. The embodiment of the application can monitor the processor and the bus in various modes (such as data read-write bus monitoring, operation code monitoring and address read-write bus monitoring) at the same time, and the monitoring range is more comprehensive.
Description
Technical Field
The present application relates to the field of processor performance detection, and in particular, embodiments of the present application relate to an apparatus and a chip for embedded on-chip monitoring and diagnosis.
Background
In order to achieve the goals of processor debugging and system analysis (for example, for full-phase debugging and analysis, the link joint test workgroup JTAG (Joint Test Action Group) sets a breakpoint to a chip through a JTAG interface so as to debug and analyze), an analysis unit is generally configured inside the processor to monitor a program counter bus through the analysis unit, and the analysis unit also provides a breakpoint after detecting a target event.
For example, as shown in fig. 1, the monitoring device (i.e. the analysis unit of the previous stage) is located on the on-chip processor, and the monitoring module is used for monitoring the program counter, and giving a target event breakpoint after detecting a target event.
It will be appreciated that existing analysis units (i.e. the monitoring module of fig. 1) suffer from the following drawbacks: first, the type of monitoring event and the number of parallel synchronous monitoring are limited (only the monitor counter), and software applications are not flexible enough. Second, because the monitoring module is located on the kernel (i.e., the CPU), when the module is configured according to the VRISCV (Reduced Instruction Set Computer-V) standard, the kernel is stopped to run, thereby causing a security risk. Third, an intrusive debugger must be used to configure and apply the monitoring module. Fourth, existing analysis units are relatively simple in functionality and difficult to accomplish complex tasks.
Therefore, how to improve the monitoring effect on the processor event is a technical problem to be solved.
Disclosure of Invention
An object of the embodiment of the present application is to provide a device and a chip for monitoring and diagnosing, through the embodiment of the present application, multiple modes of monitoring (for example, data read-write bus monitoring, operation code monitoring and address read-write bus monitoring) can be performed on a processor and a bus at the same time, the monitoring range is more comprehensive, and by adopting the embodiment of the present application, a specific bit of a certain bus can be monitored, and the object that can be monitored with better universality of the scheme is more flexible.
In a first aspect, embodiments of the present application provide an apparatus for monitoring diagnostics, the apparatus comprising: an enhanced bus comparator unit configured to monitor a target data bit of a target bus belonging to a program counter bus, an address write bus, an address read bus, a data write bus, or a data read bus according to configuration information and generate an output event; the system event counter unit is configured to analyze the monitored system under the control of the output event to obtain an analysis result; a cyclic redundancy check module configured to CRC check the monitored interface upon triggering of the output event when executing the self-test code.
The bus types monitored by some embodiments of the present application are more, and the content such as the monitored bus and the monitored bit on the bus are configurable, so that the monitoring range is improved, and the embodiments of the present application are provided with a counting module (i.e. a system event counter unit) and a CRC module (i.e. a cyclic redundancy check module) while monitoring the bus or some data bits on the bus, so as to perform statistics and check of multiple modes on the monitored bus.
In some embodiments, the enhanced bus comparator unit comprises: a first data selector configured to select at least one of the target buses from among a plurality of buses according to a monitoring target selection control signal; the time sequence adjusting module is configured to adjust the time sequence of the monitoring signal according to the target bus to obtain the target time of each item of target bus; the second data selector is configured to mask each item target bus according to the mask control signal and screen out target monitoring bus bits corresponding to each item target bus; a third data selector configured to generate a signal to be compared and a comparison enable signal according to the monitoring target selection control signal; a fourth data selector configured to mask the input monitoring reference comparison value to obtain a first monitoring target bus bit; a fifth data selector configured to mask the output of the program counter to obtain a second monitor target bus bit; the first matching comparison module is configured to obtain a first output signal according to the matching mode control signal, the first monitoring target bus bit and the second monitoring target bus bit; a second match comparing module configured to obtain a second output signal according to the match mode control signal and the output signal of the third data selector; a sixth data selector configured to obtain the output signal from the monitor target selection control signal, the first output signal, and the second output signal.
Some embodiments of the present application provide an architecture of an enhanced bus comparator unit consisting of a multiplexing module and a comparison module that can perform monitoring tasks on a system based on configuration information.
In some embodiments, the enhanced bus comparator unit further comprises: and the monitoring target configuration register is configured to receive the configuration information to obtain the monitoring target selection control signal.
Some embodiments of the present application further implement the configurability of the monitoring object by setting the corresponding configuration register, thereby improving the universality of the technical scheme.
In some embodiments, the enhanced bus comparator unit further comprises: and the matching model configuration register is configured to receive the configuration information to obtain the matching mode control signal.
Some embodiments of the present application further implement the configurability of the monitoring object by setting the corresponding configuration register, thereby improving the universality of the technical scheme.
In some embodiments, the enhanced bus comparator unit further comprises: a mask configuration register configured to receive the configuration information to obtain the mask control signal.
Some embodiments of the present application further implement the configurability of the monitoring object by setting the corresponding configuration register, thereby improving the universality of the technical scheme.
In some embodiments, the enhanced bus comparator unit further comprises: and a reference comparison value configuration register configured to obtain the monitoring reference comparison value according to the configuration information.
Some embodiments of the present application further implement the configurability of the monitoring object by setting the corresponding configuration register, thereby improving the universality of the technical scheme.
In some embodiments, the system event counter unit is configured to derive a target output from the user register configuration signal and the hardware input signal, wherein the target output comprises: the maximum count records a value, a count value match output, a count value, or a count value overflow event output.
In some embodiments, the user register configuration signal comprises: an enable signal, a reset signal, a mode control signal, a reference signal, an input processing configuration signal, and a counter write signal.
In some embodiments, the system event counter unit comprises at least one counter, wherein each of the at least one counter comprises the following modes of operation: a continuous mode, an event mode, and a start stop mode.
Some embodiments of the present application implement a system event counting function through multiple counters.
In some embodiments, the cyclic redundancy check module is configured to check a target interface, wherein the target interface comprises a processor interface, a program counter interface, an address read-write bus interface, a data read-write bus interface, or an instruction register value security attribute check interface.
In some embodiments, the cyclic redundancy check module comprises: the second time sequence adjusting module is configured to obtain a target monitoring bus signal and a counting effective signal according to the input reading and writing effective signal and the target monitoring bus; a multiplexer configured to obtain a CRC valid signal from the system event, the count valid signal, and a CRC control signal output by the system event counting module; and a calculating unit configured to obtain a target calculation result according to the CRC control signal, the count valid signal and the target monitoring bus signal.
Some embodiments of the present application provide an architecture for a cyclic redundancy check unit.
In a second aspect, some embodiments of the present application provide a chip comprising a processor and an apparatus as described in any embodiment of the first aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Cyclic redundancy check module 110, enhanced bus comparator unit 120, and system event counter unit 130
FIG. 1 is a schematic diagram of a monitoring device according to the related art;
FIG. 2 is a diagram of a system-on-chip architecture provided in an embodiment of the present application;
FIG. 3 is a block diagram of an enhanced bus comparator unit according to an embodiment of the present disclosure;
FIG. 4 is a block diagram of a system event counter unit according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a cyclic redundancy check module according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
To address at least the technical shortcomings of the background section, some embodiments of the present application provide a monitoring and diagnostic apparatus including an enhanced bus comparator unit, a system event counter unit, and a cyclic redundancy check module, which can simultaneously monitor and diagnose a plurality of target buses, and the detection targets can be configured to include, but are not limited to: the CPU program counter, CPU instruction operation code, internal data address bus read/write address and internal data address bus read/write data. The monitoring type is comprehensive and multiple monitoring can be performed simultaneously. In other embodiments of the present application, the system event counter unit may be configured to perform complex counting modes while monitoring with the monitoring diagnostic device, which has the advantage of providing better system profiling, analysis and debugging functions. For example: the output of this unit may parse the code segment Profiling code segments, may count the duration between a given memory read and write, may count system events (e.g., interrupts), may calculate the duration between system events, may implement a system timer, may measure the number of wait states in the code segment, may measure the maximum amount of time spent between a pair of events, may link the counter in multiple iterations, or may create a larger counter. In other embodiments of the present application, dedicated Cyclic Redundancy Check (CRC) units are provided, each for monitoring a different CPU interface, which facilitates a simpler, non-invasive and interruptible self-checking mechanism through a Software Test Library (STL).
Referring to fig. 2, fig. 2 is a system on a chip provided with the apparatus 100 for monitoring and diagnosing according to the embodiment of the present application, where the apparatus 100 includes: a cyclic redundancy check module 110, an enhanced bus comparator unit 120, and a system event counter unit 130.
The enhanced bus comparator unit 120 is configured to monitor target data bits of a target bus belonging to a program counter bus, an address write bus, an address read bus, a data write bus or a data read bus according to configuration information and generate an output event.
For example, in fig. 2 the enhanced bus comparator unit 120 is connected to the address bus interface 201, the data bus interface 202 and the program counter interface 203 of the on-chip processor 200 to enable monitoring of the relevant bus, the output signals of the enhanced bus comparator unit 120 of fig. 2 comprise interrupt/trigger/stop control signals output to the on-chip processor and output match signals (belonging to the output event of the enhanced bus comparator unit) which may be input or control signals of the cyclic redundancy check module 110 and the system event counter unit 130.
And the system event counter unit 130 is configured to analyze the monitored system under the control of the output event to obtain an analysis result.
The enhanced bus comparator unit 120 can monitor the target to be monitored (such as address bus read-write, data bus read-write, program counter) according to the configuration information, and through configuration, when the monitored target reaches the implied condition, output a matching signal, where the matching signal can be used to stop the processor, or can also interrupt the processor, and can be used as input of the counting analysis module included in the system event counter unit 130 to perform various operations such as statistics, timing or accumulation of events.
For example, in fig. 2 the system event counting unit 130 is connected to the system event module 300, and receives signals output by the system event module. It should be noted that, the system event counting unit 130 is also referred to as a multipurpose counting analysis module, and the module is used for performing various counting functions on the input signal of the module, and outputting a matching signal when the count reaches a matching value. This match value is configurable. For example, the input of the system event counter unit 130 of fig. 2 also includes the match signal output by the enhanced bus comparator unit 120 and the counter match event itself. The system event counter unit 130 of fig. 2 also issues interrupt/stop control signals to the processor.
A cyclic redundancy check module 110 configured to CRC check the monitored interface upon triggering of the output event when executing the self-test code.
That is, some embodiments of the present application monitor more types of buses and monitor bits on the buses, which improves the monitoring range, and the embodiments of the present application monitor some data bits on the buses or buses and simultaneously provide a counting module (i.e. a system event counter unit) and a CRC module (i.e. a cyclic redundancy check module), which perform statistics and check of multiple modes on the monitored buses, and in application, because these functions are added, the monitoring task becomes more flexible and can complete more complex programs and tasks.
The modules included in the embedded on-chip monitoring and diagnostics apparatus 100 are exemplarily described below in conjunction with fig. 3, 4, and 5.
As shown in fig. 3, in some embodiments of the present application, the enhanced bus comparator unit 120 includes: the data processing device comprises a first data selector (i.e. MUX 1), a timing adjustment module, a second data selector (i.e. MUX 2), a third data selector (i.e. MUX 3), a fourth data selector (i.e. MUX 4), a fifth data selector (i.e. MUX 5), a first match comparison module, a second match comparison module and a sixth data selector (i.e. MUX 6).
And a first data selector configured to select at least one of the target buses from among a plurality of buses according to a monitor target selection control signal. The time sequence adjustment module is configured to adjust the time sequence of the monitoring signal according to the target bus, so as to obtain the target time (namely, the critical path for the time sequence of the monitoring signal) of each item target bus, and the time sequence adjustment is performed on the monitoring signal, so that the time sequence requirement can be met while the monitoring function is ensured. And the second data selector is configured to perform mask processing on each item target bus according to the mask control signal and screen out target monitoring bus bits corresponding to each item target bus. And a third data selector configured to generate a signal to be compared and a comparison enable signal according to the monitoring target selection control signal. And the fourth data selector is configured to mask the input monitoring reference comparison value to obtain the first monitoring target bus bit. And a fifth data selector configured to mask the output of the program counter to obtain a second monitor target bus bit. The first matching comparison module is configured to obtain a first output signal according to the matching mode control signal, the first monitoring target bus bit and the second monitoring target bus bit. And the second matching comparison module is configured to obtain a second output signal according to the matching mode control signal and the output signal of the third data selector. And a sixth data selector configured to obtain the output signal from the monitor target selection control signal, the first output signal, and the second output signal.
Some embodiments of the present application provide an architecture of an enhanced bus comparator unit consisting of a multiplexing module and a comparison module that can perform monitoring tasks on a system based on configuration information.
In some embodiments of the present application, the enhanced bus comparator unit further comprises: and the monitoring target configuration register is configured to receive the configuration information to obtain the monitoring target selection control signal.
Some embodiments of the present application further implement the configurability of the monitoring object by setting the corresponding configuration register, thereby improving the universality of the technical scheme.
In some embodiments of the present application, the enhanced bus comparator unit further comprises: and the matching model configuration register is configured to receive the configuration information to obtain the matching mode control signal.
Some embodiments of the present application further implement the configurability of the monitoring object by setting the corresponding configuration register, thereby improving the universality of the technical scheme.
In some embodiments of the present application, the enhanced bus comparator unit further comprises: a mask configuration register configured to receive the configuration information to obtain the mask control signal.
Some embodiments of the present application further implement the configurability of the monitoring object by setting the corresponding configuration register, thereby improving the universality of the technical scheme.
In some embodiments of the present application, the enhanced bus comparator unit further comprises: and a reference comparison value configuration register configured to obtain the monitoring reference comparison value according to the configuration information.
Some embodiments of the present application further implement the configurability of the monitoring object by setting the corresponding configuration register, thereby improving the universality of the technical scheme.
The structure of the unit and the input and output signals are exemplarily described below in connection with the operation of the enhanced comparison unit.
In some embodiments of the present application the enhanced bus comparator unit has the function that the output event (or output signal) of the unit comprises the following types: generating a hardware breakpoint; generating a hardware observation point; generating a tracking mark for instruction acquisition matching and generating a system interrupt RTOSINT; the address bus is read through the monitoring data, the address bus is monitored and written through the monitoring data, the data is written into the data bus through the monitoring data, and the system interrupt RTOSINT is generated; event outputs are generated for use by other modules by monitoring any program address bus, virtual Program Counter (VPC), or program counter of the CPU.
As described above, the enhanced bus comparator unit may be configured by a configuration register in some embodiments of the present application. The type of configuration information (i.e., the content written into the corresponding configuration register) includes:
a. A target for monitoring is selected. Targets include, but are not limited to, program counter, address write bus, address read bus, data write bus, data read bus.
b. Matching patterns. The method comprises an absolute matching mode, a matching mode which is greater than or equal to the absolute matching mode, a matching mode which is less than or equal to the absolute matching mode, and a matching mode which is less than the absolute matching mode.
c. And (5) mask configuration. For masking bits that are not of interest, in absolute match mode the masked bits will not be compared.
d. Reference is made to the comparison value configuration. For comparison with the bus that needs to be monitored. Depending on the matching pattern and the detection target, the enhanced bus comparator unit may generate a corresponding interrupt, breakpoint or monitoring point.
As shown in FIG. 3, the architecture of the enhanced bus comparison unit is that the control signal of the MUX1 is a control signal selected by a monitoring target of the system configuration, and in practical application, multiple buses are used simultaneously, so that more application scenarios are obtained, and the MUX1 is used for selecting the address, data and control buses monitored by the corresponding enhanced bus comparison unit. These buses then enter timing adjustment logic to adjust the desired supervisory signal timing to monitor the target bus (i.e., the bus derived by MUX 1) at the correct time. The MUX2 masks the bus under monitoring according to a mask control signal configured by the system to mask out bus bits that do not need to be monitored. The MUX3 selects a control signal according to a monitoring target of the system configuration, and generates a desired signal to be compared and a comparison enable signal. Then, a comparison logic is entered, and when the comparison enable signal is valid, the comparison enable signal is compared (the signal is generated according to the configuration of the monitor target and the MASK signal of the software configuration, for example, the address read bus is to be monitored, the target of the monitoring is the address bus, the compared enable signal is the bus read operation signal) with the monitor reference signal (the monitor reference signal is generated by the MASK signal of the software configuration, for example, the monitor reference signal is configured as 0xAA if the read address bus is to be monitored, and the monitor reference signal is generated by the MASK signal of the software configuration, for example, the read operation of the address 0xAA is to be monitored). When matched, a corresponding match output is generated.
The processing of the monitor reference comparison value is to mask the bus bits not requiring monitoring through the MUX4, and generate the monitor reference signal to be used by the corresponding comparison logic to generate the matching signal.
The program counter bus is also masked by MUX5 to mask out bus bits that do not need to be monitored. And then, a matching logic (namely a matching comparison module connected with the output of the MUX 5) is entered, and the signal to be compared and the monitoring reference signal are compared when the comparison enabling signal is valid according to a matching mode control signal configured by the system. When matched, a corresponding match output is generated. For example, the matching output includes: the method comprises the steps of matching a trigger event to a CPU, generating a corresponding breakpoint, using an internal COUNTER for triggering a corresponding count or using an internal CRC module for triggering a corresponding CRC check.
Finally, the MUX6 outputs the matched match bus output to be monitored by the system according to the monitoring selection control signal (for example, the detection target can be configured by CPU program counter, CPU instruction operation code, read/write address of the internal data address bus of the chip, and read/write data of the internal data address bus of the chip). The MUX6 is a matching signal of the monitored target, and can be used for outputting to the processor, stopping the processor or providing an interrupt to the processor, or outputting to the multipurpose count analysis module, further processing, or entering the CRC module (i.e. the cyclic redundancy check module) as an event trigger signal of the module for triggering CRC calculation. It can be understood that, because of different monitoring timings, a part of the monitoring signals need to be subjected to timing adjustment, and a part of the signals cannot be subjected to timing adjustment by any trigger, so that according to the selection of the monitoring target, the monitoring comparison module outputs a corresponding matching signal.
It should be noted that each enhanced new bus match unit has a corresponding matched control signal to generate a different configuration, outputting independent matched outputs, which may be configured as interrupt, processor stall signal, system event counter unit control signal, cyclic redundancy check unit enable signal. Flexible configuration for use in a system or debug application.
The enhanced bus comparator unit outputs a processing module (not shown in the figure), and for the multi-channel enhanced bus comparator unit outputs, a processing module is also arranged in the device, and the outputs can be processed by AND operation and OR operation through user configuration, and the outputs after logic operation can also be used as interrupt outputs, control signals of the system event counter unit and enabling signals of the cyclic redundancy check unit.
In some embodiments of the present application, the system event counter unit 130 is configured to obtain a target output from the user register configuration signal and the hardware input signal, wherein the target output includes: the maximum count records a value, a count value match output, a count value, or a count value overflow event output.
Some embodiments of the present application provide a core functionality of a system event counter unit.
In some embodiments of the present application, the user register configuration signal includes: an enable signal, a reset signal, a mode control signal, a reference signal, an input processing configuration signal, and a counter write signal. In some embodiments of the present application, the system event counter unit includes at least one counter, wherein each of the at least one counter includes the following modes of operation: a continuous mode, an event mode, and a start stop mode. That is, some embodiments of the present application implement a system event counting function through multiple counters.
The structure and function of the system event counter is described in detail below in conjunction with fig. 4.
In some embodiments of the present application, a system event counter unit provides better system profiling, analysis, and debugging functions, the unit containing counters, the debugging and analysis processes may be enhanced in various types of system scenarios, such as: parsing the code segment Profilingcode segments; counting a duration between a specified memory read and write; counting system events (e.g., interrupts); calculating a duration between system events; a system timer; measuring the number of wait states in the code segment; measuring a maximum amount of time spent between a pair of events, measured in a plurality of iterations; linking counters links events or creates larger counters.
It should be noted that, in other embodiments of the present application, the system event counter unit further has the following functions:
first, the functions of the counter capable of counting specifically include:
any matching events generated by the enhanced bus comparator unit are counted. The enhanced bus comparator unit generates events that can be used to start and stop counting. System event control, including interrupts, timer interrupts, and other events of the system. These system events can be used to start and stop counting. If the count reaches the reference value, an interrupt or viewpoint is generated.
Second, if the count reaches the reference value, an interrupt or viewpoint is generated.
Third, a plurality of counting modes.
For example, the architecture of the system event counter unit according to some embodiments of the present application is shown in fig. 5, in which the input of the system event counter unit is divided into two major parts:
user register configuration signal:
unit enable signal: for starting the system event counter unit.
Cell reset signal: for resetting the system event counter unit.
Mode control signal: for controlling the behaviour of the counter in the system event counter unit.
Specific counting mode of the counter.
The behavior of the counter when a match or stop event occurs when the counter is in a different mode.
When the counter is in different modes, the counter is responsive to counting trigger signals, such as edge response and level response.
Reference to the REF signal: a counter unit for a system event generates a match signal, the match being established when the count value of the counter equals the REF value.
Input processing configuration signal: for configuring the tuning control of the hardware inputs. Including but not limited to synchronization, reversing, etc. adjustment operations.
Cnt_wr counter write signal: the use of REG_WR_DATA allows software to directly configure the value of the counter in the system event counter unit.
Cnt_max_wr counter write signal: the software can directly configure the counter maximum count record value by being used together with REG_WR_DATA.
Second, hardware input signal:
cnt_input_sig: used in event mode for counting as a counter in an event trigger unit.
Cnt_reset_sig: in each mode is used to reset the counter in the cell.
Cnt_start_sig: used in a 'start-stop' mode for starting a counter in a cell for successive counting.
Cnt_stop_sig: used in a 'start-stop' mode for stopping the counting of the counter in the cell.
The outputs of the system event counter unit are:
a system event counter unit counts the record value at maximum.
And secondly, counting values of a system event counter unit counter.
And thirdly, matching and outputting the counter value of the system event counter unit.
Fourth, the system event counter unit counts the overflow event output.
It should be noted that, in some embodiments of the present application, the counter in the system event counter unit includes the following operation modes:
continuous mode: the counter counts the processor cycles as long as the event is active.
Event mode: when cnt_input_sig is active, the counter will count.
Start stop mode: in this mode, two events are allowed to act as start and stop indicators for the counter. The counter will only start counting when a defined start event occurs. The counter will then continue counting until a stop event occurs. After the first start event occurs, more start events will be ignored until a stop event occurs. He has two sub-modes
Maximum mode: this mode allows the user to detect the maximum counts that occur during various count iterations in the start stop mode. For example, the user may set a counter in a start stop count mode to count the duration of the key code cycle. Each time a stop event occurs and the counter stops, the counter value is checked against the current max_count in the register. If the new value is greater, the maximum count register is updated. The counter will always be reset to zero at the stop event and ready to start counting at the next start event. Thus, max_count will contain the maximum number of cycles that occur between start and stop conditions in multiple iterations.
Cumulative count mode: the system event counter unit may be used to generate a cumulative count of a plurality of start and stop events. In this mode, unlike the maximum mode, the counter is not reset by a stop event. Conversely, when a start event occurs, it stops counting and resumes counting. In the cumulative COUNT mode, max_count is inactive.
The cyclic redundancy check module is exemplarily described below.
In some embodiments of the present application, the cyclic redundancy check module is configured to check a target interface, wherein the target interface includes a processor interface, a program counter interface, an address read-write bus interface, a data read-write bus interface, or an instruction register value security attribute check interface.
In some embodiments of the present application, the cyclic redundancy check module includes: a second timing adjustment module (corresponding to the timing adjustment module of fig. 3) configured to obtain a target supervisory bus signal and a count valid signal according to the input read-write valid signal and the target supervisory bus; a multiplexer (corresponding to MUX1 of FIG. 3) configured to obtain CRC valid signals from the system events (e.g., 8 CRC units each corresponding to a different calculation target, each having been time-sequentially adjusted to give CRC calculation enable and data signals to each CRC unit calculation unit, and a multiplexer for each CRC unit to select other events as the calculation enable signals of the CRC units), the count valid signals and the CRC control signals; a calculation unit (corresponding to the CRC calculation unit of fig. 5) configured to obtain a target calculation result from the CRC control signal, the count valid signal, and the target supervisory bus signal.
Some embodiments of the present application provide an architecture for a cyclic redundancy check unit.
The architecture of the cyclic redundancy check unit of some embodiments of the present application is exemplarily described below in conjunction with fig. 5.
In some embodiments of the present application, a Cyclic Redundancy Check (CRC) unit monitors the processor bus and calculates the CRC when executing the self-test code. This functionality facilitates a simpler, non-invasive and interruptible self-checking mechanism through a Software Test Library (STL). Each CRC unit is used to monitor a different processor interface. For example, CRC unit 1 is used to monitor a program counter, while CRC unit 2 is used to monitor a data read address bus. Table 1 shows the processor interface monitored by each CRC unit.
Table 1 processor interface monitored by each CRC unit
| CRC unit | Processor interface |
| CRC1 | Program counter |
| CRC2 | Address read bus |
| CRC3 | Address write bus |
| CRC4 | Data read bus |
| CRC5 | Data write bus |
| CRC6 | Instruction register value (non-secure area) |
| CRC7 | Instruction register value (safe zone 1) |
| CRC8 | Instruction register value (safe zone 2) |
The main purpose of the CRC unit is to ensure that the functionality remains intact when the processor executes the same software test library in multiple iterations. This is achieved by comparing the calculated CRC value after each iteration with a pre-calculated standard value.
CRC7 and CRC8 in the above table are used to calculate the instruction register values for secure enclave 1 and secure enclave 2 instruction execution. The calculated CRC value for a given secure region is only applicable to accesses originating from that region.
The architecture of the Cyclic Redundancy Check (CRC) unit is shown in fig. 5, the interface signals are as follows:
monitoring bus signals: according to Table 1, different CRC units correspond to different supervisory buses
Corresponding to the monitoring read-write effective signal: only when valid will CRC calculation be enabled.
System event input: including external system events, enhanced new comparison unit match event logic processing output and system event count unit match events, which can be used to enable CRC unit computation by configuring a CRC computation enable select signal
A register configured CRC control signal. They include:
CRC calculation enable strobe: for selecting the valid signal that enables CRC calculation.
CRC seed signal: for configuring the CRC calculation initial value.
CRC function Enable signal: a function enable signal.
CRC initialization signal: for initially dividing the CRC calculation unit.
In some embodiments of the present application, each CRC unit has its own monitor signal that monitors for computation of the corresponding event, the monitored signal being time-aligned so that CRC computation can be enabled at the correct event. By default, all valid events on a given interface enable the CRC unit to calculate. However, by configuring the CRC calculation enable strobe, it may be used to strobe CRC calculations when a valid event occurs. For example: the enhanced bus compare unit has the ability to monitor the program counter, data write and data read. The CRC unit may use an enhanced bus compare unit to determine when the check value should be calculated. For example, if the check value needs to be calculated only when the processor performs a particular function, the user may set the enhanced bus compare unit to monitor the program counter and generate a CRC qualifier when that function is performed. This allows the CRC unit to calculate the check value only when needed.
It will be appreciated that some embodiments of the present application provide for more flexibility in application by allowing the system to monitor more system events through a dedicated enhanced comparator unit, system event counting unit and cyclic redundancy check unit. The device provided by the application can be used by a debugger and also can be used by application software. For many real-time systems, it is not always possible to connect a debugger and perform intrusive debugging. In these cases, the user code can set up and control the device to debug and evaluate the system without disturbing the interrupt application.
It should be noted that, the monitored bus may vary depending on the architecture of the system because of the different configuration of the processor model and the internal bus of the chip. The system event counter can have different mode combinations, can modify, delete and add different functions, and can also change the priority. The CRC calculation unit changes the structure according to the difference of the bit width of the monitoring bus, and is related to the architecture of the system. These embodiments are all encompassed by the embodiments of the present application.
As shown in fig. 2, some embodiments of the present application provide a chip that includes a processor and a means for monitoring diagnostics as described in the above embodiments.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other manners as well. The apparatus embodiments described above are merely illustrative, for example, flow diagrams and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, the functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. An apparatus for monitoring diagnostics, the apparatus comprising:
an enhanced bus comparator unit configured to monitor a target bus belonging to a program counter bus, an address write bus, an address read bus, a data write bus, or a data read bus, according to configuration information, and to generate an output event;
the system event counter unit is configured to analyze the monitored system under the control of the output event to obtain an analysis result;
a cyclic redundancy check module configured to perform a CRC check on the monitored interface upon triggering of the output event when executing the self-test code;
wherein the enhanced bus comparator unit comprises:
a first data selector configured to select at least one of the target buses from among a plurality of buses according to a monitoring target selection control signal;
the time sequence adjusting module is configured to adjust the time sequence of the monitoring signal according to the target bus to obtain the target time of each item of target bus;
the second data selector is configured to mask each item target bus according to the mask control signal and screen out target monitoring bus bits corresponding to each item target bus;
A third data selector configured to generate a signal to be compared and a comparison enable signal according to the monitoring target selection control signal;
a fourth data selector configured to mask the input monitoring reference comparison value to obtain a first monitoring target bus bit;
a fifth data selector configured to mask the output of the program counter to obtain a second monitor target bus bit;
the first matching comparison module is configured to obtain a first output signal according to the matching mode control signal, the first monitoring target bus bit and the second monitoring target bus bit;
a second match comparing module configured to obtain a second output signal according to the match mode control signal and the output signal of the third data selector;
a sixth data selector configured to obtain the output signal from the monitor target selection control signal, the first output signal, and the second output signal.
2. The apparatus of claim 1, wherein the enhanced bus comparator unit further comprises:
and the monitoring target configuration register is configured to receive the configuration information to obtain the monitoring target selection control signal.
3. The apparatus of claim 1, wherein the enhanced bus comparator unit further comprises:
and the matching model configuration register is configured to receive the configuration information to obtain the matching mode control signal.
4. The apparatus of claim 1, wherein the enhanced bus comparator unit further comprises:
a mask configuration register configured to receive the configuration information to obtain the mask control signal.
5. The apparatus of claim 1, wherein the enhanced bus comparator unit further comprises:
and a reference comparison value configuration register configured to obtain the monitoring reference comparison value according to the configuration information.
6. The apparatus of any of claims 1-5, wherein the system event counter unit is configured to obtain a target output from a user register configuration signal and a hardware input signal, wherein the target output comprises: the maximum count records a value, a count value match output, a count value, or a count value overflow event output.
7. The apparatus of claim 6, wherein the user register configuration signal comprises: an enable signal, a reset signal, a mode control signal, a reference signal, an input processing configuration signal, and a counter write signal.
8. The apparatus of claim 7, wherein the system event counter unit comprises at least one counter, wherein each of the at least one counter comprises the following modes of operation: a continuous mode, an event mode, and a start stop mode.
9. The apparatus of claim 7, wherein the cyclic redundancy check module comprises:
the second time sequence adjusting module is configured to obtain a target monitoring bus signal and a counting effective signal according to the input reading and writing effective signal and at least one bus;
a multiplexer configured to obtain a CRC valid signal from the system event, the count valid signal, and a CRC control signal;
and a calculating unit configured to obtain a target calculation result according to the CRC control signal, the count valid signal and the target monitoring bus signal.
10. A chip comprising a processor and the apparatus of any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210668784.XA CN115391132B (en) | 2022-06-14 | 2022-06-14 | Monitoring and diagnosing device and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210668784.XA CN115391132B (en) | 2022-06-14 | 2022-06-14 | Monitoring and diagnosing device and chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115391132A CN115391132A (en) | 2022-11-25 |
| CN115391132B true CN115391132B (en) | 2024-03-29 |
Family
ID=84117303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210668784.XA Active CN115391132B (en) | 2022-06-14 | 2022-06-14 | Monitoring and diagnosing device and chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115391132B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117009185A (en) * | 2023-09-14 | 2023-11-07 | 飞腾信息技术有限公司 | Bus monitoring method, device, system on chip and equipment |
| CN117193097B (en) * | 2023-09-26 | 2024-07-16 | 北京中科昊芯科技有限公司 | Device and method for processing on-chip multifunctional signal |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1378679A (en) * | 1999-10-13 | 2002-11-06 | 全斯美达有限公司 | Programmable event computer system |
| CN101764794A (en) * | 2008-12-23 | 2010-06-30 | 中国科学院空间科学与应用研究中心 | Programmable IEEE1394 bus monitoring system and monitoring method thereof |
| CN101989242A (en) * | 2010-11-12 | 2011-03-23 | 深圳国微技术有限公司 | Bus monitor for improving safety of SOC (System on a Chip) as well as realizing method thereof |
| CN107607853A (en) * | 2017-08-18 | 2018-01-19 | 北京集创北方科技股份有限公司 | Adjustment method, device, storage medium and the processor of chip |
| CN111078492A (en) * | 2019-10-25 | 2020-04-28 | 芯创智（北京）微电子有限公司 | System and method for monitoring state of SoC internal bus |
| WO2022093599A1 (en) * | 2020-10-29 | 2022-05-05 | Micron Technology, Inc. | Techniques for detecting a state of a bus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT201800005506A1 (en) * | 2018-05-18 | 2019-11-18 | PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT AND PROCEDURE | |
| JP2020140380A (en) * | 2019-02-27 | 2020-09-03 | ローム株式会社 | Semiconductor device and debugging system |
-
2022
- 2022-06-14 CN CN202210668784.XA patent/CN115391132B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1378679A (en) * | 1999-10-13 | 2002-11-06 | 全斯美达有限公司 | Programmable event computer system |
| CN101764794A (en) * | 2008-12-23 | 2010-06-30 | 中国科学院空间科学与应用研究中心 | Programmable IEEE1394 bus monitoring system and monitoring method thereof |
| CN101989242A (en) * | 2010-11-12 | 2011-03-23 | 深圳国微技术有限公司 | Bus monitor for improving safety of SOC (System on a Chip) as well as realizing method thereof |
| CN107607853A (en) * | 2017-08-18 | 2018-01-19 | 北京集创北方科技股份有限公司 | Adjustment method, device, storage medium and the processor of chip |
| CN111078492A (en) * | 2019-10-25 | 2020-04-28 | 芯创智（北京）微电子有限公司 | System and method for monitoring state of SoC internal bus |
| WO2022093599A1 (en) * | 2020-10-29 | 2022-05-05 | Micron Technology, Inc. | Techniques for detecting a state of a bus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115391132A (en) | 2022-11-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN115391132B (en) | Monitoring and diagnosing device and chip | |
| US4845615A (en) | Software performance analyzer | |
| JP5328531B2 (en) | Monitoring of data processing equipment and aggregation of monitoring data | |
| US5103394A (en) | Software performance analyzer | |
| CN109328340B (en) | Memory fault detection method and device and server | |
| Rashid et al. | Characterizing the impact of intermittent hardware faults on programs | |
| US6557119B1 (en) | Microcomputer debug architecture and method | |
| EP1272934B1 (en) | Non-intrusive application code profiling method and apparatus | |
| JPS6010358A (en) | Internal system measuring/monitoring apparatus | |
| US6487683B1 (en) | Microcomputer debug architecture and method | |
| US6463553B1 (en) | Microcomputer debug architecture and method | |
| DeOrio et al. | Post-silicon bug diagnosis with inconsistent executions | |
| Hari et al. | SASSIFI: Evaluating resilience of GPU applications | |
| US8185772B2 (en) | Determining execution times of commands | |
| US6502210B1 (en) | Microcomputer debug architecture and method | |
| US6331957B1 (en) | Integrated breakpoint detector and associated multi-level breakpoint techniques | |
| Leng et al. | Hardware performance counters for system reliability monitoring | |
| Rashid et al. | Towards understanding the effects of intermittent hardware faults on programs | |
| US20070226471A1 (en) | Data processing apparatus | |
| JP2023504658A (en) | Cause identification of observed anomalies in integrated circuit chips | |
| CN105718375B (en) | The restorability measure of embedded system | |
| KR20220113423A (en) | Debug State Machine Trigger Extended Performance Monitor Counters | |
| Frtunikj et al. | Qualitative evaluation of fault hypotheses with non-intrusive fault injection | |
| Fryer | The memory bus monitor: a new device for developing real-time systems | |
| CN113094217B (en) | Method for carrying out fault analysis and diagnosis on self-checking result in electronic system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |