CN107564903A - 具有电压限制和电容增强的电路 - Google Patents

具有电压限制和电容增强的电路 Download PDF

Info

Publication number
CN107564903A
CN107564903A CN201710522574.9A CN201710522574A CN107564903A CN 107564903 A CN107564903 A CN 107564903A CN 201710522574 A CN201710522574 A CN 201710522574A CN 107564903 A CN107564903 A CN 107564903A
Authority
CN
China
Prior art keywords
transistor
source electrode
voltage
doped region
drain electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710522574.9A
Other languages
English (en)
Other versions
CN107564903B (zh
Inventor
菲利浦·拉特
简·雄斯基
巴里·怀恩
赖艳
史蒂文·托马斯·皮克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yasuyo Co Ltd
Original Assignee
Yasuyo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yasuyo Co Ltd filed Critical Yasuyo Co Ltd
Publication of CN107564903A publication Critical patent/CN107564903A/zh
Application granted granted Critical
Publication of CN107564903B publication Critical patent/CN107564903B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0626—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H01L27/0733—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H01L29/7832—Field effect transistors with field effect produced by an insulated gate with multiple gate structure the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本公开的方面涉及可利用增强电容和减轻的雪崩击穿进行操作的电路。如可以根据一个或多个实施例所实现的那样，设备和/或方法涉及共源共栅电路的各个晶体管，其中一个晶体管通过向另一个晶体管的栅极施加电压来控制所述另一个晶体管处于关断状态。多个掺杂区域被沟槽分开，其中，导电沟槽配置和布置有掺杂区域，从而在第二晶体管的源极和漏极之间提供电容，并且限制第二晶体管的源极和漏极之一处的电压，由此减轻第二晶体管的雪崩击穿。

Description

具有电压限制和电容增强的电路
技术领域
本发明涉及一种电路，更具体地，涉及一种提供电压钳制和电容的电路，其例如可以被实现用于控制高电压器件。
背景技术
许多器件采用开关式电路，这可以以各种方式实现。例如，可以按期望将高电压开关与相关的电路一起使用。在一些应用中，常开型器件(晶体管)通过耦接了导致常关断的节点操作(net operation)的附加器件而在高电压下使用。一种这样的方法涉及使用其中低电压FET(场效应晶体管)耦接到高电压器件的共源共栅布置来提供控制栅极电压。
虽然这样的器件是有用的，但某些状况会导致过电压，这会对高电压器件和低电压FET中的任一个或两者造成损害。例如，如果高电压器件中的漏电流高于低电压器件的漏电流，或者低电压FET的切断比高电压器件更快，则可能会出现操作问题和可靠性问题。
对于各种应用而言，这些和其它事件已经对这种器件的制造和实施提出了挑战。
发明内容
各种示例实施例涉及多种问题，比如上面指出的那些问题和/或根据与晶体管电路(比如涉及高电压晶体管的电路)的操作有关的以下公开内容会变得明显的其他问题。在各种实施方式中，使用具有增强电容和减轻雪崩击穿的低电压晶体管来控制常开型晶体管。
在某些示例实施例中，本公开的方面涉及对提供增强电容和雪崩击穿控制的半导体结构的使用。这样的方面可以利用可在与晶体管本身的形成共享的工艺步骤中进一步形成的由沟槽分隔的掺杂区域来实现。
根据特定实施例，一种设备包括具有第一晶体管和第二晶体管的共源共栅电路，第一晶体管和第二晶体管各自具有栅极、源极、沟道和漏极，其中第二晶体管的漏极电连接到第一晶体管的源极。第二晶体管连接成并且可操作为通过对第一晶体管的栅极施加电压来控制第一晶体管处于关断状态。所述设备还包括多个导电沟槽和一个或多个掺杂区域，所述一个或多个掺杂区域位于导电沟槽中的相邻导电沟槽之间并且提供p-n结。导电沟槽配置并布置有掺杂区域，以提供第二晶体管的源极和漏极之间的电容，并且通过限制第二晶体管的源极和漏极之一处的电压(例如，通过对电压进行钳制)来减轻第二晶体管的雪崩击穿。
另一个实施例涉及一种方法，所述方法可以利用如上所述的电路来实现。提供第一晶体管和第二晶体管用于共源共栅电路，第一晶体管和第二晶体管各自具有栅极、源极、沟道和漏极，其中第二晶体管的漏极电连接到第一晶体管的源极。多个导电沟槽连同各相邻沟槽之间的一个或多个掺杂区域连接到第二晶体管的源极和漏极。第二晶体管用于通过对第一晶体管的栅极施加电压来控制第一晶体管处于关断状态，并且导电沟槽和掺杂区域用于在第二晶体管的源极和漏极之间提供电容并减轻第二晶体管的雪崩击穿。在这种情况下，可以通过限制或钳制第二晶体管的源极和漏极之一处的电压来减轻雪崩击穿。
在其它具体示例实施例中，一种设备包括共源共栅电路、电容器电路和钳制二极管电路。共源共栅电路包括高电压GaN晶体管，所述高电压GaN晶体管具有栅极、源极、漏极和连接该高电压GaN晶体管的源极和漏极的沟道。共源共栅电路还包括低电压FET，所述低电压FET具有栅极、连接到高电压GaN晶体管的栅极的源极、连接到高电压GaN晶体管的源极的漏极、以及连接该低电压FET的源极和漏极的沟道。电容器和钳制二极管电路连接到低电压FET晶体管的源极和漏极。在某些实施例中，低电压FET通过将其源极处的电压施加到高电压GaN晶体管的栅极来控制高电压GaN晶体管处于关断状态，同时电容器和钳制二极管在低电压FET的源极和漏极之间提供电容，并且通过钳制源极和漏极两端的电压来减轻低电压FET的雪崩击穿。
上述讨论/概述不旨在描述本公开的每个实施例或每个实施方式。下面的附图和详细描述也例示了各种实施例。
附图说明
考虑以下结合附图的详细描述，可以更全面地理解各种示例实施例，在附图中：
图1示出了根据本公开的设备；
图2示出了根据本公开的设备的截面图；
图3示出了根据本公开的设备的截面图；
图4示出了根据本公开的设备的顶视图；以及
图5示出了表征可以根据一个或多个实施例实现的示例沟槽间隔和相关击穿电压的曲线图。
尽管本文中讨论的各种实施例可被修改为改型和替代形式，但是本发明的各方面在附图中通过示例方式示出，并且将被详细描述。然而，应当理解，不旨在将本公开限制于所描述的特定实施例。相反，旨在涵盖落入包括权利要求中所限定的各方面的本公开的范围内的所有改型、等同物和替代方案。此外，在本申请全文中使用的术语“示例”仅仅是为了说明而不是限制。
具体实施方式
本公开的方面被认为是可应用于涉及过电压抑制或其它电压控制的各种不同类型的设备、系统和方法。在某些实施方式中，当在诸如级联电路的电路中的过电压抑制的情况下使用本公开的各方面时(可以在各种类型的电路和相关器件/系统中实现)，已经表明本公开的各方面是有益的。在一些实施例中，可利用低电压开关操作的电路为所述开关提供额外的漏源电容以及钳制功能。这样的电路可以与常开型开关或晶体管一起实现(例如，在这种常开型高电压开关的源极处，并且可操作为使该高电压开关关断)。常开型晶体管是在没有栅极电压的情况下处于导通(导电)状态的晶体管。通过使用示例性情况的非限制性示例的以下讨论可以理解各个方面，但本公开不限于此。
因此，在下面的描述中，阐述了各种细节以描述本文中呈现的示例。然而，对于本领域技术人员显而易见的是，可以在没有以下给出的所有具体细节的情况下实践一个或多个其它示例和/或这些示例的变型。在其它情况下，未详细描述众所周知的特征，以免使本文中的示例的描述变得模糊不清。为了便于说明，可以在不同的附图中使用相同的附图标记来指代相同元件或相同元件的附加实例。此外，尽管在某些情况下可以在各个附图中描述方面和特征，但是应当理解，来自一个附图或实施例的特征可以与另一个附图或实施例的特征组合，即使该组合未被明确地示出或未被明确描述为组合。例如，以低电压开关示出的附加电容/钳制功能可以与本文所示的其它电路一起使用。在与这种低电压开关一起实现附加电容/钳制功能的情况下，附加电容/钳制功能(和相关电路)可以与除如附图所示的高电压输入开关之外的电路和/或作为如附图所示的高电压输入开关的替代物的电路一起使用，比如，附加电容/钳制功能(和相关电路)可以与各种不同类型的电路的实施方式一起使用。
各种实施例涉及利用满足增强型Coss(输出电容或漏源电容)和电压钳制这两种功能的电路/间隔结构来提供增强型Coss(输出电容或漏源电容)和电压钳制功能。在各种情况下，对电路和电路中的材料(例如，绝缘材料)之间的间隔进行设置以微调钳制电压。这样的实施例可以利用耦接到被提供了增强型Coss的低电压晶体管的常开型晶体管来实现。例如，可以使用具有增强型Coss和电压钳制的低电压FET(例如，MOSFET)来实现GaN(氮化镓)常开型晶体管。这些方法可以被实现为例如钳制处于关断状态下的FET的漏极电压，这可以减轻或防止该FET的漏极处的过电压状况(和相关的雪崩)，否则，由于常开型晶体管相当快速地关断，可能导致该过电压状况(和相关的雪崩)。
某些实施例涉及这样一种结构，所述结构起到附加电容和钳制二极管作用，从而提供如上所述的增强Coss和电压钳制。结合这样的实施例，已经认识/发现，单个结构可以实现这些效果，并且进一步地，这样的结构可以在用于形成相邻晶体管的处理步骤期间得以实施。与各种实施例一致，可以使用与用于低电压器件中的边缘终端相同的工艺来在同一晶片上构造一系列深沟槽来提供增强型Coss。如上所述，沟槽连接到FET的源极，这提供了增强/附加的Coss。沟槽还与每个沟槽之间的p主体(p-body)注入物(例如，利用用于主结构的p型注入物来实施)一起使用，从而在一系列这些沟槽之间限定二极管。
在各种实施例中，将这种结构的击穿电压调整到期望值，以便提供期望的功能(例如，保护高电压器件(比如，由FET控制的GaN器件)的栅极和/或防止FET雪崩)。在一个实施例中，使用附加注入物(例如，p型或n型)来修改用作电压钳制的p-n二极管的击穿。在另一个实施例中，改变深沟槽之间的距离以设定击穿电压。在另一个实施例中，限定与深沟槽的接触来设置击穿电压，例如提供更少的触点和/或接触一系列沟槽中更少的沟槽。其它实施例采用上述两种或更多种方法的组合(例如，添加注入物并修改深沟槽距离)来调整击穿电压。设置击穿电压的其它方法可以包括以下方法中的一个或多个(其也可以与上述一种或多种方法结合实施)：设置/改变沟槽深度(例如，在沟槽比相邻漂移区更深的情况下电容得到修改)；改变漂移区厚度；改变一个或多个区域中的掺杂剂浓度；以及改变沟槽内的绝缘体厚度。
例如，可以利用可使用RESURF(降低的表面电场)原理来实现高击穿电压的低电压MOSFET来实现本文中的各种方法。例如，可以(相对于原始设计)增加深沟槽之间的距离以减少结构中RESURF的量(例如，如图4所示)。因此，各个方面涉及采用(例如，具有低电压器件的)共源共栅配置中的电压钳制的电路和/或相关系统/设备，该共源共栅配置利用了两个隔离沟槽之间的RESURF效应。可以实施这种方法来保护低电压MOSFET和所连接的开关(例如，GaN晶体管)的栅极免受由于重复雪崩而造成的损害。电压钳制还增加了可用于在电压瞬变期间保护器件的附加输出电容。
在一些实施例中，在共源共栅布置中如上所述的低电压MOSFET置于高电压器件的源极。高电压器件可以例如包括GaN HEMT(高电子迁移率晶体管)或SiC JFET(碳化硅结栅场效应晶体管)。当低电压MOSFET关断时，在常开型高电压器件中产生导致(或维持)该常开型高电压器件关断的负栅极电压(例如，低电压MOSFET器件栅极与源极之间的差(Vg-Vs)为负值)。
低电压MOSFET的漏源电压(VDS)可以通过常开型高电压器件的阈值电压和这两个器件的电容来表征，如以下公式所述：
其中,Vx是该MOSFET的漏源电压，CDS(GaN)是GaN HEMT的漏源电容；Vd是GaN HEMT的最大额定电压；CGS(GAN)是GaN HEMT的栅源电压；Vth(GAN)是GaN HEMT的阈值电压。可以看出，Vx取决于：所连接器件的最大额定电压(Vd)；常开型(例如，GaN)器件的阈值电压Vth(GAN)(注意，由于这是负数，所以上述公式中的最后一项将为正值)；以及这两个器件的电容CDS(GaN)、CGS(GAN)和COSS(MOS)。
各种实施例涉及使用电压钳制来确保Vx是低的或尽可能低的。这有助于确保不超过常开型器件的最大栅极电压，并且可以确保低电压MOSFET不会雪崩。对于后者，这可以有助于长期的可靠性。此外，这有助于确保低电压MOSFET不会雪崩，以便实现真正的ZVS(零电压开关)并提高软开关应用中的效率。这也可以有助于优化Coss相关的反向恢复电荷并使硬开关应用中的损耗最小化。Coss可以通过增加电容而进一步优化，这也会降低Vx。
根据特定实施例，一种设备包括具有第一晶体管和第二晶体管的共源共栅电路，第一晶体管和第二晶体管各自具有栅极、源极、沟道和漏极。第二晶体管的漏极和源极分别连接到第一晶体管的源极和栅极。因此，可以使用第二晶体管的导通/关断状态来控制第一晶体管的导通/关断状态。此外，第二晶体管可以在没有控制信号的情况下将第一晶体管维持在关断状态，以使电路作为常关型电路工作。多个导电沟槽和每对相邻沟槽之间的至少一个掺杂区域(每个掺杂区域提供p-n结)在第二晶体管的源极和漏极之间提供电容，并且通过限制第二晶体管的源极和漏极之一处的电压电平来减轻第二晶体管的雪崩击穿。例如，导电沟槽可以通过从源极延伸到沟槽的触点而耦接至第二晶体管的源极。例如，掺杂区域可以形成p-n二极管的一部分或全部(例如，形成二极管的p区域和n区域，或者形成可与不同的这种p区域或n区域相接触的这些区域中的一个)。在一些示例中，p-n结可以形成在掺杂区域与第一晶体管的源极和漏极的延伸区域的交叉点处。在一些实施方式中，掺杂区域和沟槽形成二极管和电容器，所述二极管和电容器与沟道并联地耦接至第二晶体管的源极和漏极。
就这方面而言,有利于各种共源共栅应用。例如，在第一晶体管是常开型晶体管的情况下，第二晶体管通过将来自第二晶体管的源极的电压耦合到常开型晶体管的栅极来控制第一晶体管处于关断状态。第二晶体管两端的电压降在常开型晶体管的栅极和源极之间设置负电压差，从而保持所述关断状态。
可以实现各种不同类型的半导体结构以相对于晶体管结构形成掺杂区域和沟槽。在一些实施例中，掺杂区域和沟槽可以与第二晶体管的沟道并联地实现，其中沟槽彼此横向相邻地布置，并且掺杂区域横向地位于沟槽之间。在各种实施例中，第二晶体管的源极包括在沟槽和掺杂区域之上延伸的掺杂层，第二晶体管的漏极包括在掺杂区域之下延伸的第二掺杂层，沟槽在掺杂区域之间延伸并进入第二掺杂层。在这种情况下，为了便于精益加工和简单化，可以作为用于形成晶体管的共同注入工艺的一部分来形成掺杂区域。
在一些实施例中，如上所述，第一晶体管是高电压晶体管，第二晶体管是低电压晶体管。在这种上下文中的高电压晶体管涉及具有比低电压晶体管更高的阈值电压的晶体管，例如诸如GaN HEMT或SiC JFET的功率MOSFET。该方法有助于在实现高电压晶体管的优点的同时利用低电压晶体管进行控制。第二晶体管通过设置第一晶体管的负栅源电压差来将第一晶体管从导通状态切换到关断状态，而掺杂区域相对于钳制电压阈值电平限制第二晶体管的漏极处的电压电平。例如在开关的时机可能导致高电压被施加至第二晶体管的情况下，经由附加电容和电压钳制，这种方法可以有助于低电压晶体管的切换和保护。例如，当第二晶体管从导通状态切换到关断状态时，沟槽和掺杂区域可以限制第二晶体管的源极和漏极两端的电压降。这样，第二晶体管可以通过将提供常开型晶体管的栅极与源极之间的负电压差的电压耦合到第一晶体管的栅极来使第一晶体管关断，同时保护免受不期望的过电压状况。
另一个实施例涉及一种可以用如上所述的电路来实现的方法。提供各自具有栅极、源极、沟道和漏极第一晶体管和第二晶体管，并且提供与所述第二晶体管的源极和漏极连接的多个导电沟槽，各导电沟槽由一个或多个掺杂区域间隔开。第二晶体管用于通过对第一晶体管的栅极施加电压来将第一晶体管控制在关断状态，并且沟槽和掺杂区域用于在第二晶体管的源极和漏极之间提供电容，以及减轻第二晶体管的雪崩击穿。在这种情况下，可以通过限制(例如，钳制)第二晶体管的源极和漏极之一处的电压来减轻雪崩击穿。
可以调整掺杂区域和沟槽以设置第二晶体管的操作特性。例如，掺杂区域可以以选定的掺杂剂及剂量进行掺杂，从而设置漏极和沟道之间的击穿电压。沟槽可以以一定的距离进行设置，该距离调整/设置漏极和沟道之间的击穿电压。掺杂和沟道距离的组合可以一起使用，从而调整或设置第二晶体管的击穿电压。
现在转到附图，图1示出了具有相应开关电路的设备100，所述设备100包括第一(开关)电路110、第二(开关)电路120和第三电路130，所述第三电路130操作为对如图所示的Vx进行钳制并且在第二电路120两端提供额外的电容。在一些实施方式中，第一电路110包括GaN晶体管，或者第一电路110是GaN晶体管，并且第二开关120包括NMOS晶体管，或者第二开关120是NMOS晶体管。如通过其他示例所示出的那样，第三电路130可以包括电容电路131和二极管电路132。
设备100可以以各种方式操作。在一些实施例中，第二电路120是耦接到第一电路110(作为GaN晶体管)的源极的NMOS晶体管，并且第二电路120操作为提供对第一电路110的耦接在节点121的栅极的控制。第二电路120响应于控制信号Vg，并且当Vg未被有源地驱动时，共源共栅配置确保第一电路110关断。当NMOS晶体管切换为关断状态，并且在此期间GaN晶体管切换为关断时，电容电路131和二极管132操作为分别提高NMOS晶体管的漏极122和源极123之间的电容和对Vx进行钳制。在一些实施例中，电容电路131和二极管电路132被实施在两个隔离沟槽之间，以保护NMOS晶体管免受由于重复雪崩而引起的损害，并且电压钳制效应进一步增加了在电压瞬变期间起保护作用的输出电容。沟槽产生额外的Coss并且二极管产生钳制，从而防止MOSFET雪崩。电容电路131和二极管电路132可以与MOSFET的有源区域并联地连接至MOSFET的漏极和源极。
因此，在第一电路110被实施为GaN晶体管并且第二电路120被实施为NMOS晶体管的情况下，当GaN器件关断时，GaN晶体管的阈值电压是负值，并且GaN晶体管的栅极和源极之间的差(Vg-Vs)是负值。GaN器件的连接到MOSFET 120的漏极的源极的电压(VsGaN)是正值，并且GaN器件的连接到MOSFET 120的源极的栅极的电压(VgGaN)是比MOSFET 120的漏极电压低的某个值(例如，0)。因此，GaN器件的栅极和源极之间的电压差(VgGaN–VsGaN)是负值。
图1中示出的各个电路组件可以以各种方式连接和实现。在一些实施例中，漏极122通过接合线连接至GaN晶体管110的源极，并且源极123通过另一根接合线连接至GaN晶体管110的栅极。类似地，可以使用夹片接合(clip bonding)来形成这些连接。在其它实施例中，利用公共衬底/芯片中的金属层连接将GaN晶体管110和NMOS晶体管120以及第三电路130一起实施在公共衬底/芯片中。
各实施例涉及其中电容电路131和二极管电路132是提供两种功能的单一结构的一部分的电路130。这样的电路可以耦接至各种其它类型的电路或器件，并相应地起作用。其它实施例涉及随电路120一起实现的电路130，其中电容电路131和二极管电路132为(晶体管)电路120提供增强电容和电压限制/钳制。然后，可以以各种不同类型的电路来实现电路120，利用电路130来进行电容控制和钳制控制。
图2示出了根据本公开的设备200的截面图。设备200包括掺杂衬底210、硅外延层(episilicon layer)212(例如，漂移区)、主体注入层(body implant layer)214、绝缘层216和导电层218。例如，掺杂衬底210和硅外延层212可以是n、n-或N+，主体注入层214为p或P+。包括沟槽220的深沟槽从主体注入层214的各部分之间延伸到掺杂衬底210中。对于各种应用，这些深沟槽例如通过停止在硅外延层212中而形成为较浅的深度。沟槽220内衬有绝缘材料221，并且进一步填充有导电材料222。触点(包括230)将导电层218耦接到沟槽和主体注入层214。对于某些实施例，还可以从主体注入层214延伸至掺杂衬底210地添加RESURF注入物。在各种实施例中，不使用RESURF注入物。利用耦接到MOSFET的漏极(或者作为MOSFET的漏极的一部分)的掺杂衬底210、以及耦接到MOSFET的源极(或者作为MOSFET的源极的一部分)的导电层218、沟槽和各主体注入层部分(充当二极管)，漏极处电压被钳制，并且漏源电容得以提高。
在一些实施例中，导电层218(例如，源极)和导电沟槽220之间的触点230是不连续或省略的。例如，多个触点在器件上间隔开，并且被导电沟槽未直接连接到导电层218的部分隔开。就此，R-C电路得以形成，并且可以被实施为减轻导电层218和掺杂衬底210之间(例如，在相邻FET的源极和漏极之间)的电压振荡。
在各实施例中，沟槽阵列用于提供电容。这样的阵列可以例如利用如图2中所示的沟槽来实现。某些应用涉及这样一种阵列：p-n结形成在如图2所示的相邻的沟槽之间(例如，在214处的p主体区域和下面的区域212/210之间)或者以其它方式形成，并且相邻沟槽之间的某些区域不包括这样的p-n结。这种方法对于产生增加的电容和/或减少的结漏(junction leakage)来说可能是有用的。
图3示出了根据本公开的设备300的截面图。可以使用图2的设备来实现图3的各个方面，在这种情况下，某些部分被类似地标出。设备300包括掺杂衬底310、硅外延层312、主体注入层314、绝缘层316和导电层318。类似于图2，掺杂衬底310和硅外延层312可以是掺杂的N+，主体注入层314是P+。包括沟槽320的浅有源沟槽从主体注入层314的各部分之间延伸到硅外延层312中。触点(包括330)可以可选地在p主体注入区域(例如，RESURF区域)上方实现，并且将导电层318耦接到主体注入层314。某些实施例不涉及RESURF结构，并且某些实施例涉及分裂栅极或阶梯状氧化物组件以提供高击穿电压。
在一个或多个实施例中，图2所示的设备200与图3所示的设备300并行实现，并且两者均连接在源极(导电层218/318)和漏极(掺杂衬底210/310)之间。在这种情况下，设备200和300中的每一个均可以耦接到共同的源区和漏区，其中源极(218/318)和漏极(210/310)被共享，并且各个设备200和300彼此并联。例如，可以利用晶体管结构的有源区来实现如图3所示的设备，并且可以在同一晶体管结构的边缘终端区域中实现图2所示的设备。
在本文的截面图中，示出了某些掺杂区域，并且用各自的掺杂剂类型表征这些掺杂区域。然而，应当理解，可以在实现期望的结构(例如，形成二极管的p-n结)的同时，使各区域(比如，漂移区域(例如，在212处))与不同极性相掺杂。因此，各实施例涉及这样的结构，所述结构可以利用与通过示例示出的掺杂不同的掺杂来实现。
图4示出了根据本公开的设备400的顶视图。可以根据图2的设备200实现具有边缘终端的设备400。该设备包括沟槽区域(包括沟槽410和412)以及位于沟槽410和412之间的主体注入区域420。触点(包括触点430)延伸到每个沟槽区域和主体注入区域中。对于某些应用，到下方二极管的触点是连续的。在其他应用中，触点区域被限制为在不存在触点的区域中提供电压钳制。
图5示出了表征可以根据一个或多个实施例实现的示例沟槽间隔和相关击穿电压的曲线图。垂直轴表示所得的击穿电压，横轴表示沟槽之间的间距。曲线510和520示出了相似掺杂分布的变化，曲线530和540示出了彼此相似但不同于曲线510和520的掺杂分布的变化。
本文中可能使用到的用于例示定向的术语(例如，上/下、左/右，顶/底和在…之上/在…之下)指的是如图所示的元件的相对位置。应当理解，术语可能仅是出于符号方便的目的而被使用，并且在实际使用中，所公开的结构可以被定向为不同于附图中所示的定向(例如，被表征为相对于彼此横向布置的结构可以是垂直堆叠的，这样做同样能获得类似的结果)。因此，不应当以限制性的方式来解释这些术语。
本领域技术人员将认识到，除非另有说明，否则本说明书(包括权利要求书)中所使用的各种术语均表示本领域的一般含义。作为示例，本说明书描述和/或示出了用于通过各种电路或电路来实现所要求保护的公开的方面。这些电路或电路系统可以被示出各种术语，或者可以使用各种术语来示出这些电路或电路系统，所述各种术语比如为块、模块、装置、系统、单元、控制器、钳制和/或其它电路类型描述(例如，图1的附图标记110、120和130可以描绘上下文中的块/模块)。这样的电路或电路系统被讨论为与其它元件一起使用，从而例示可以以形式或结构、步骤、功能、操作、活动等来实施某些实施例的方式。作为另一个示例，在说明书可以提及“第一[结构类型]”、“第二[结构类型]”等的情况下，可以使用诸如[“电路”，“电路系统”等等]的术语来代替所述[结构类型]，形容词“第一”和“第二”不用于意指结构的任何描述或用于提供任何实质意义；相反，这样的形容词仅用于英语语言的先行词，以将一个类似命名的结构与另一个类似命名的结构区分开来(例如，“被配置为钳制...的第一电路”被解释为“被配置为钳制...的电路”)。
基于上述讨论和说明，本领域技术人员将容易地认识到，可以对各种实施例进行各种修改和改变，而无需严格遵循本文所示出和描述的示例性实施例和应用。例如，如附图中所例示的方法可以涉及以各种顺序执行的步骤，在实施例的一个或多个方面得以保留的情况下，或者可以涉及更少或更多的步骤。所示的各个沟槽和各个层可以以不同的顺序形成或者以不同的布置形成，从而实现特定的效果。作为另一示例，不同类型的高电压器件可以与低电压开关和产生钳制和电容增强效果的相关的组件一起使用。这些改型并不偏离本公开的各方面(包括权利要求中所阐述的方面)的真实精神和范围。

Claims (20)

1.一种设备，包括：
共源共栅电路，其易受包括雪崩击穿的过电压状况影响，所述共源共栅电路包括
第一晶体管，其具有栅极、源极、沟道和漏极，以及
第二晶体管，其具有栅极、源极、沟道和电连接到所述第一晶体管的源极的漏极，所述第二晶体管被配置和布置成通过对所述第一晶体管的栅极施加电压来控制所述第一晶体管处于关断状态；
多个导电沟槽；以及
一组一个或多个掺杂区域，每个掺杂区域位于相应的相邻一对导电沟槽之间，并且配置为提供p-n结，其中，所述多个导电沟槽和一个或多个掺杂区域与所述共源共栅电路一起配置和布置，以在所述第二晶体管的源极和漏极之间提供电容，并且通过限制所述第二晶体管的源极或漏极处的电压电平来减轻所述第二晶体管的雪崩击穿。
2.根据权利要求1所述的设备，其中
所述掺杂区域和所述导电沟槽是与所述第二晶体管的沟道并联地连接到所述第二晶体管的源极和漏极的电路的一部分，所述导电沟槽彼此横向相邻地布置，所述掺杂区域横向地位于所述导电沟槽之间；
所述第二晶体管的源极包括在所述导电沟槽和所述掺杂区域的上方延伸的第一掺杂层；
所述第二晶体管的漏极包括在所述掺杂区域的下方延伸的第二掺杂层；并且
所述导电沟槽在所述掺杂区域之间延伸并进入所述第二掺杂层。
3.根据权利要求1所述的设备，其中：
所述第一晶体管是具有高击穿电压的高电压晶体管，以及
所述第二晶体管是具有低于所述高击穿电压的低击穿电压的低电压晶体管，所述第二晶体管的漏极耦接到所述第一晶体管的源极，所述第二晶体管配置和布置成：在所述掺杂区域相对于钳位电压阈值电平限制所述第二晶体管的漏极处的电压电平的同时，通过设置所述第一晶体管的负栅源电压差来将所述第一晶体管从导通状态切换到关断状态。
4.根据权利要求1所述的设备，其中，所述导电沟槽通过触点耦接到所述第二晶体管的源极，所述触点从所述第二晶体管的源极延伸到所述导电沟槽。
5.根据权利要求1所述的设备，其中：
所述第一晶体管是常开型晶体管，以及
所述第二晶体管配置和布置成：通过将来自所述第二晶体管的源极的电压耦合到所述常开型晶体管的栅极来在所述常开型晶体管的栅极和源极之间提供负电压差，控制所述第一晶体管处于关断状态。
6.根据权利要求1所述的设备，其中，每个掺杂区域是p-n二极管的一部分，所述p-n二极管包括所述掺杂区域以及所述第一晶体管的源极和漏极的延伸区域，每个p-n二极管具有由所述导电沟槽中的一个隔离开的部分。
7.根据权利要求1所述的设备，其中，所述导电沟槽和所述掺杂区域配置和布置成：在所述第二晶体管从导通状态切换为关断状态的同时、并且在所述第二晶体管通过将提供所述第一晶体管的栅极与源极之间的负电压差的电压耦合至所述第一晶体管的栅极来关断所述第一晶体管的同时，限制所述第二晶体管的源极和漏极两端的电压降。
8.根据权利要求1所述的设备，其中
所述第一晶体管是常开型电路，以及
所述第二晶体管配置和布置成将所述常开型电路操作成处于常关断状态。
9.根据权利要求1所述的设备，其中，所述掺杂区域和所述导电沟槽形成并联连接在所述第二晶体管的源极和漏极之间的二极管和电容器。
10.根据权利要求1所述的设备，其中，所述掺杂区域配置和布置成其中有掺杂剂，以设置所述漏极和沟道之间的击穿电压。
11.根据权利要求1所述的设备，其中，所述导电沟槽配置和布置成所述导电沟槽之间有一定的距离，以设置所述漏极和沟道之间的击穿电压。
12.根据权利要求1所述的设备，其中，所述导电沟槽和所述掺杂区域配置和布置成经由所述掺杂区域中的掺杂剂和各所述导电沟槽间隔开的距离来设置所述漏极和沟道之间的击穿电压。
13.一种方法，包括：
提供具有栅极、源极、沟道和漏极的晶体管，所述晶体管易受到包括雪崩击穿的过电压状况的影响；
提供多个导电沟槽；
在相邻的一对导电沟槽之间提供至少一个掺杂区域，每个掺杂区域提供p-n结；以及
利用所述导电沟槽和所述掺杂区域来在所述源极和所述漏极之间提供电容，并且通过限制所述源极和所述漏极之一处的电压电平来减轻所述晶体管的雪崩击穿。
14.根据权利要求13所述的方法，其中，提供所述晶体管、提供所述多个导电沟槽、以及提供所述至少一个掺杂区域的步骤包括：在共同的工艺中同时形成所述晶体管的一部分和所述多个导电沟槽的一部分以及所述至少一个掺杂区域。
15.根据权利要求13所述的方法，还包括：
将所述漏极电耦接到共源共栅晶体管的源极；以及
通过将电压耦合到所述共源共栅晶体管的栅极来控制所述共源共栅晶体管处于关断状态。
16.根据权利要求13所述的方法，还包括通过以下操作中的一个或多个设置所述漏极和沟道之间的击穿电压：
掺杂所述至少一个掺杂区域以实现所述击穿电压；
以设置所述击穿电压的固定距离提供被所述导电沟槽隔开的所述至少一个掺杂区域；
设置所述导电沟槽的深度；
设置绝缘层的厚度，并且通过将每个沟槽内衬有所设定的厚度的绝缘层来形成导电沟槽。
17.根据权利要求13所述的方法，其中
提供所述至少一个掺杂区域包括用所述多个掺杂区域形成二极管，所述二极管连接在所述第二晶体管的源极和漏极之间，以及
限制所述第二晶体管的源极和漏极之一处的电压电平包括使用所述二极管来钳制所述电压。
18.根据权利要求13所述的方法，其中，提供所述多个导电沟槽包括：将所述导电沟槽中的至少一个电连接到所述源极，并且通过将所述导电沟槽中的至少另一个与所述源极电分离来形成RC电路，所述RC电路配置为降低所述源极和所述漏极之间的电压振荡。
19.一种设备，包括：
晶体管，其具有栅极、源极、沟道和漏极；以及
多个导电沟槽和至少一个掺杂区域，所述至少一个掺杂区域位于每对相邻的导电沟槽之间，并且配置为提供p-n结，其中，所述多个导电沟槽和所述至少一个掺杂区域配置和布置成在所述源极和所述漏极之间提供电容，并且通过限制所述源极或所述漏极处的电压电平来减轻所述晶体管的雪崩击穿。
20.根据权利要求19所述的设备，其中，所述漏极电耦接到共源共栅布置中的另一个晶体管的源极，并且其中，所述晶体管配置和布置成通过将来自所述晶体管的源极的电压耦合至共源共栅晶体管的栅极来控制所述另一个晶体管处于关断状态。
CN201710522574.9A 2016-07-01 2017-06-30 具有电压限制和电容增强的电路 Active CN107564903B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/200,308 US9941265B2 (en) 2016-07-01 2016-07-01 Circuitry with voltage limiting and capactive enhancement
US15/200,308 2016-07-01

Publications (2)

Publication Number Publication Date
CN107564903A true CN107564903A (zh) 2018-01-09
CN107564903B CN107564903B (zh) 2023-05-26

Family

ID=58714952

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710522574.9A Active CN107564903B (zh) 2016-07-01 2017-06-30 具有电压限制和电容增强的电路

Country Status (3)

Country Link
US (1) US9941265B2 (zh)
EP (1) EP3264463B1 (zh)
CN (1) CN107564903B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111293175A (zh) * 2018-12-06 2020-06-16 安世有限公司 具有集成钳位二极管的半导体器件
CN111430347A (zh) * 2020-06-11 2020-07-17 嘉兴景焱智能装备技术有限公司 氮化镓栅极级联单元及其集成的半导体结构
CN111490663A (zh) * 2019-01-25 2020-08-04 苏州捷芯威半导体有限公司 智能集成式开关管及谐振型软开关电路

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11632054B2 (en) 2019-04-24 2023-04-18 Power Integrations, Inc. Mode operation detection for control of a power converter with an active clamp switch
EP3959807B1 (en) 2019-04-24 2023-06-07 Power Integrations, Inc. Power converter comprising an active non-dissipative clamp circuit, and respective controller.
US10965218B1 (en) * 2019-11-15 2021-03-30 Power Integrations, Inc. Active clamp circuit with steering network

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040038467A1 (en) * 2001-07-03 2004-02-26 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same
CN101536189A (zh) * 2006-11-16 2009-09-16 万国半导体股份有限公司 具有电磁干扰滤波器的垂直瞬态电压抑制器（tvs）的电路结构及制造方法
EP2256799A2 (en) * 2009-05-28 2010-12-01 International Rectifier Corporation Monolithic vertically integrated composite group III-V and group IV semiconductor device and method for fabricating same
US20110210338A1 (en) * 2010-03-01 2011-09-01 International Rectifier Corporation Efficient High Voltage Switching Circuits and Monolithic Integration of Same
EP2736073A1 (en) * 2012-11-21 2014-05-28 Nxp B.V. Cascode semiconductor device
CN104078461A (zh) * 2013-03-28 2014-10-01 Nxp股份有限公司 级联半导体器件
CN104183631A (zh) * 2013-05-24 2014-12-03 英飞凌科技股份有限公司 半导体器件、制造半导体器件的方法以及集成电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8304314B2 (en) * 2008-09-24 2012-11-06 Semiconductor Components Industries, Llc Method of forming an MOS transistor
US9859882B2 (en) 2011-03-21 2018-01-02 Infineon Technologies Americas Corp. High voltage composite semiconductor device with protection for a low voltage device
US9281388B2 (en) 2011-07-15 2016-03-08 Infineon Technologies Americas Corp. Composite semiconductor device with a SOI substrate having an integrated diode
US9171837B2 (en) 2012-12-17 2015-10-27 Nxp B.V. Cascode circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040038467A1 (en) * 2001-07-03 2004-02-26 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same
CN101536189A (zh) * 2006-11-16 2009-09-16 万国半导体股份有限公司 具有电磁干扰滤波器的垂直瞬态电压抑制器（tvs）的电路结构及制造方法
EP2256799A2 (en) * 2009-05-28 2010-12-01 International Rectifier Corporation Monolithic vertically integrated composite group III-V and group IV semiconductor device and method for fabricating same
US20110210338A1 (en) * 2010-03-01 2011-09-01 International Rectifier Corporation Efficient High Voltage Switching Circuits and Monolithic Integration of Same
EP2736073A1 (en) * 2012-11-21 2014-05-28 Nxp B.V. Cascode semiconductor device
CN104078461A (zh) * 2013-03-28 2014-10-01 Nxp股份有限公司 级联半导体器件
CN104183631A (zh) * 2013-05-24 2014-12-03 英飞凌科技股份有限公司 半导体器件、制造半导体器件的方法以及集成电路

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111293175A (zh) * 2018-12-06 2020-06-16 安世有限公司 具有集成钳位二极管的半导体器件
CN111490663A (zh) * 2019-01-25 2020-08-04 苏州捷芯威半导体有限公司 智能集成式开关管及谐振型软开关电路
CN111430347A (zh) * 2020-06-11 2020-07-17 嘉兴景焱智能装备技术有限公司 氮化镓栅极级联单元及其集成的半导体结构
CN111430347B (zh) * 2020-06-11 2020-09-04 嘉兴景焱智能装备技术有限公司 氮化镓栅极级联单元及其集成的半导体结构

Also Published As

Publication number Publication date
EP3264463A1 (en) 2018-01-03
US20180006015A1 (en) 2018-01-04
US9941265B2 (en) 2018-04-10
CN107564903B (zh) 2023-05-26
EP3264463B1 (en) 2022-07-27

Similar Documents

Publication Publication Date Title
CN107564903A (zh) 具有电压限制和电容增强的电路
US7982239B2 (en) Power switching transistors
CN105226058B (zh) 利用深扩散区在单片功率集成电路中制备jfet和ldmos晶体管
CN103703566B (zh) 半导体装置及其制造方法
US9160326B2 (en) Gate protected semiconductor devices
CN104347620B (zh) 半导体器件、电子电路以及用于切换高电压的方法
CN104134659B (zh) 能够进行雪崩能量处理的iii族氮化物晶体管
CN105280711B (zh) 电荷补偿结构及用于其的制造
CN103035641B (zh) 半导体装置
US10446695B2 (en) Planar multi-implanted JFET
US11245002B2 (en) Superjunction transistor arrangement and method of producing thereof
JP2017118135A (ja) 双方向素子、双方向素子回路および電力変換装置
US8264015B2 (en) Semiconductor device wherein a first insulated gate field effect transistor is connected in series with a second field effect transistor
KR102246570B1 (ko) 전력 반도체 장치
CN104299997A (zh) 电荷补偿半导体器件
JP2015523723A (ja) 高電圧接合型電界効果トランジスタ
TW201517280A (zh) 具有一電流分散層的半導體裝置
US10121907B2 (en) Planar triple-implanted JFET
US20140021934A1 (en) Devices and components for power conversion circuits
CN107785367A (zh) 集成有耗尽型结型场效应晶体管的器件及其制造方法
CN101719721B (zh) 低压电源
CN103378159A (zh) 具有mosfet的晶体管装置和制造方法
CN107482006B (zh) 具有集成二极管的晶体管器件
US20240072785A1 (en) Electronic circuit with a transistor device and a clamp circuit and method
WO2018187651A1 (en) Planar multi-implanted jfet

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant