CN104078461A - 级联半导体器件 - Google Patents

级联半导体器件 Download PDF

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CN104078461A
CN104078461A CN201410053613.1A CN201410053613A CN104078461A CN 104078461 A CN104078461 A CN 104078461A CN 201410053613 A CN201410053613 A CN 201410053613A CN 104078461 A CN104078461 A CN 104078461A
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effect transistor
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菲利浦·拉特
马尔腾·雅各布斯·斯万内堡
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Naizhiya Co Ltd
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Abstract

一种半导体器件，包括以级联形式布置的第一场效应晶体管和第二场效应晶体管，其中所述第一场效应晶体管是耗尽型晶体管；并且其中所述第二场效应晶体管包括第一源栅电容和与第一源栅电容并联的第二附加源栅电容。一种功率因子校正(PFC)电路，包括所述半导体器件。一种电源，包括所述PFC电路。

Description

级联半导体器件
技术领域
本发明涉及半导体器件，具体涉及晶体管级联布置。更具体地，本发明涉及一种级联布置，所述级联布置包括基于氮化镓的晶体管器件。本发明还涉及包括这种级联布置的功率因子校正电路和包括这种功率因子校正电路的电源。
背景技术
例如在机动(automotive)电子器件和高功率RF技术中，诸如III-V氮化镓(GaN)高电子迁移率晶体管(HEMT)和SiC基结栅极场效应晶体管(JFET)器件等器件已经使能了高电压、高电流和低导通电阻操作，从而得到高功率和高效率操作。HEMT和JFET是场效应晶体管器件的示例。GaN基器件的宽带隙提供了能够高电压高温度操作的鲁棒且可靠的器件。由于与硅基器件相比RF性能更好(低电容和高击穿电压)，GaN技术越来越受欢迎，其中硅基器件例如用于在计算设备和便携式通信设备的电源中使用的功率因子校正电路。
GaN基场效应晶体管器件典型地制造在硅(Si)、碳化硅(SiC)和蓝宝石衬底上。GaN HEMT或者SiC JFET典型地是耗尽型器件，因此需要负栅极电压(当与源极电压相比时)和栅漏偏置来切换器件。因此，这种器件已知是常开(normally on)器件。换句话说，当在使用时并且不施加栅源电压的情况下，器件处于导通状态。
作为常开的结果，没有隔离输入电源电压。因此在机动和电源应用所需的高电压(例如200-600伏)下，无法隔离输入电压可能增加损坏与这种高电压器件相连的低功率辅助电路和部件的风险。因此，驱动GaNHEMT或者JFET器件由于多种原因而具有挑战性。最明显的是，需要负电压偏置来切换这种常开器件。
一种针对这种高电压常开器件创建常关(normally off)开关的技术是使用级联布置。如图1所示，在这种布置中，将低电压FET14放置在的高电压FET10器件的源极。当关断低电压FET时，在常开高电压器件中产生负栅极电压，从而关断高电压器件。
如图1所示，低电压FET是NMOS器件。将NMOS低电压FET放置于高电压器件的源极，其中低电压FET的漏极与高电压器件的源极相连。高电压器件的栅极和低电压FET的源极相连，使得它们是级联器件的源极端子。
当关断高电压FET器件时，通过以下给出的等式1来确定低电压FET的漏源电压VDS(示出为图1中的Vx)。Vx是高电压器件的阈值电压和电容的函数。在等式1中，电容COSS(MOS)等于低电压FET器件的栅漏电容CGD和漏源电容CDS之和。
Vx = C DS ( GaN ) · V d - ( C OSS ( MOS ) + C GS ( GaN ) ) · V th ( GaN ) C DS ( GaN ) + ( C OSS ( MOS ) + C GS ( GaN ) )             等式1
从等式1可以看出，作为低电压FET的漏源电压VDS，Vx依赖于施加的额定电压Vd，所述额定电压Vd由高电压FET器件的最大额定电压限制。典型地，高电压FET器件的最大额定电压在60至100伏特范围内。
当级联器件已经关断时，也就是没有向低电压FET施加栅极电压Vg时，漏源电压Vx将依赖于高电压FET和低电压FET的相应反向漏电流而变化。高电压FET的漏源漏电流IDS(GaN)将增加级联器件漏源电压Vx，而低电压FET的漏源漏电流IDS(nmos)将减小级联器件的漏源电压Vx。因此，低电压FET的漏源电压将保持恒定、降低或者增加，并且可以依赖于漏电流ID(GaN)、IDS(nmos)以及高电压FET的栅极漏电流IG(GaN)来表示这些情况。
1.Vx恒定：IDS(nmos)IG(GaN)＝ID(GaN)
2.Vx降低：IDS(nmos)IG(GaN)>ID(GaN)
3.Vx增加：IDS(nmos)IG(GaN)<ID(GaN)
在以上的情况1至3的每一种情况下，因为高电压FET的源极处于比栅极更高的电势，IG(GaN)的值将是负的。
对于上述的情况1，每个漏电流平衡，使得Vx保持恒定。
对于上述的情况2，Vx降低至大约高电压FET的阈值电压Vt，在所述阈值电压Vt处ID(GaN)将增加，直到漏电流平衡并且Vx稳定为止。
对于上述的情况3，Vx增加至低电压FET的雪崩电压，在所述雪崩电压处IDS(nmos)将增加，直到漏电流平衡并且Vx稳定为止。这种情况可以引起低电压FET雪崩。
典型地，与Si基器件相比GaN基器件目前具有更高的漏电流，额定电压的差异越大泄漏的差异越大。这意味着在确定是否发生情况3并强制使低电压MOSFET雪崩时，GaN器件中栅极泄漏的级别是严格的。
在高电压FET合并了肖特基栅极的情况下，漏极漏电流的大部分将经由栅极离开高电压FET。同样地，高电压器件的漏源漏电流IDS(GaN)将较低，因为漏电流经由栅极离开，几乎没有电流经由源极离开，所以IDS(GaN)将较低(并且IG(GaN)将较高)，并且将发生上述情况2给出的情形。然而由于稳定性问题，如由GaN器件的高切换速率导致的高频振荡，可能需要在高电压FET的栅极处包括串联栅极电阻器以减小栅极漏电流。如果栅极阻抗高(IG(GaN)变低)，将发生情况3，Vx增加至低电压器件的雪崩电压。
相较于肖特基栅极器件，由于绝缘栅极GaN器件的栅极泄漏明显更低(由于在栅极端子和GaN材料之间提供的电隔离的存在)从而在使用时可能使得在应用中能量损耗更小，所以绝缘栅极GaN器件更加优选。然而，由于与低电压FET的低漏极漏电流相结合的低泄漏，情况3的雪崩情形更可能在绝缘栅极器件中发生。
在一些情况下，在雪崩条件下操作低电压器件将导致增加的器件工作温度，并且这可能有问题的，例如在器件不是连续操作的情况下或者在提供足够的热沉/封装的情况下。然而，对于长期器件可靠性，需要不在雪崩条件下操作，因为向低电压MOSFET的栅极氧化物中注入热载流子可能导致增加的Rd(导通)、阈值电压Vt减小或增加的漏源泄漏以及最终的器件故障。另外，如果低电压FET的雪崩电压大于高电压FET的最大栅极电压，那么可能损坏高电压FET并且可能发生故障。
发明内容
提出了一种半导体器件，包括以级联形式布置的第一场效应晶体管和第二场效应晶体管，其中所述第一场效应晶体管是在操作时具有漏电流的耗尽型晶体管；其中所述第二场效应晶体管包括固有漏源电阻和与第一漏源电阻并联布置的附加漏源电阻，第二附加漏源电阻布置为使得在操作时通过附加电阻的电流大于第一场效应晶体管的漏电流。
附加的电阻确保了当级联器件处于关断状态时第二场效应晶体管的漏源电压不会增加，并且有效地增加第二场效应晶体管的泄漏。
第二附加漏源电阻可以是电阻型分压器，所述电阻型分压器包括连接为电压分压器的至少两个电阻，其中电压分压器的公共节点与第三场效应晶体管的栅极相连。这种布置形成了主动箝位，并且增加了电路设计自由度，也就是不需要选择电阻器值(欧姆)来确保低电压FET的总漏电流总是大于第一场效应电阻器，从而防止了如上所述的附加功率损耗。
还提出了一种包括半导体器件的功率因子校正电路和一种包括所述功率因子校正电路的电源。
附图说明
下文中只参考附图作为示例进一步描述本发明，其中：
图1是根据现有技术的级联布置的电路图；
图2是根据本发明的级联布置的电路图；
图3是具有附加电阻的低电压MOSFET器件的管芯布局；
图4是箝位布置的电路图；以及
图5是功率因子校正电路的电路图。
具体实施方式
尽管以下讨论涉及MOSFET、JFET和HEMT，本领域普通技术人员应该认识到可以使用任意合适的晶体管。本领域普通技术人员还应该认识到可以依赖于特定的应用需求而使用任意器件额定电压。
如图1所示，级联布置包括第一场效应晶体管，例如高电压FET器件10。高电压器件10具有源极端子13、栅极端子12和漏极端子11。级联布置还包括第二场效应晶体管，例如低电压n-沟道MOSFET14。低电压MOSFET器件14和高电压FET器件10设置为三端子级联。高电压FET10的栅极12与低电压MOSFET14的源极15相连。高电压FET10的源极13与低电压MOSFET14的漏极16相连。高电压FET相较于低电压FET在更高的电压下工作。如在现有技术中所理解的，高电压器件和低电压器件称作高侧器件和低侧器件。
所得到的级联布置提供了三端子器件，其中高电压FET器件10的漏极11是漏极端子，并且低电压MOSFET器件14的栅极17和源极15分别提供了栅极端子和源极端子。
图2示出了图1的级联布置(其中类似的参考数字与图1中的类似特征相对应)，具有一些附加电路细节。高电压FET器件10可以是GaN HEMT或者SiC JFET，具有固有漏源电容C_gan，所述固有的漏源电容C_gan是高电压器件10的固有结电容。然而本领域普通技术人员应该理解的是可以使用任意合适的常开器件。这样，低电压MOSFET14可以是n-沟道MOSFET，并且具有固有漏源电容C_mos，所述固有漏源电容C_mos是低电压MOSFET14的固有结电容。本领域普通技术人员应该理解的是可以使用任意合适的低电压MOSFET。
可以横跨低电压MOSFET的漏极和源极提供附加电容C_add。附加电容有助于防止在Vx下发生高瞬时电压。
低电压MOSFET14包括固有漏源电阻(未示出)。当低电压MOSFET14处于导通状态时，这种电阻已知为Rds(导通)，并且是源极材料电阻、沟道电阻、外延层的电阻和漏极电阻之和。可以横跨低电压MOSFET14的漏极和源极提供附加电阻Radd，使得附加电阻Radd与低电压MOSFET14并联。
可以通过将分离的电阻集成到包含高电压MOSFET和低电压MOSFET的整体级联器件管芯上来包括附加电电阻Radd。替代地，高电压MOSFET和低电压MOSFET可以在分离的管芯上，附加电阻Radd集成到廉价的低电压MOSFET管芯14上。替代地，附加电阻Radd可以是没有集成到任何管芯上的分立电阻，而是简单地在电路级横跨低电压MOSFET14的漏极连接和源极连接而外部地连接。
对于将附加电阻Radd集成到廉价低电压MOSFET14管芯上的情况，可以在与低电压MOSFET的源极和漏极相连的管芯的多晶硅材料中形成所谓的多晶硅电阻器(poly-resistor)。可以在形成低电压MOSFET的多晶硅栅极结构的同时形成多晶硅电阻器。也可以使用诸如SIPOS(半绝缘多晶硅)之类的其他层来形成附加电阻。典型地，例如可以在管芯的边缘处连接漏极。因为这种电阻器横跨边缘端接(edge termination)结构，所以存在以下风险：这种电阻器上的电压可能导致寄生沟道，所述寄生沟道损害了边缘端接的能力。确保不发生这种情况(例如，通过将电阻器设置在较厚的绝缘材料上面)的方法在本领域是众所周知的，并且为了简明起见这里不进行描述。
替代地，如图3所示，深沟槽隔离结构(也就是垂直沟槽结构)可以用于在低电压MOSFET管芯上形成附加电阻Radd。深沟槽隔离结构的形成在本领域是众所周知的，并且为了简明起见这里不进行讨论。如前所述，附加电阻Radd与低电压MOSFET的漏极连接30和源极连接30相连。在这种情况下，例如通过使用蛇形或弯折(meander)结构，将多晶硅电阻器的宽度限制为沟槽结构的宽度，使得所需的电阻占据较少的管芯空间。另外，这种结构的使用确保了通过如上所述的横跨边缘端接的附加电阻Radd不会损害边缘端接34。此外，可以通过添加p-体掩模(p-body mask)(未示出)将漏极连接从边缘端接移开，从而允许Radd位于管芯任意部分上。在图3中，垂直沟槽结构与源极连接32(有效地用作边缘端接)相连，也就是说有源器件区域可以是在这种结构的底部。
附加电容确定漏源电压Vx的值(根据上述等式1)。附加电阻的R_add值(欧姆)应该使得在操作期间在最大允许漏源电压下通过附加电阻器Radd的电流将总是大于高电压FET的漏源漏电流IDS。因此，附加电阻Radd的值需要确保Vx将总是减小。Vx将落到使高电压FET10在低电流下导通的点，从而确保了流过高电压FET10的电流与流过附加电阻Radd的电流匹配，并且实现了上述的情况1。
为了防止电压Vx上升并且引起低电压MOSFET14雪崩，至接地的电流路径的电流之和应该大于或等于GaN器件的漏极电流。如果Vx除以Radd大于Id(GaN)，那么雪崩将不会发生。关于上述三种情况，情况2或情况3将发生在关断器件时(所有电流精确匹配的可能性非常低)，因此Vx将降低至使高电压FET10开始充分传导以至于满足情况1的点，或者替代地Vx将增加到低电压MOSFET14雪崩为止。
如图4所示，附加电阻Radd可以设置为箝位电路51。箝位电路51包括放置于低电压MOSFET14的漏极和源极之间的电阻型分压器50。电阻型分压器50包括两个电阻52和54。电阻型分压器(50)的中点(或者公共节点)55与另外的低电压MOSFET56的栅极相连。
在操作中，如果高电压FET10的漏电流引起Vx上升，相应地电阻型分压器中点处的电压也上升。所述中点是电压分压器的公共节点。因为所述中点与另外的低电压MOSFET56(用作箝位器件)的栅极相连，一旦所述中点达到MOSFET56的阈值电压，MOSFET56将开始导通。当发生这种情况时，来自高电压FET10的过量电流不再对低电压MOSFET14的电容充电，而是流过另外的低电压MOSFET56的沟道。按照这种方式，满足了情况1。也就是说，由于另外的低电压MOSFET56的附加电流，电流现在平衡了，并且在不会引起总漏电流增加的情况下Vx稳定。
如上所述，可以使用深沟槽隔离结构或者通过所谓的多晶硅电阻器来集成电阻型分压器50。替代地，电阻型分压器50可以不与级联器件集成，而是在电路级设置在器件的外部。
上述布置的应用可以包括功率因子校正(PFC)电路，PFC电路用于隔离用于移动计算设备和电信设备的AC-DC干线转换器电源。在这种电源中，AC输入有效地经历(see)大电感性负载，所述大电感性负载可以引起电源的功率因子小于1。PFC电路允许AC输入经历接近单位一(nearunity)功率因子。依赖于电源的输出功率，州(state)和国家(national)法律现在要求接近单位一功率因子。
公共PCF电路是有源升压PFC，所述有源升压PFC确保了从电源汲取的电流是正弦的(即无谐波)并且与电流同相。图5中说明了这种布置。
如图5所示，PFC电路的输入I/P是整流的AC干线电压，并且输出是整流的DC电压。AC干线的整流是通过所示的二极管电桥电路实现的。升压电路本身包括电感器L、高电压功率开关S和高电压PFC二极管D。控制高电压开关S的占空比，使得调节输出电压Vout从而确保接近单位一的功率因子，并且将谐波电流失真最小化。PFC二极管D可以是高电压部件，在高效率PFC电路中可以在SiC或GaN中制造PFC二极管D，因为由于这些器件的反向恢复特性比硅器件好。具体地，可以在GaN HEMT工艺中在相同的管芯上制造高电压开关S和二极管两者。
在这种具体的电路中，高电压输入经由电感器与高电压开关S的漏极相连，高电压开关S的源极接地。然后，当没有操作时(也就是没有向开关施加功率)，高电压开关必须关断以防止将输入电压短接到接地。由于这种要求，需要在级联布置中使用常开器件以将其转换为常关器件。为此目的，上述级联布置适用作高电压开关S以在这种PFC布置中使用。
在这种PFC应用中使用的级联器件也可以将PFC二极管集成到相同的封装中。例如在GaN HEMT工艺中级联开关S和二极管制造工艺可以兼容，那么可以将这两个部件集成到单一的管芯中。替代地，二极管D可以与低电压MOSFET14或者高电压FET10器件集成。
上述布置也可以用于将功率器件与控制电路单片集成，例如在紧凑荧光照明(CFL)应用中。
在所附的独立权利要求中阐述了本发明的具体和优选方面。可以将来自从属权利要求和/或独立权利要求的特征组合适当地进行组合，不仅仅是在权利要求中进行阐述。
本公开的范围包括任意新特征或者本文明确或非明确公开的任意新组合或其任意概括，不管其是否涉及要求保护的发明，也不管其是否解决了本发明解决的技术问题中的任何一个或全部。申请人这里需要提醒注意的是，在本申请或者得自本申请的任意后续申请的程序期间，可以用这些特征构成新的权利要求。具体地参考所附权利要求，可以将从属权利要求中的特征与独立权利要求中的特征相组合，各个独立权利要求中的特征可以按照任意合适的方式进行组合，而不是仅以权利要求中枚举的特定组合的形式来组合。
在分离的实施例的上下文中描述的特征也可以在单一实施例中以组合的形式提供。相反为了简明起见，在单一实施例的上下中描述的各种特征也可以分离地或者按照任意适当的子组合方式提供。
为了完整起见，还需要声明的是，术语“包括”不排除其他元件或步骤，术语“一种”不排除多个，单一处理器或其他单元可以实现在权利要求中阐述的多个装置的功能，权利要求中的参考符号不应构成对权利要求的范围的限制。

Claims (13)

1.一种半导体器件，包括以级联形式布置的第一场效应晶体管和第二场效应晶体管，
其中所述第一场效应晶体管是在操作时具有漏电流的耗尽型晶体管；
其中所述第二场效应晶体管包括固有漏源电阻和与第一漏源电阻并联布置的附加漏源电阻，第二附加漏源电阻布置为使得在操作时流经附加电阻的电流大于第一场效应晶体管的漏电流。
2.根据权利要求1所述的半导体器件，其中所述漏电流是漏源漏电流。
3.根据权利要求1所述的半导体器件，其中所述第二附加漏源电阻是电阻型分压器，并且所述第二附加漏源电阻包括至少两个电阻，所述至少两个电阻连接为具有公共节点的电压分压器，其中所述电压分压器的公共节点与第三场效应晶体管的栅极相连。
4.根据权利要求3所述的半导体器件，其中所述第二附加漏源电阻是主动箝位。
5.根据权利要求1至4中任一项所述的半导体器件，其中所述第二附加漏源电阻与所述第二场效应晶体管集成。
6.根据权利要求1至5中任一项所述的半导体器件，其中通过深沟槽隔离来集成所述第二附加漏源电阻。
7.根据任一前述权利要求所述的半导体器件，包括横跨所述第二场效应晶体管的漏极和源极并联布置的附加电容。
8.根据权利要求7所述的半导体器件，其中所述附加电容布置为增大所述第二场效应晶体管的结电容。
9.根据权利要求1所述的半导体器件，其中所述第一场效应晶体管是高电子迁移率晶体管或者结型栅极场效应晶体管。
10.根据权利要求3所述的半导体器件，其中所述第二场效应晶体管和第三场效应晶体管是n-沟道晶体管。
11.根据权利要求3所述的半导体器件，其中所述第一场效应晶体管、第二场效应晶体管和第三场效应晶体管被集成到单一管芯上。
12.一种功率因子校正电路，包括根据权利要求1至11中任一项所述的半导体器件。
13.一种电源，包括根据权利要求11所述的功率因子校正电路。
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