CN107546257A - 金属‑氧化物沟道半导体场效应晶体管的外延层结构 - Google Patents
金属‑氧化物沟道半导体场效应晶体管的外延层结构 Download PDFInfo
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Abstract
本发明公开了一种金属‑氧化物沟道半导体场效应晶体管的外延层结构,金属‑氧化物半导体场效应晶体管设置有外延层结构、栅极、衬底和沟道,沿衬底指向栅极的方向定义为延伸方向,外延层结构的掺杂浓度沿延伸方向先逐渐增大然后再逐渐减小。本发明能够使金属‑氧化物沟道半导体场效应晶体管器件的耐压能力得到提高,降低其导通电阻并增强可靠性,得以进一步提高金属‑氧化物沟道半导体场效应晶体管器件的沟道密度,减小单胞尺寸。
Description
技术领域
本发明属于场效应晶体管技术领域,尤其涉及一种金属-氧化物沟道半导体场效应晶体管的外延层结构。
背景技术
金属-氧化物半导体场效应晶体管是一种以金属层的栅极隔着氧化层利用电场的效应来控制半导体的场效应晶体管,被广泛使用在模拟电路与数字电路中。随着半导体工艺的进步,使得高密度深沟道结构变得可能,从而进一步减小器件单胞尺寸。在半导体工艺中,外延层为生长在衬底上的单晶硅。
但是过去所用的沟道MOSFET(金属-氧化物半导体场效应晶体管)采用的单外延层或者双外延层随着沟道的变深和密度变大,已经不能最大化的优化沟道功率MOSFET器件的表现。因此,需要更优化的外延层的设计来配合高密度深沟道的工艺结构来优化沟道功率MOSFET器件比如增强器件的耐压能力(BV),减小导通电阻(Rdson),从而改进器件的品质因数。外延层的厚度和参杂浓度的不同会影响沟道功率MOSFET器件的功能参数。
发明内容
针对现有技术存在的技术缺陷,本发明的目的是提供一种金属-氧化物沟道半导体场效应晶体管的外延层结构,所述外延层结构的掺杂浓度先逐渐增大然后再逐渐减小。
优选地,所述金属-氧化物半导体场效应晶体管设置有栅极、衬底和沟道,沿所述衬底指向所述栅极的方向定义为延伸方向,所述外延层结构的掺杂浓度沿所述延伸方向先逐渐增大然后再逐渐减小。
优选地,所述外延层结构沿所述延伸方向包括第一外延层、第二外延层和第三外延层,所述第一外延层和所述第三外延层的掺杂浓度均小于所述第二外延层的掺杂浓度的最大值。
优选地,沿所述延伸方向,所述第二外延层包括多个子层且多个所述子层的掺杂浓度不同,所述第一外延层是均匀分布的,第三外延层的掺杂浓度是均匀分布的,具有最高掺杂浓度的所述子层位于所述第二外延层的上半部分且所述最高掺杂浓度大于所述第一外延层和所述第三外延层的掺杂浓度。
优选地,沿所述延伸方向,多个所述子层的掺杂浓度按照如下方式分布:
-先逐渐增大然后再逐渐减小;
-逐渐增大至所述最高掺杂浓度然后再均匀分布;
-先逐渐增大至所述最高掺杂浓度然后再均匀分布,最后再逐渐减小。
优选地,沿所述延伸方向,所述第一外延层的上表面低于所述沟道的底部,所述沟道的底部位于所述第二外延层的下半部分,所述第三外延层的下表面高于所述栅极的底部。
优选地,沿所述延伸方向,所述第二外延层包括多个子层且多个所述子层的掺杂浓度不同,所述第一外延层是均匀分布的,所述第三外延层的掺杂浓度逐渐减小,具有最高掺杂浓度的所述子层位于所述第二外延层的上半部分,所述最高掺杂浓度大于所述第一外延层,所述最高掺杂浓度大于或等于所述第三外延层下表面的掺杂浓度,所述第三外延层的掺杂浓度逐渐减小。
优选地,沿所述延伸方向,多个所述子层的掺杂浓度按照如下方式分布:
-逐渐增大;
-逐渐增大至所述最高掺杂浓度然后再均匀分布。
优选地,沿所述延伸方向,所述第一外延层的上表面低于所述沟道的底部,所述沟道的底部位于所述第二外延层的下半部分,所述第三外延层的下表面低于所述栅极的底部。
优选地,沿所述延伸方向,所述第二外延层下表面的掺杂浓度大于所述第一外延层上表面的参杂浓度,所述第二外延层上表面的掺杂浓度大于所述第三外延层下表面的掺杂浓度,所述第一外延层是均匀分布的,第三外延层的掺杂浓度是均匀分布的。
优选地,沿所述延伸方向,所述第二外延层的掺杂浓度是均匀分布的或者是逐渐增大的。
优选地,所述第一外延层的掺杂浓度小于所述第三外延层的掺杂浓度。
优选地,沿所述延伸方向,所述第一外延层的上表面高于所述沟道的底部,所述沟道的底部位于所述第一外延层内,所述第三外延层的下表面低于所述栅极的底部。
本发明通过对金属-氧化物沟道半导体场效应晶体管的外延层结构的参杂浓度进行相应的设置,突破了传统的单外延层或双外延层结构。提供至少具有3外延层的结构,并且不同高度的外延层结构的参杂浓度的也不同,使得功率MOSFET器件的耐压能力得到提高,降低了功率MOSFET器件的道统电阻,提高了MOSFET的可靠性。
附图说明
通过阅读参照以下附图对非限制性实施例所作的详细描述,本发明的其它特征、目的和优点将会变得更明显:
图1示出了本发明的具体实施方式的,一种金属-氧化物沟道半导体场效应晶体管器件的纵向剖面示意图;
图2示出了本发明的具体实施方式的,一种金属-氧化物沟道半导体场效应晶体管外延层结构中,掺杂浓度随外延层深度变化关系图;
图3示出了本发明的具体实施方式的,另一种金属-氧化物沟道半导体场效应晶体管外延层结构中,掺杂浓度随外延层深度变化关系图;
图4示出了本发明的具体实施方式的,另一种金属-氧化物沟道半导体场效应晶体管外延层结构中,掺杂浓度随外延层深度变化关系图;
图5示出了本发明的具体实施方式的,另一种金属-氧化物沟道半导体场效应晶体管外延层结构中,掺杂浓度随外延层深度变化关系图;
图6示出了本发明的具体实施方式的,另一种金属-氧化物沟道半导体场效应晶体管外延层结构中,掺杂浓度随外延层深度变化关系图;
图7示出了本发明的具体实施方式的,另一种金属-氧化物沟道半导体场效应晶体管外延层结构中,掺杂浓度随外延层深度变化关系图;
图8示出了本发明的具体实施方式的,另一种金属-氧化物沟道半导体场效应晶体管外延层结构中,掺杂浓度随外延层深度变化关系图;
图9示出了本发明的具体实施方式的,另一种金属-氧化物沟道半导体场效应晶体管外延层结构中,掺杂浓度随外延层深度变化关系图;
图10示出了本发明的具体实施方式的,对应于图8和图9的掺杂浓度随外延层深度变化关系图的一种金属-氧化物沟道半导体场效应晶体管器件的纵向剖面示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清晰,下面结合附图及其实施例对本发明的技术方案进行描述。
图1示出了本发明的具体实施方式的,一种金属-氧化物沟道半导体场效应晶体管器件的纵向剖面示意图。所述金属-氧化物沟道半导体场效应晶体管(沟道功率MOSFET)按导电沟道可进一步分为P沟道和N沟道器件;按栅极电压幅值可分为当栅极电压为零时漏源极之间存在导电沟道的耗尽型以及栅极电压大于(小于)零时存在导电沟道的增强型。在本发明中,功率MOSFET主要即N沟道增强型(但并不限于N沟道MOSFET,同理的实施方式也适用于P沟道MOSFET)。具体地,如图1所示,所述沟道功率MOSFET器件从下至上依次包括碳化硅构成的底部衬底1,形成在衬底1之上的外延层结构,位于所述外延层结构两侧的直条形沟道3,所述外延层结构表面的硅晶圆形成所述沟道功率MOSFET的基区4,所述基区4表面为由源极金属形成的源区5,所述源极金属由钛、硅化钛或其他低势垒高度金属组成。其中,所述衬底1、外延层结构以及所述基区4分别采用具有不同导电特性的半导体硅材料制作而成。在本发明中,所述外延层结构的参杂浓度和厚度根据需要进行设置,通常,通过在所述外延层结构的硅基体中混入硼、磷、砷的卤化物或氢化物作为掺杂剂,在此不予赘述。
进一步地,所述外延层结构的的掺杂浓度在纵向不同深度由下至上先逐渐增大然后再逐渐减小。需要说明的是,所述外延层2的厚度可以根据需要设定,从所述外延层结构的上表面到不同的深度区域的所述外延层的硅基质中的掺杂浓度不同。这样的设置,可以通过将所述外延层2在纵向不同深度进一步细分为多个子层,使得所述外延层结构为多层结构,每一层的掺杂浓度情况不同,从而在不同深度行成不同的浓度梯度。更进一步地,所述外延层结构至少可以被划分为3层,其中,中间外延层的掺杂浓度最高,顶部外延层以及底部外延层的掺杂浓度低于所述中间外延层。优选地,所述顶部外延层的掺杂浓度还高于所述底部外延层的掺杂浓度。更为具体地,将在后述具体实施例中结合附图做更为详细的说明,在此不予赘述。
继续参考图1,所述沟道3中包括位于所述沟道3表面的沟槽式栅极31和设置在所述栅极31下方并与所述栅极31绝缘的屏蔽栅32。所述栅极31以及所述屏蔽栅32在所述沟道3中优选填充有多晶硅。所述栅极31围绕在所述沟道3的侧壁,所述基区4位于所述栅极31之间。所述屏蔽栅32用于屏蔽、减小栅极-漏极电容并提高晶体管的截止电压。进一步地,沿所述衬底1指向所述栅极31的方向定义为延伸方向,所述外延层结构的掺杂浓度沿所述延伸方向先逐渐增大然后再逐渐减小。更进一步地,所述外延层结构沿所述延伸方向包括第一外延层21、第二外延层22和第三外延层23,所述第一外延层21和所述第三外延层23的掺杂浓度均小于所述第二外延层22的掺杂浓度的最大值。具体地,参考图1,所述第一外延层21的上表面低于所述沟道3的底部,所述第一外延层21的掺杂浓度要低于所述第二外延层22的掺杂浓度。进一步地,所述沟道3的底部所在深度位于所述第二外延层22的下半部分所在深度。所述外延层结构的掺杂浓度的最高值位于所述第二外延层中,在所述第二外延层中,沿所述延伸方向,所述第二外延层22的参杂浓度可以逐渐增大至所述最高值再逐渐下降,可以是均匀变化,也可以是突变,更为具体的,将在后述具体实施例中进一步说明。所述第三外延层23的底部所在深度要深于所述栅极31的底部,所述第三外延层23的掺杂浓度低于所述第二外延层22的掺杂浓度的最大值。
在本发明的一个优选的具体实施例中,如图2所示,一种金属-氧化物沟道半导体场效应晶体管外延层结构中,掺杂浓度随外延层深度变化关系图。结合图1、图2,沿所述延伸方向,所述外延层结构的底部外延层的掺杂浓度最低,并且所述底部外延层的掺杂浓度为固定值,参杂剂在所述底部外延层中均匀分布,随着所述外延层结构深度的减小至所述中部外延层,在所述中部外延层中,所述掺杂浓度随着所述深度的减小逐渐增加,优选二者呈一次函数的线性关系,且所述掺杂浓度在所述中间外延层的顶端时具有最高值。随后,在顶部外延层,所述掺杂浓度降至某一固定值,参杂剂在所述顶部外延层中均匀分布。
综上,本发明的技术方案,由所述衬底1向上延伸至少依次设有第一外延层21、第二外延层22以及第三外延层23的结构,并且通过设置所述外延层结构中的不同部分与所述沟道3的位置关系,突破了现有技术中单外延层或双外延层的局限,可以将所述沟道3的沟道密度增加,使得所述沟道3相互之间的间距变小,并且随着所述沟道3的变深使得隔离栅32的屏蔽作用加强,在保证同样的耐压能力的同时,使传统沟道功率MOSFET器件的第二外延层和第一外延层的掺杂浓度得以增加,并降低导通电阻。进一步地,由于本发明中所述第三外延层23的掺杂浓度较低,能用比较低的P型掺杂浓度形成沟道MOSFET的基区以得到期望的阈值电压,同时基区的PN结的临界电场强度下降对MOSFET的非制动感应开关(UIS)能力有明显提升。
作为本发明的不同优选实施例,图3至图5分别示出了本发明的具体实施方式的,所述外延层结构中,掺杂浓度随外延层深度变化关系图。其中,图3、图4以及图5中所述第一外延层21的厚度相同,所述第二外延层22的厚度相同,所述第三外延层23的厚度相同。具体地,沿所述延伸方向,所述第二外延层22包括多个子层且多个所述子层的掺杂浓度不同,需要说明的是,引入所述子层的表述是为了更便于对所述外延层的结构特点进行更为准确的描述,并不代表在所述第二外延层22中存在明确的分层以及层与层之间的界线。所述第一外延层21是均匀分布的,所述第三外延层23的掺杂浓度同样是均匀分布的,即所述第一外延层21以及所述第三外延层23各自不同深度的掺杂浓度相同,所述第一外延层21的掺杂浓度优选不同于所述第三外延层。更为优选的,所述第一外延层21的掺杂浓度低于所述第三外延层23的掺杂浓度。进一步地,在所述第二外延层22中,具有最高掺杂浓度的所述子层位于所述第二外延层22的上半部分且所述最高掺杂浓度大于所述第一外延层21和所述第三外延层23的掺杂浓度。
下面分别对图3至图5所示的实施例进行详细描述。在图3所示实施例中,所述第二外延层22中,沿所述延伸方向,多个所述子层的掺杂浓度先逐渐增大然后再逐渐减下。如图3所示,所述第一外延层21以及所述第三外延层23的掺杂浓度为固定值,在所述第一外延层21以及所述第三外延层23中均匀分布。所述第一外延层21的掺杂浓度优选小于所述第三外延层23的掺杂浓度。进一步地,在所述第二外延层22中沿所述延伸方向,掺杂浓度随所述第二外延层22的深度值的减小而增加,二者优选呈线性的一次函数关系。当所述深度减小至所述第二外延层22的上半部分中的特定深度位置时达到掺杂浓度的最高值,并继续随着深度的减小而呈线性递减直至到达所述第二外延层22的顶部。所述第二外延层22的最底端的参杂浓度与所述第一外延层21的最顶端的掺杂浓度相同;所述第二外延层22的最顶端的参杂浓度与所述第三外延层23的最底端的掺杂浓度相同。
作为图3所示实施例的一个变化例,在图4中,所述第一外延层21以及所述第三外延层23的设置与图3所示实施例相同。如图4所示,沿所述延伸方向,在所述第二外延层22中,多个所述子层的掺杂浓度随所述第二外延层22的深度值的减小而增加,二者优选呈线性的一次函数关系。当所述深度减小至所述第二外延层22的上半部分中的特定深度位置时达到掺杂浓度的最高值,并继续随着深度的减小而保持所述最高值直至到达所述第二外延层22的顶部,即在所述第二外延层22的上半部分的特定深度以上位置的所述子层的参杂浓度固定为所述最高值。所述第二外延层22的最底端的参杂浓度与所述第一外延层21的最顶端的掺杂浓度相同。
在另一个变化例中,如图5所示,所述第一外延层21以及所述第三外延层23的设置与图3所示实施例相同。沿所述延伸方向,在所述第二外延层22中,多个所述子层的掺杂浓度随所述第二外延层22的深度值的减小而增加,二者优选呈线性的一次函数关系。当所述深度减小至所述第二外延层22的上半部分中的特定深度位置时达到掺杂浓度的最高值,并且在向上一定厚度范围内维持所述最高值,随后再随着深度的减小而呈线性递减直至到达所述第二外延层22的顶部。所述第二外延层22的最底端的参杂浓度与所述第一外延层21的最顶端的掺杂浓度相同;所述第二外延层22的最顶端的参杂浓度与所述第三外延层23的最底端的掺杂浓度相同。
结合图1至图5,沿所述延伸方向,所述第一外延层21的上表面低于所述沟道3的底部,所述沟道3的底部位于所述第二外延层22的下半部分,所述第三外延层23的下表面深于所述栅极31的底部,在此不予赘述。
图6、图7分别示出了本发明的具体实施方式的,另一种所述外延层结构中,掺杂浓度随外延层深度变化关系图。图6所示实施例的第一外延层21以及第三外延层23的设置与图7所示实施例中所述第一外延层21以及所述第三外延层23的设置相同。具体地,沿所述延伸方向,所述第二外延层22包括多个子层且多个所述子层的掺杂浓度不同,需要说明的是,引入所述子层的表述是为了更便于对所述外延层的结构特点进行更为准确的描述,并不代表在所述第二外延层22中存在明确的分层以及层与层之间的界线。所述第一外延层21是均匀分布的,即所述第一外延层21不同深度的掺杂浓度相同,所述第三外延层23的掺杂浓度逐渐减小。进一步地,在所述第二外延层22中,具有最高掺杂浓度的所述子层位于所述第二外延层22的上半部分且所述最高掺杂浓度大于所述第一外延层21的掺杂浓度。更进一步地,所述最高掺杂浓度大于或等于所述第三外延层23下表面的掺杂浓度,所述第三外延层23的掺杂浓度逐渐减小。
具体地,在图6所示实施例中,沿所述延伸方向,多个所述子层的掺杂浓度随所述第二外延层22的深度值的减小而增加,二者优选呈线性的一次函数关系。当所述深度减小至所述第二外延层22的顶端位置时达到掺杂浓度的最高值。所述第二外延层22的最顶端的参杂浓度与所述第三外延层23的最底端的掺杂浓度相同。
而在图7所示实施例中,沿所述延伸方向,在所述第二外延层22中,多个所述子层的掺杂浓度随所述第二外延层22的深度值的减小而增加,二者优选呈线性的一次函数关系。当所述深度减小至所述第二外延层22的上半部分中的特定深度位置时达到掺杂浓度的最高值,并继续随着深度的减小而保持所述最高值直至到达所述第二外延层22的顶部,即在所述第二外延层22的上半部分的特定深度以上位置的所述子层的参杂浓度固定为所述最高值。
进一步地,结合图1、图6以及图7,沿所述延伸方向,所述第一外延层21的上表面低于所述沟道3的底部,所述沟道3的底部位于所述第二外延层22的下半部分,所述第三外延层23的下表面低于所述栅极31的底部。
进一步地,图8、图9分别示出了本发明的具体实施方式的,另一种所述外延层结构中,掺杂浓度随外延层深度变化关系图。图8所示实施例的第一外延层21以及第三外延层23的设置与图9所示实施例中所述第一外延层21以及所述第三外延层23的设置相同。具体地,沿所述延伸方向,所述第二外延层22下表面的掺杂浓度大于所述第一外延层21上表面的参杂浓度,所述第二外延层22上表面的掺杂浓度大于所述第三外延层23下表面的掺杂浓度。其中,所述第一外延层21中的参杂剂是均匀分布的,所述第三外延层23的掺杂剂也是是均匀分布的。优选地,所述第一外延层21的掺杂浓度小于所述第三外延层23的掺杂浓度。更进一步的,如图8所示,所述第一外延层21、所述第二外延层22以及所述第三外延层23各自的掺杂浓度均为固定值,掺杂剂在所述第一外延层21、所述第二外延层22以及所述第三外延层23各自均匀分布。进一步地,所述第二外延层22的掺杂浓度大于所述第三外延层的掺杂浓度,所述第三外延层23的掺杂浓度大于所述第一外延层的掺杂浓度。而在图9所示实施例中,多个所述子层的掺杂浓度随所述第二外延层22的深度值的减小而增加,二者优选呈线性的一次函数关系。当所述深度减小至所述第二外延层22的顶端位置时达到掺杂浓度的最高值。
进一步地,结合图8至图10,在这样的实施例中,沿所述延伸方向,所述第一外延层21的上表面高于所述沟道3的底部,所述沟道3的底部位于所述第一外延层21内,所述第三外延层23的下表面低于所述栅极31的底部。通过这样的设置,所述沟道3的底部没有停留在所述第二外延层22,而是穿透所述第二外延层22,能够提高功率沟道MOSFET器件的耐压能力。
以上对本发明的具体实施例进行了描述。该发明的实施方式同理也适用于P沟道MOSFET。需要理解的是,本发明并不局限于上述特定实施方式,对于本领域技术人员可以在权利要求的范围内做出各种变形或修改,这并不影响本发明的实质内容。
Claims (13)
1.金属-氧化物沟道半导体场效应晶体管的外延层结构,其特征在于,所述外延层结构的掺杂浓度先逐渐增大然后再逐渐减小。
2.根据权利要求1所述的外延层结构,其特征在于,所述金属-氧化物半导体场效应晶体管设置有栅极、衬底和沟道,沿所述衬底指向所述栅极的方向定义为延伸方向,所述外延层结构的掺杂浓度沿所述延伸方向先逐渐增大然后再逐渐减小。
3.根据权利要求2所述的外延层结构,其特征在于,所述外延层结构沿所述延伸方向包括第一外延层、第二外延层和第三外延层,所述第一外延层和所述第三外延层的掺杂浓度均小于所述第二外延层的掺杂浓度的最大值。
4.根据权利要求3所述的外延层结构,其特征在于,沿所述延伸方向,所述第二外延层包括多个子层且多个所述子层的掺杂浓度不同,所述第一外延层是均匀分布的,第三外延层的掺杂浓度是均匀分布的,具有最高掺杂浓度的所述子层位于所述第二外延层的上半部分且所述最高掺杂浓度大于所述第一外延层和所述第三外延层的掺杂浓度。
5.根据权利要求4所述的外延层结构,其特征在于,沿所述延伸方向,多个所述子层的掺杂浓度按照如下方式分布:
-先逐渐增大然后再逐渐减小;
-逐渐增大至所述最高掺杂浓度然后再均匀分布;
-先逐渐增大至所述最高掺杂浓度然后再均匀分布,最后再逐渐减小。
6.根据权利要求4或5所述的外延层结构,其特征在于,沿所述延伸方向,所述第一外延层的上表面低于所述沟道的底部,所述沟道的底部位于所述第二外延层的下半部分,所述第三外延层的下表面高于所述栅极的底部。
7.根据权利要求3所述的外延层结构,其特征在于,沿所述延伸方向,所述第二外延层包括多个子层且多个所述子层的掺杂浓度不同,所述第一外延层是均匀分布的,所述第三外延层的掺杂浓度逐渐减小,具有最高掺杂浓度的所述子层位于所述第二外延层的上半部分,所述最高掺杂浓度大于所述第一外延层,所述最高掺杂浓度大于或等于所述第三外延层下表面的掺杂浓度,所述第三外延层的掺杂浓度逐渐减小。
8.根据权利要求7所述的外延层结构,其特征在于,沿所述延伸方向,多个所述子层的掺杂浓度按照如下方式分布:
-逐渐增大;
-逐渐增大至所述最高掺杂浓度然后再均匀分布。
9.根据权利要求1至8中任一项所述的外延层结构,其特征在于,沿所述延伸方向,所述第一外延层的上表面低于所述沟道的底部,所述沟道的底部位于所述第二外延层的下半部分,所述第三外延层的下表面低于所述栅极的底部。
10.根据权利要求3所述的外延层结构,其特征在于,沿所述延伸方向,所述第二外延层下表面的掺杂浓度大于所述第一外延层上表面的参杂浓度,所述第二外延层上表面的掺杂浓度大于所述第三外延层下表面的掺杂浓度,所述第一外延层是均匀分布的,第三外延层的掺杂浓度是均匀分布的。
11.根据权利要求10所述的外延层结构,其特征在于,沿所述延伸方向,所述第二外延层的掺杂浓度是均匀分布的或者是逐渐增大的。
12.根据权利要求10所述的外延层结构,其特征在于,所述第一外延层的掺杂浓度小于所述第三外延层的掺杂浓度。
13.根据权利要求10至12中任一项所述的外延层结构,其特征在于,沿所述延伸方向,所述第一外延层的上表面高于所述沟道的底部,所述沟道的底部位于所述第一外延层内,所述第三外延层的下表面低于所述栅极的底部。
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CN110676321A (zh) * | 2018-07-03 | 2020-01-10 | 无锡华润华晶微电子有限公司 | 沟槽mosfet及其制造方法 |
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