CN107466161A - A kind of method for hollowing out copper foil at differential pair via - Google Patents
A kind of method for hollowing out copper foil at differential pair via Download PDFInfo
- Publication number
- CN107466161A CN107466161A CN201710552597.4A CN201710552597A CN107466161A CN 107466161 A CN107466161 A CN 107466161A CN 201710552597 A CN201710552597 A CN 201710552597A CN 107466161 A CN107466161 A CN 107466161A
- Authority
- CN
- China
- Prior art keywords
- differential pair
- copper foil
- pair via
- vias
- hollowing out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0002—Apparatus or processes for manufacturing printed circuits for manufacturing artworks for printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
- H05K2201/0776—Resistance and impedance
- H05K2201/0784—Uniform resistance, i.e. equalizing the resistance of a number of conductors
Abstract
The present invention provides a kind of method for hollowing out copper foil at differential pair via, during PCB design, before deposited copper step, comprises the following steps：Step 1. sets the functional module for hollowing out copper foil at differential pair via；Step 2. is set in a menu hollows out at differential pair via copper foil options and corresponding with the functional module of step 1；Step 3. judges whether the differential pair via in need for hollowing out copper foil, if so, copper foil options at differential pair via is hollowed out in selection menu, into step 4；If nothing, into step 6；Step 4. selection needs to hollow out the differential pair via of copper foil；Step 5. forbids wiring area in aspect needed for selected differential pair via periphery addition automatically；Return to step 3；Step 6. terminates.The present invention can a key hollow out copper foil at differential pair via, improve Layout design efficiencies, reduce the manually operated workload of Layout engineer.
Description
Technical field
The invention belongs to PCB design field, and in particular to a kind of method for hollowing out copper foil at differential pair via.
Background technology
Server board is stuck in the PCB design phases, to ensure that the impedance before and after HW High Way via is consistent, in the design
Need to hollow out the copper foil at differential pair via.Generally need.The size of via copper ring is checked manually, added in the region of via composition
Add other aspects except differential pair cabling to forbid wiring area, cause that Layout engineer's workload is larger, and design efficiency is relatively low.
This is the deficiencies in the prior art, therefore, for drawbacks described above of the prior art, there is provided one kind hollows out differential pair mistake
The method of copper foil, is necessary at hole.
The content of the invention
It is an object of the present invention to it is big to hollow out copper foil workload at differential pair via manually for the above-mentioned PCB design phases
The defects of, there is provided a kind of method for hollowing out copper foil at differential pair via, to solve above-mentioned technical problem.
To achieve the above object, the present invention provides following technical scheme：
A kind of method for hollowing out copper foil at differential pair via, during PCB design, before deposited copper step, comprise the following steps：
Step 1. sets the functional module for hollowing out copper foil at differential pair via；
Step 2. is set in a menu hollows out at differential pair via copper foil options and corresponding with the functional module of step 1；
Step 3. judges whether the differential pair via in need for hollowing out copper foil,
If so, copper foil options at differential pair via is hollowed out in selection menu, into step 4；
If nothing, into step 6；
Step 4. selection needs to hollow out the differential pair via of copper foil；
Step 5. forbids wiring area in aspect needed for selected differential pair via periphery addition automatically；Return to step 3；
Step 6. terminates.
Further, step 1 setting hollows out the functional module of copper foil at differential pair via, comprises the following steps that：
Step 1-1. obtains the information of the differential pair via of selection automatically, and the information of the differential pair via includes differential pair via
Routing layer, in differential pair via in the copper ring race diameter dimension D of each via, differential pair via two vias central point
The common central point O of two vias in O1 and O2 and differential pair via；
Step 1-2. sets the first setpoint distance L；
Step 1-3. setting differential pair groups of vias region, the differential pair groups of vias region includes selected differential pair via and difference
It is divided to the region between two vias in via, and the region between two vias and the central point 01 of two vias and O2 company
Line is parallel；
Step 1-4. is since the common central point O of two vias of differential pair via, along the ragged edge of differential pair groups of vias
Shape stretches out the first setpoint distance L, and wiring area is forbidden in formation；
Step 1-5. enters step 2.
Further, the first setpoint distance L is 4mil.
Further, PCB design process is carried out in Allergo environment, and step 1 is set in Cadence Skill environment
Hollow out copper foil functional module at differential pair via.
Further, the required aspect in step 5 is other PCB layout layers in addition to differential pair routing layer.
The beneficial effects of the present invention are：
The present invention hollows out at differential pair via the functional module of copper foil and corresponding with menu item by setting, can a key hollow out
Copper foil at differential pair via, Layout design efficiencies are improved, reduce the manually operated workload of Layout engineer.
In addition, design principle of the present invention is reliable, and it is simple in construction, there is very extensive application prospect.
As can be seen here, the present invention is compared with prior art, with prominent substantive distinguishing features and significantly progressive, its implementation
Beneficial effect be also obvious.
Brief description of the drawings
Fig. 1 is flow chart of the method for the present invention；
Fig. 2 is the flow chart that setting hollows out the functional module of copper foil at differential pair via；
Fig. 3 is the differential signal line cabling schematic diagram for needing to hollow out copper foil at differential pair via of embodiment 1；
Fig. 4 is that the PCB layer for needing to hollow out copper foil at differential pair via of embodiment 1 folds schematic diagram；
Fig. 5 is schematic diagram of the differential pair via of embodiment 1 before required aspect hollows out copper foil；
Fig. 6 is schematic diagram of the differential pair via of embodiment 1 after required aspect hollows out copper foil；
Fig. 7 is the formation schematic diagram in the differential pair groups of vias region of embodiment 1；
Fig. 8 is to hollow out the option schematic diagram of copper foil at differential pair via in menu；
Wherein, 1. first differential pair positive signal via；2. the first differential pair negative signal via；O1. the first differential pair positive signal mistake
The center in hole；O2. the center of the first differential pair negative signal via；O. the first differential pair positive signal via 1 and the first differential pair are born
The common central point of 2 two vias of signal via.
Embodiment：
To enable the purpose of the present invention, feature, advantage more obvious and understandable, it is embodied below in conjunction with the present invention
Accompanying drawing in example, the technical scheme in the present invention is clearly and completely described.
As shown in figure 1, the present invention provides a kind of method for hollowing out copper foil at differential pair via, during PCB design, applying
Before copper step, comprise the following steps：
Step 1. sets the functional module for hollowing out copper foil at differential pair via；PCB design process is carried out in Allergo environment, step
Rapid 1 in Cadence Skill environment setting hollow out copper foil functional module at differential pair via；
As shown in Fig. 2 step 1 comprises the following steps that：
Step 1-1. obtains the information of the differential pair via of selection automatically, and the information of the differential pair via includes differential pair via
Routing layer, in differential pair via in the copper ring race diameter dimension D of each via, differential pair via two vias central point
The common central point O of two vias in O1 and O2 and differential pair via；
It is 4mil that step 1-2., which sets the first setpoint distance L, the first setpoint distance L,；
Step 1-3. setting differential pair groups of vias region, the differential pair groups of vias region includes selected differential pair via and difference
It is divided to the region between two vias in via, and the region between two vias and the central point 01 of two vias and O2 company
Line is parallel；
Step 1-4. is since the common central point O of two vias of differential pair via, along the ragged edge of differential pair groups of vias
Shape stretches out the first setpoint distance L, and wiring area is forbidden in formation；
Step 1-5. enters step 2；
Step 2. is set in a menu hollows out at differential pair via copper foil options and corresponding with the functional module of step 1；
Step 3. judges whether the differential pair via in need for hollowing out copper foil,
If so, copper foil options at differential pair via is hollowed out in selection menu, into step 4；
If nothing, into step 6；
Step 4. selection needs to hollow out the differential pair via of copper foil；
Step 5. forbids wiring area in aspect needed for selected differential pair via periphery addition automatically；Return to step 3；It is required
Aspect is other PCB layout layers in addition to differential pair routing layer；
Step 6. terminates.
Embodiment 1 is as shown in Figure 3, it is necessary to hollow out the first differential pair positive signal via 1 and the first differential pair negative signal via 2
The copper foil of other PCB layout layer correspondence positions outside differential pair routing layer；
As shown in figure 8, the menu selection item that selection hollows out copper foil at differential pair via " void for Diff via ", clicks need
The differential pair via of copper foil is hollowed out, the first differential pair positive signal via 1 is hollowed out and the first differential pair negative signal via 2 is in institute
Need the copper foil of aspect；
The automatic information for obtaining differential pair via；
The automatic routing layer for obtaining the first differential pair positive signal via 1 and the first differential pair negative signal via 2, as shown in figure 3, the
One differential pair positive signal and the first differential pair negative signal pass through the first differential pair positive signal via 1 and from top layer Top layer outlets
One differential pair negative signal via 2 changes layer to be terminated to bottom Bottom layers, cabling, as shown in the folded schematic diagram of Fig. 4 12 layers of PCB layer,
Other aspects needed in removing top layer Top layers, Bottom layers hollow out the first differential pair positive signal via 1 and the first differential pair is born
Copper foil at signal via 2, other aspects be GND1, Signal1, GND2, Signal2, GND/Power, GND/Power,
Signal3, GND3, Signal4 and GND4；
As shown in fig. 7, obtain the copper ring of the first differential pair positive signal via 1 and the first differential pair negative signal via 2 automatically in addition
Race diameter size, the central point O1 of the first differential pair positive signal via 1, the central point O2 of the first differential pair negative signal via 2
And first differential pair positive signal via 1 and the common central point O of first 2 two vias of differential pair negative signal via；
Set the first setpoint distance as L be 4mil；
The groups of vias region of the first differential pair positive signal via 1 and the first differential pair negative signal via 2 is set, as shown in fig. 7, mistake
Hole group region includes the first differential pair positive signal via 1, the first differential pair negative signal via 2 and the first differential pair positive signal via
1 and the first region between differential pair negative signal via 2, and the first differential pair positive signal via 1 and the first differential pair negative signal
Region and the central point O1 of the first differential pair positive signal via 1 and the center of the first differential pair negative signal via 2 between via 2
Point O2 line is parallel；
First differential pair positive signal via 1 and the first differential pair negative signal via 2 except top layer Top layers, Bottom layers other
Aspect hollow out copper foil before schematic diagram it is as shown in Figure 5；
As shown in fig. 7, opened from the common central point O of the first differential pair positive signal via 1 and the first differential pair negative signal via 2
Begin, stretch out the first setpoint distance 4mil along the ragged edge elliptical shape of differential pair groups of vias, wiring area is forbidden in formation；
First differential pair positive signal via 1 and the first differential pair negative signal via 2 except top layer Top layers, Bottom layers other
The schematic diagram hollowed out after copper foil of aspect is as shown in Figure 6.
Embodiments of the invention are illustrative and not restrictive, and above-described embodiment is only to aid in understanding the present invention, because
This is every by those skilled in the art's technique according to the invention the invention is not restricted to the embodiment described in embodiment
Other embodiments that scheme is drawn, also belong to the scope of protection of the invention sheet, and the scope for inventing application is not limited to
The PCB design phase of server board, it is every to need the PCB design phase for hollowing out copper foil at differential pair via to use this at other
The technical scheme of invention also belongs to protection scope of the present invention.
Claims (5)
- A kind of 1. method for hollowing out copper foil at differential pair via, it is characterised in that during PCB design, before deposited copper step, Comprise the following steps：Step 1. sets the functional module for hollowing out copper foil at differential pair via；Step 2. is set in a menu hollows out at differential pair via copper foil options and corresponding with the functional module of step 1；Step 3. judges whether the differential pair via in need for hollowing out copper foil,If so, copper foil options at differential pair via is hollowed out in selection menu, into step 4；If nothing, into step 6；Step 4. selection needs to hollow out the differential pair via of copper foil；Step 5. forbids wiring area in aspect needed for selected differential pair via periphery addition automatically；Return to step 3；Step 6. terminates.
- 2. a kind of method for hollowing out copper foil at differential pair via as claimed in claim 1, it is characterised in that step 1 setting is dug The functional module of copper foil, is comprised the following steps that at empty differential pair via：Step 1-1. obtains the information of the differential pair via of selection automatically, and the information of the differential pair via includes differential pair via Routing layer, in differential pair via in the copper ring race diameter dimension D of each via, differential pair via two vias central point The common central point O of two vias in O1 and O2 and differential pair via；Step 1-2. sets the first setpoint distance L；Step 1-3. setting differential pair groups of vias region, the differential pair groups of vias region includes selected differential pair via and difference It is divided to the region between two vias in via, and the region between two vias and the central point 01 of two vias and O2 company Line is parallel；Step 1-4. is since the common central point O of two vias of differential pair via, along the ragged edge of differential pair groups of vias Shape stretches out the first setpoint distance L, and wiring area is forbidden in formation；Step 1-5. enters step 2.
- A kind of 3. method for hollowing out copper foil at differential pair via as claimed in claim 2, it is characterised in that first setting Distance L is 4mil.
- A kind of 4. method for hollowing out copper foil at differential pair via as claimed in claim 1, it is characterised in that PCB design process Carried out in Allergo environment, step 1 sets in Cadence Skill environment and hollows out copper foil functional module at differential pair via.
- A kind of 5. method for hollowing out copper foil at differential pair via as claimed in claim 1, it is characterised in that the institute in step 5 Aspect is needed as other PCB layout layers in addition to differential pair routing layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710552597.4A CN107466161A (en) | 2017-07-07 | 2017-07-07 | A kind of method for hollowing out copper foil at differential pair via |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710552597.4A CN107466161A (en) | 2017-07-07 | 2017-07-07 | A kind of method for hollowing out copper foil at differential pair via |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107466161A true CN107466161A (en) | 2017-12-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710552597.4A Pending CN107466161A (en) | 2017-07-07 | 2017-07-07 | A kind of method for hollowing out copper foil at differential pair via |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107944197A (en) * | 2017-12-20 | 2018-04-20 | 郑州云海信息技术有限公司 | The processing method of back drill safe distance at a kind of differential pair via based on Cadence skill |
| CN108260297A (en) * | 2017-12-29 | 2018-07-06 | 深圳市兴森快捷电路科技股份有限公司 | A kind of method and system for improving point glue surface Chip patch yields |
| CN108882513A (en) * | 2018-08-30 | 2018-11-23 | 郑州云海信息技术有限公司 | A kind of dig a hole method, apparatus and system for keeping away line automatically |
| CN109815570A (en) * | 2019-01-15 | 2019-05-28 | 郑州云海信息技术有限公司 | A method of it checks and whether there is cabling between differential signal via hole |
| CN109977602A (en) * | 2019-04-10 | 2019-07-05 | 苏州浪潮智能科技有限公司 | A kind of method for hollowing and equipment of copper sheet |
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| US7797663B2 (en) * | 2007-04-04 | 2010-09-14 | Cisco Technology, Inc. | Conductive dome probes for measuring system level multi-GHZ signals |
| US20100257504A1 (en) * | 2009-04-07 | 2010-10-07 | Hon Hai Precision Industry Co., Ltd. | Automatic system and method for providing pcb layout |
| CN103761100A (en) * | 2014-01-24 | 2014-04-30 | 浪潮(北京)电子信息产业有限公司 | Method and system for quickly drawing wiring prohibition areas around differential-signal via holes |
| CN103793575A (en) * | 2014-02-19 | 2014-05-14 | 浪潮(北京)电子信息产业有限公司 | Method and device for arranging passing holes in single plate |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7797663B2 (en) * | 2007-04-04 | 2010-09-14 | Cisco Technology, Inc. | Conductive dome probes for measuring system level multi-GHZ signals |
| US20100257504A1 (en) * | 2009-04-07 | 2010-10-07 | Hon Hai Precision Industry Co., Ltd. | Automatic system and method for providing pcb layout |
| CN103761100A (en) * | 2014-01-24 | 2014-04-30 | 浪潮(北京)电子信息产业有限公司 | Method and system for quickly drawing wiring prohibition areas around differential-signal via holes |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107944197A (en) * | 2017-12-20 | 2018-04-20 | 郑州云海信息技术有限公司 | The processing method of back drill safe distance at a kind of differential pair via based on Cadence skill |
| CN108260297A (en) * | 2017-12-29 | 2018-07-06 | 深圳市兴森快捷电路科技股份有限公司 | A kind of method and system for improving point glue surface Chip patch yields |
| CN108882513A (en) * | 2018-08-30 | 2018-11-23 | 郑州云海信息技术有限公司 | A kind of dig a hole method, apparatus and system for keeping away line automatically |
| CN108882513B (en) * | 2018-08-30 | 2021-09-17 | 郑州云海信息技术有限公司 | Automatic line avoiding digging method, device and system |
| CN109815570A (en) * | 2019-01-15 | 2019-05-28 | 郑州云海信息技术有限公司 | A method of it checks and whether there is cabling between differential signal via hole |
| CN109815570B (en) * | 2019-01-15 | 2022-02-22 | 郑州云海信息技术有限公司 | Method for checking whether wiring exists between differential signal via holes |
| CN109977602A (en) * | 2019-04-10 | 2019-07-05 | 苏州浪潮智能科技有限公司 | A kind of method for hollowing and equipment of copper sheet |
| CN109977602B (en) * | 2019-04-10 | 2022-08-19 | 苏州浪潮智能科技有限公司 | Copper sheet hollowing method and equipment |
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Application publication date: 20171212 |