CN107464834A - 功率半导体器件及其制造方法 - Google Patents

功率半导体器件及其制造方法 Download PDF

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CN107464834A
CN107464834A CN201710413790.XA CN201710413790A CN107464834A CN 107464834 A CN107464834 A CN 107464834A CN 201710413790 A CN201710413790 A CN 201710413790A CN 107464834 A CN107464834 A CN 107464834A
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power semiconductor
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CN107464834B (zh
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金莹俊
禹赫
金台烨
赵汉信
朴泰泳
李珠焕
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Hyundai Mobis Co Ltd
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Hyundai Autron Co Ltd
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Abstract

一种功率半导体器件及其制造方法，包括：栅电极，配置于基板的沟道内；第一导电型的主体区和第二导电型的源区，第一导电型的主体区在基板内配置于栅电极的一侧，第二导电型的源区在第一导电型的主体区内与栅电极相邻配置；第一导电型的浮动区，在基板内配置于栅电极的另一侧；第一导电型的边缘掺杂区，在基板内与第一导电型的浮动区分离配置并与源区电连接；第二导电型的边缘结隔离区，在基板内配置于第一导电型的浮动区与第一导电型的边缘掺杂区之间；以及第二导电型的漂移区，在基板内配置于第一导电型的浮动区、第一导电型的边缘掺杂区以及第二导电型的边缘结隔离区下方，边缘结隔离区的第二导电型掺杂浓度比漂移区的第二导电型掺杂浓度高。

Description

功率半导体器件及其制造方法
技术领域
本发明涉及一种功率半导体器件及其制造方法，更加详细地，涉及一种绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)器件及其制造方法。
背景技术
绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)是MOS(MetalOxide Silicon：金氧硅)和双极技术的结晶体，具有低正向损耗和高速的特征，以基于闸流晶体管、双极晶体管、MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor，场效应管)等无法实现的领域中的用途为对象逐渐扩大其应用，是广泛应用在300V以上的电压区域的高效率且高速的电力系统中必须要使用的新一代功率半导体器件。在1970年代开发出电力用MOSFET之后，作为切换器件，在要求高速切换的范围内使用MOSFET，在中压至高压中要求大量的电流传导的范围内使用双极晶体管、闸流晶体管、GTO等。1980年代初期开发的IGBT在输出特性方面具有超过双极晶体管的电流能力，在输入特性方面具有如MOSFET那样的栅极驱动特性，因此可以实现约100KHz左右的高速切换。由此，IGBT不仅可以用作MOSFET、双极晶体管、闸流晶体管的代替器件，还造就出新的应用系统，因此，除了工业领域之外，其使用范围还逐渐扩大到家用电器。
相关的现有技术有韩国公开公报第20140057630号(2014.05.13公开，发明名称：IGBT及其制造方法)。
发明内容
要解决的技术问题
本发明的目的在于提供一种在切换IGBT的状态下，能够全力防止由于空穴电流而导致动态内压下降，确保稳健性和空间效率性的半导体器件及其制造方法。但是，这些技术问题只是例示性的，本发明的范围并不限定于此。
解决技术问题的手段
提供一种用于解决上述技术问题的本发明一方面的功率半导体器件。上述功率半导体器件包括：栅电极，配置于基板的沟道内；第一导电型的主体区和第二导电型的源区，所述第一导电型的主体区在所述基板内配置于所述栅电极的一侧，所述第二导电型的源区在所述第一导电型的主体区内与所述栅电极相邻配置；第一导电型的浮动区，在所述基板内配置于所述栅电极的另一侧；第一导电型的边缘掺杂区，在所述基板内与所述第一导电型的浮动区分离配置，并与所述源区电连接；第二导电型的边缘结隔离区(edge junctionisolation)，在所述基板内配置于所述第一导电型的浮动区与所述第一导电型的边缘掺杂区之间；以及第二导电型的漂移区，在所述基板内配置于所述第一导电型的浮动区、所述第一导电型的边缘掺杂区以及所述第二导电型的边缘结隔离区下方，所述边缘结隔离区的第二导电型掺杂浓度比所述漂移区的第二导电型掺杂浓度相对更高。
可以是，在所述功率半导体器件中，所述第一导电型的边缘掺杂区配置于器件的边缘末端(edge termination)区域。
可以是，所述功率半导体器件还包括布线图案，所述布线图案配置在所述基板上，以便电连接所述源区和所述第一导电型的边缘掺杂区。
可以是，在所述功率半导体器件中，所述第一导电型的浮动区包围所述栅电极的底面和至少另一侧面，所述第一导电型的浮动区的最大掺杂深度比所述沟道的深度更深，所述第一导电型的边缘掺杂区的最大掺杂深度比所述沟道的深度更深。
可以是，在所述功率半导体器件中，在所述基板的上表面，经由所述第一导电型的浮动区与所述第一导电型的边缘掺杂区之间并在朝向所述基板的下表面方向垂直分布的电场中，最大电场所在深度比所述沟道的深度更深。
可以是，在所述功率半导体器件中，所述基板包括晶片以及在所述晶片上生长的外延层，所述第一导电型的浮动区的下部以及第一导电型的边缘掺杂区的下部包含所述晶片与所述外延层的边界面。
可以是，在所述功率半导体器件中，所述第二导电型以及所述第一导电型具有彼此相反的导电型，分别是n型和p型中的任意一个。
提供一种用于解决上述技术问题的本发明另一方面的功率半导体器件的制造方法。所述功率半导体器件的制造方法包括：向晶片上的第一区域和第二区域注入第一导电型杂质，向所述晶片的位于所述第一区域和所述第二区域之间的第三区域注入比所述晶片中包含的第二导电型掺杂浓度更高浓度的第二导电型杂质的步骤；在所述晶片上形成外延层，从而形成包括所述晶片和所述外延层的基板的步骤；扩散所述杂质，从而在对应于所述第一区域的所述基板上形成第一导电型的浮动区，在对应于所述第二区域的所述基板上形成第一导电型的边缘掺杂区，在对应于所述第三区域的所述基板上形成第二导电型的边缘结隔离区的步骤；向所述外延层注入杂质并扩散，从而形成第二导电型的源区的步骤；以及形成将所述源区和所述边缘掺杂区电连接的布线图案的步骤。
可以是，在所述功率半导体器件的制造方法中，所述第一导电型的浮动区的下部和第一导电型的边缘掺杂区的下部包含所述晶片与所述外延层的边界面。
发明的效果
根据如上所述实现本发明的一实施例，可以使用通过利用电荷共享(chargesharing)效果的连结，从而实现能够确保稳健性以及空间效率性的功率半导体器件。但是，本发明的范围并不限定于这些效果。
附图说明
图1是示出本发明的一实施例的功率半导体器件结构的截面图。
图2是示出在图1所示的本发明的一实施例的功率半导体器件中C方向的电场大小的曲线图。
图3是示出本发明的一实施例的功率半导体器件的局部结构的截面图。
图4a至图4f是示出本发明的一实施例的功率半导体器件的制造方法的截面图。
附图标记说明
1：基板；10：漂移区；20：沟道；30a、30b：浮动区；30c：边缘掺杂区；42：主体区；44：源区；50：栅电极；70：边缘结隔离区。
具体实施方式
以下，参照附图详细说明本发明的实施例。但是，本发明并不限定于下面说明的实施例，而是可以通过互不同的各种方式实现，以下的实施例是为了向具有通常知识的技术人员完整地告知发明范围而提供的，以便完整的公开本发明。并且，为了便于说明，在附图中至少一部分构成元素的尺寸有可能被夸大或缩小。在附图中相同的标记表示相同的元素。
在本说明书中，第一导电型以及第二导电型具有彼此相反的导电型，分别可以是n型和p型中的任意一个。例如，可以是第一导电型是p型，第二导电型是n型，在附图中，作为一种示例，假设这样的导电型结构。但是，本发明的技术构思并不限定于此，例如还可以是第一导电型是n型，第二导电型是p型。
图1是示出本发明的一实施例的功率半导体器件结构的截面图，图2是示出在图1所示的本发明的一实施例的功率半导体器件中C方向的电场大小的曲线图。
参照图1，本发明的一实施例的功率半导体器件包括配置于基板1的沟道20内的栅电极50。其中，基板1可以理解为包括晶片和在晶片上外延生长的外延层。并且，本功率半导体器件包括：第一导电型的主体区42，在基板1内配置于栅电极50的一侧；以及第二导电型的源区44，在第一导电型的主体区42内与栅电极50相邻配置。
本发明的一实施例的功率半导体器件包括：第一导电型的浮动区30b，在基板1内配置于栅电极50的另一侧；第一导电型的边缘掺杂区30c，在基板1内与第一导电型的浮动区30b分离配置，并与源区44电连接；以及第二导电型的边缘结隔离(edge junctionisolation)区70，在基板1内配置于第一导电型的浮动区30b与第一导电型的边缘掺杂区30c之间。
而且，本发明的一实施例的功率半导体器件包括第二导电型的漂移区10，所述第二导电型的漂移区10在基板1内配置于第一导电型的浮动区30b、第一导电型的边缘掺杂区30c以及第二导电型的边缘结隔离区70的下方，边缘结隔离区70的第二导电型掺杂浓度N2比漂移区10的第二导电型掺杂浓度N3相对更高。
第一导电型的边缘掺杂区30c配置在功率半导体器件的边缘末端(edgetermination)区域Z2。第一导电型的边缘掺杂区30c通过配置在基板1上的布线图案68与源区44电连接。因此，边缘掺杂区30c保持为源电势(source potential)。虽然附图中未示出，但是，在边缘掺杂区30c和基板1的外缘之间设有场板(field plate)、沟道截断环(channelstopper)等边缘结构体(edge structure)。
在基板1的上部形成与栅电极50电连接的布线图案64以及与源区44和主体区42电连接的布线图案68。布线图案64、68起到电极或接触器的作用，通过加入绝缘图案62、66来实现电绝缘。另一方面，在基板1的下部配置有集电极76，虽然附图中未示出，但是，在形成集电极76之前，可以先形成第二导电型的缓冲层(buffer layer)和/或者第一导电型的集电极层。
根据图1示出的C方向的结构，P型连结的浮动区30b和边缘掺杂区30c通过N型连结来隔离(isolation)。并且，边缘结隔离区70的第二导电型掺杂浓度N2与漂移区10的第二导电型掺杂浓度N3相比相对更高。根据这样的结构，可以在第一导电型的浮动区30b和边缘掺杂区30c的垂直方向、厚度的中心深度的更下方，例如B区域C1，形成最大电场。还可以进行调节电荷量平衡(charge balance)，以使最大电场下降到浮动区30b和边缘掺杂区30c的底面C2。
在通常的功率半导体器件中，在A区域中形成最大电场，但是，在具有该结构的功率半导体器件中，在B区域中形成最大电场，因此能够改善隔离区域的内压因切换状态的空穴注入带来的电场动态变化而下降的现象。即，现有的隔离结构在切换IGBT的时，动态内压因空穴电流而下降，相反，本发明的隔离结构可使用基于电荷共享(charge sharing)效果的连结，能够实现确保稳健性和空间效率性的有益效果。
当施加电压时，在N型损耗(depletion)下，若将静止状态的电场和电荷量的关系简化为C方向的一维，则dE/dx＝(1/ε)*n，可以视为仅掺杂N的函数，但是，当IGBT动作时，若注入载体，则受到所注入的电荷量的影响，变成dE/dx＝(1/ε)*(n+h-e)，在C区间，没有通过MOS的电子注入，由h(空穴浓度)带来电场变化率的增加。在一般的结构中，由于空穴浓度变化带来的电场变化率的增加，导致在同样的最大电场中电场面积减少，内压急剧降低，但是，在本结构中，在A、B之间形成电场变化率为负的区间，当电场的倾斜度增加时，加大电场的面积，从而缓解动态内压下降。根据上述的本发明的技术构思，在高电压的切换中，能够防止由于电流流动而导致隔离(isolation)区间的动态内压下降，能够实现可提升IGBT稳健性的功率半导体器件。
图3是示出本发明的一实施例的功率半导体器件的局部结构的截面图，对应于图1的结构中配置在边缘结隔离区70的左侧的结构。
参照图3，在基板1内具备分别配置于彼此分离的第一沟道20a以及第二沟道20b的一对栅电极50a、50b。其中，基板1可以理解为包括晶片和在晶片上外延生长的外延层。并且，功率半导体器件100包括：第一导电型的主体区42，在基板1内配置于第一沟道20a和第二沟道20b之间；一对第二导电型的源区44a、44b，在第一导电型的主体区42内分别与第一沟道20a和第二沟道20b相邻，并彼此分离配置；第一导电型的浮动区30a，在基板1内分别包围第一沟道20a的底面和至少另一侧面；以及第一导电型的浮动区30b，分别包围第一沟道20b的底面和至少另一侧面，一对第一导电型的浮动区30a、30b在基板1内彼此分离配置。以基板1的上表面1s为基准，到浮动区30a、30b底面的深度比到第一沟道20a以及第二沟道20b的底面的深度更深。即，第一导电型的浮动区30a、30b的最大掺杂深度可以比第一沟道20a以及第二沟道20b的深度更深。
本发明的一实施例的功率半导体器件100包括第二导电型的漂移区10，所述第二导电型的漂移区10在基板1内从一对第一导电型的浮动区30a、30b的下方12开始经由一对第一导电型的浮动区30a、30b之间14，延续到第一导电型的主体区42。尤其是，在漂移区10中，一对第一导电型的浮动区30a、30b之间的第二导电型掺杂浓度N1比一对第一导电型的浮动区30a、30b下方的第二导电型掺杂浓度N3相对更高。
另一方面，第一导电型的主体区42的最大掺杂深度可以比第一沟道20a以及第二沟道20b的深度更浅，第一导电型的浮动区30a、30b的最大掺杂深度可以比第一沟道20a以及第二沟道20b的深度更深。其中，在漂移区10中，一对第一导电型的浮动区30a、30b之间以及第一沟道20a与第二沟道20b之间的第二导电型掺杂浓度与一对第一导电型的浮动区30a、30b下方的第二导电型掺杂浓度相比相对更高。
与上述说明的本发明的一实施例的功率半导体器件100相比，当浮动区30a、30b未形成到沟道20a、20b的底面时，在沟道20a、20b底面出现电场增大的问题，而当浮动区30a、30b仅形成到沟道20a、20b底面的情形时，当在供给IGBT的基本电流的G方向的MOSFET中缩小沟道20a、20b的分离距离时，由于第一导电型杂质的扩散，基本电流的路径受到限制，出现无法将单元间距缩小到一定距离以下的问题。
分布在一对第一导电型浮动区30a、30b之间14的第二导电型掺杂浓度N1比分布在第一导电型浮动区30a、30b下方12的第二导电型掺杂浓度N3相对更高，因此即使沟道20a、20b之间的间隔距离变窄，也可以形成基本电流供给路径，供给充足的基本电流，形成N1和P1的平衡(Balance)，以便在浮动区30a、30b的下部形成最大电场，加强稳健性。
即，当在供给IGBT的基本电流的G方向的MOSFET中缩小沟道之间的间隔距离F时，可以通过形成N1区域，从而来改善浮动区30a、30b的第一导电型杂质扩散而限制基本电流路径的现象。并且，根据本发明的一实施例的功率半导体器件100的结构，假设跨导相同时，以更窄的间隔距离F形成高单元密度，在总电流相同下，能够降低G区间的电流密度，缓解局部温度上升，改善短路特性。
基于这样的原理在改善IGBT电阻和短路特性的同时，调节区域14的第二导电型杂质浓度N1和浮动区30a、30b的第一导电型杂质浓度P1的电荷总量，使得最大电场形成在浮动区30a、30b的下部，从而能够提高稳健性。其中，形成有最大电场G1的下部与沟道20a、20b底面相比更低。另一方面，在变形的实施例中，形成最大电场G2的区域也可以具有与浮动区30a、30b的底面相同的高度。
在施加电压时，在N型损耗(depletion)下，若将静止状态的电场和电荷量的关系简化为一维，则dE/dx＝(1/ε)*n，可以视为仅掺杂N的函数，但是，IGBT动作时，若注入载体，则受到所注入的电荷量的影响，变成dE/dx＝(1/ε)*(n+h-e)，在关闭状态下，当G区间的空穴密度处于过剩状态时，在一般的结构中，由于空穴浓度的变化带来的电场变化率的增加，在相同的最大电场中电场面积减少，从而内压急剧降低，但是，在本发明的结构中，在沟道20a、20b的底面与主体区42的底面之间形成电场变化率为负的区间，在电场的倾斜度增加时，可加大电场的面积，从而缓解动态内压下降。
图4a至图4f是示出本发明的一实施例的功率半导体器件的制造方法的截面图。
参照图4a，向晶片A上的第一区域I和第二区域II注入第一导电型杂质，向位于所述晶片A的第一区域I与第二区域II之间的第三区域III和第四区域IV，注入比包含在所述晶片A中的第二导电型掺杂浓度更高浓度的第二导电型杂质。选择性地区分第一区域I至第四区域IV中的、所选定的至少一部分区域，并可以分成步骤依次执行或同时执行这样的杂质注入工序。图4a示出的P1区域、N1区域、N2区域、P2区域分别对应于图1示出的浮动区30a和30b、浮动区30a和30b之间的漂移区14、边缘结隔离区70、边缘掺杂区30c的一部分。
参照图4b，在晶片A上形成外延层B，从而形成包括晶片A和外延层B的基板1。在外延层B生长之后，还可以执行通过外延层B的上表面进一步注入杂质的掺杂工序。
参照图4c，去除外延层B的一部分，可以在包括第一区域I以及第四区域IV的边界的区域分别形成彼此分离的第一沟道20a以及第二沟道20b。
参照图4d，在注入有第一导电型以及第二导电型的杂质的状态下，通过热处理等扩散工序，在对应于第一区域I的基板1上形成第一导电型的浮动区30a、30b，在对应于第二区域II的基板1上形成第一导电型的边缘掺杂区30c，在对应于第三区域III的基板1上形成第二导电型的边缘结隔离区70。此时，第一导电型的浮动区30a、30b和边缘掺杂区30c的下部可以包括晶片A和外延层B的边界面F。
参照图4e，在第一沟道20a以及第二沟道20b之间的区域注入杂质，可以形成第一导电型的主体区42和一对第二导电型的源区44，所述一对第二导电型的源区44在第一导电型的主体区42内分别与第一沟道20a和第二沟道20b相邻且彼此分离配置。接着，利用绝缘膜对第一沟道20a和第二沟道20b的内壁进行衬垫，填充(filling)栅电极物质，从而可以形成栅电极50a。
参照图4f，可以形成将源区44和边缘掺杂区30c电连接的布线图案68。
在通过包括这样的步骤的制造方法来实现本发明的一实施例的功率半导体器件中，在边缘结隔离区70中形成最大电场的位置可以是包括晶片A和外延层B的边界面F的第一导电型的浮动区30b和边缘掺杂区30c的下部。
参照附图中示出的实施例来说明了本发明，但是，这些只是例示性的，对于所属领域中具有通常知识的技术人员而言，可以由此得到各种变形及等同的其他实施例。因此，本发明的真正的保护范围应该基于权利要求书的技术构思来限定。

Claims (9)

1.一种功率半导体器件，其特征在于，包括：
栅电极，配置于基板的沟道内；
第一导电型的主体区和第二导电型的源区，所述第一导电型的主体区在所述基板内配置于所述栅电极的一侧，所述第二导电型的源区在所述第一导电型的主体区内与所述栅电极相邻配置；
第一导电型的浮动区，在所述基板内配置于所述栅电极的另一侧；
第一导电型的边缘掺杂区，在所述基板内与所述第一导电型的浮动区分离配置，并与所述源区电连接；
第二导电型的边缘结隔离区，在所述基板内配置于所述第一导电型的浮动区与所述第一导电型的边缘掺杂区之间；以及
第二导电型的漂移区，在所述基板内配置于所述第一导电型的浮动区、所述第一导电型的边缘掺杂区以及所述第二导电型的边缘结隔离区下方，
所述边缘结隔离区的第二导电型掺杂浓度比所述漂移区的第二导电型掺杂浓度相对更高。
2.根据权利要求1所述的功率半导体器件，其特征在于，
所述第一导电型的边缘掺杂区配置于器件的边缘末端区域。
3.根据权利要求1所述的功率半导体器件，其特征在于，
所述功率半导体器件还包括布线图案，所述布线图案配置在所述基板上，以便电连接所述源区和所述第一导电型的边缘掺杂区。
4.根据权利要求1所述的功率半导体器件，其特征在于，
所述第一导电型的浮动区包围所述栅电极的底面和至少另一侧面，所述第一导电型的浮动区的最大掺杂深度比所述沟道的深度更深，所述第一导电型的边缘掺杂区的最大掺杂深度比所述沟道的深度更深。
5.根据权利要求4所述的功率半导体器件，其特征在于，
在所述基板的上表面，经由所述第一导电型的浮动区与所述第一导电型的边缘掺杂区之间并在朝向所述基板的下表面方向垂直分布的电场中，最大电场所在深度比所述沟道的深度更深。
6.根据权利要求1所述的功率半导体器件，其特征在于，
所述基板包括晶片以及在所述晶片上生长的外延层，所述第一导电型的浮动区的下部以及第一导电型的边缘掺杂区的下部包含所述晶片与所述外延层的边界面。
7.根据权利要求1至6中任一项所述的功率半导体器件，其特征在于，
所述第二导电型以及所述第一导电型具有彼此相反的导电型，分别是n型和p型中的任意一个。
8.一种功率半导体器件的制造方法，其特征在于，包括：
向晶片上的第一区域和第二区域注入第一导电型杂质，向所述晶片的位于所述第一区域和所述第二区域之间的第三区域注入比所述晶片中包含的第二导电型掺杂浓度更高浓度的第二导电型杂质的步骤；
在所述晶片上形成外延层，从而形成包括所述晶片和所述外延层的基板的步骤；
扩散所述杂质，从而在对应于所述第一区域的所述基板上形成第一导电型的浮动区，在对应于所述第二区域的所述基板上形成第一导电型的边缘掺杂区，在对应于所述第三区域的所述基板上形成第二导电型的边缘结隔离区的步骤；
向所述外延层注入杂质并扩散，从而形成第二导电型的源区的步骤；以及
形成将所述源区和所述边缘掺杂区电连接的布线图案的步骤。
9.根据权利要求8所述的功率半导体器件的制造方法，其特征在于，
所述第一导电型的浮动区的下部和第一导电型的边缘掺杂区的下部包含所述晶片与所述外延层的边界面。
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