CN107408534A - 具有集成无源组件的开关式功率级 - Google Patents

具有集成无源组件的开关式功率级 Download PDF

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Publication number
CN107408534A
CN107408534A CN201680014046.6A CN201680014046A CN107408534A CN 107408534 A CN107408534 A CN 107408534A CN 201680014046 A CN201680014046 A CN 201680014046A CN 107408534 A CN107408534 A CN 107408534A
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China
Prior art keywords
inductor
chip
phase
switch
pair
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Granted
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CN201680014046.6A
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CN107408534B (zh
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塔纳·朵思路欧格鲁
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Chaoyang Semiconductor Technology Jiangyin Co ltd
Enran intellectual property Holding Co.,Ltd.
Enran Technology (Hongkong) Co.,Ltd.
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En All Ran Technology
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

可缩放开关式调节器架构具有集成电感器。在一些实施例中，所述开关式调节器的开关的面积及电流驱动能力与构建于所述开关上方的面积内的电感器匹配。在一些实施例中，组合式开关与电感器被构造为单位单元且可经组合以视需要形成较大元件而用于较高电流驱动能力及多相操作。

Description

具有集成无源组件的开关式功率级
背景技术
本发明大体来说涉及用于调节半导体电路的功率的开关式调节器，且更特定来说涉及用于开关式调节器的集成电感器。
各种移动装置中所使用的典型单芯片系统(SoC)中的功率分布网络包含经由微凸块或铜柱连接到封装衬底的芯片上金属化层。通常在封装内使用一或多个重新分布层(RDL)来将来自或去往微凸块或铜柱的信号路由到所述封装的球，所述封装连接到印刷电路(PCB)。此可产生显著寄生电感，所述寄生电感可是这些装置的性能的显著限制因素，这是因为较高频率及较高电流会由于负载电流的快速改变而产生也被称为衰减的本地瞬时效应。
嵌入式电压调节器(eVR)(通常是具有电感器的开关式调节器)的使用可用于减小或解释由寄生电感带来的变化。然而，以小的形状因子(每平方毫米的额定电流)为具有高电感比电阻值(L/R：电感[nH]/每电阻[mohms])的eVR实施方案提供电感器可颇具挑战性。
发明内容
本发明的一些方面涉及具有集成电感器的可缩放开关式调节器架构及/或涉及依靠提供电感器的结构的面积而将各种性能参数优化的方法。优选地，开关式调节器的开关的面积及电流驱动能力与可构建于所述开关上方的相同面积内的电感器匹配。在一些实施例中，组合式开关与电感器被构造为单位单元且可经组合以视需要形成较大元件而用于较高电流驱动能力及多相操作。
本发明的一个方面涉及一种集成芯片封装，所述集成芯片封装包括：倒装芯片类型的集成电路(IC)芯片，其包含单芯片系统(SoC)及开关式电压调节器，所述开关式电压调节器包含串联耦合于较高电压电平连接与较低电压电平连接之间的至少第一开关及第二开关；多层衬底，其具有腔，在所述腔中具有至少一个电感器，所述至少一个电感器具有散置着铁氧体材料的多个上部迹线层，所述电感器包含第一端及第二端；及多个微凸块，其将所述IC芯片连接到所述衬底，包含将所述第一开关与所述第二开关之间的节点连接到所述电感器的所述第一端的微凸块。
本发明的另一方面涉及一种倒装芯片封装，所述倒装芯片封装包括：倒装芯片类型的集成电路(IC)芯片，其包含单芯片系统(SoC)及多相电压调节器，所述多相电压调节器包含串联耦合的第一对晶体管及串联耦合的第二对晶体管；及多层封装衬底，其具有多个重新分布层以及第一电感器及第二电感器，所述第一电感器及所述第二电感器由多个电镀迹线形成，所述第一电感器及所述第二电感器中的每一者包含第一端及第二端，所述多个电镀迹线由所述多层封装衬底的腔内的导电层形成，铁氧体材料在所述导电层中的至少一些导电层之间，且其中第一多个电镀迹线中的至少一者经配置以将所述第一电感器的所述第二端连接到所述第二电感器的所述第一端；及多个凸块，其经配置以在多个节点处将所述IC芯片连接到所述多层封装衬底，所述多个节点包含供应节点、接地节点、负载输出节点及电感器节点，所述负载输出节点包含所述第一电感器的所述第二端与所述第二电感器的所述第一端之间的连接，所述电感器节点包含：经配置以将所述第一对晶体管之间的节点连接到第一电感器结构的所述第一端的节点；及经配置以将所述第二对晶体管之间的节点连接到第二电感器结构的所述第二端的节点。
在查阅本发明之后可立刻理解本发明的这些及其它方面。
附图说明
图1是展示根据本发明的方面的多层封装衬底上的单芯片系统(SoC)的部分横截面图。
图2出于阐释目的展示图1的eVR的开关的样本布局以及实例性单相开关式调节器的部分电路图。
图3提供根据本发明的方面的电感器结构的三维图与附属横截面。
图4展示根据本发明的方面的四相实施方案的三维图。
图5展示图4的电感器的横截面以及磁场方向。
图6是利用图4的电感器的四相开关式调节器的部分电路图。
图7展示根据本发明的方面的8相实施方案的电感器结构的横截面。
图8图解说明可用于形成根据本发明的方面的电感器结构的步骤。
图9是多层封装的俯视图，其展示用于2相电感器阵列的第一腔及用于4相电感器阵列的第二腔。
图10展示图9的多层封装的构造的第一横截面及第二横截面。
图11展示根据本发明的一些方面的封装的横截面，所述横截面图解说明用于产生具有凸块的铜表面的过程步骤。
具体实施方式
图1是展示根据本发明的方面的多层封装衬底113上的单芯片系统(SoC)111的部分横截面图。SoC通过微凸块115耦合到多层封装的第一侧，其中多层封装的第二相对侧具有用于耦合到印刷电路板(PCB)(未展示)的球117。
SoC是通常包含用于执行操作的各种电路的半导体装置，举例来说，在各种实施例中包含一或多个处理器核心且在SoC 111的情形中包含嵌入式电压调节器(eVR)。举例来说，eVR可是开关式调节器且开关式调节器可包含开关，所述开关用于将电感器的一侧交替地耦合到较高电压电平及较低电压电平，其中电感器的另一侧提供电压输出节点(Vout)，所述电压输出节点将经调节功率提供到eVR的功率域。
多层封装包含重新分布层(RDL)，所述重新分布层包含耦合RDL的各个部分及/或微凸块与球的金属化迹线及导通孔。RDL及导通孔用于在封装内对信号进行路由。多层封装也包含用于具有图1中所展示的第一电感器119a及第二电感器119b的电感器结构的腔。在图1中，金属化部分119c分离第一电感器与第二电感器的区域。
在图1的实施例中，微凸块包含：Vdd凸块，其用于将较高电压电平提供到SoC的eVR；及接地凸块，其用于将较低电压电平提供到SoC的eVR。Vdd凸块通过导通孔121a耦合到Vdd球，且接地凸块通过导通孔121b耦合到接地球。导通孔121a及121b位于电感器119a、119b的相对侧。
微凸块也包含：输出凸块，其用于将共同eVR输出从多层封装衬底中的电感器提供到SoC；及(如所展示)两个电感器输入凸块LX1及LX2，其用于将输入提供到多层封装衬底中的电感器。在图1的实施例中使用多个电感器，其中SoC的eVR是多相开关式调节器。尽管在图1中仅展示多相开关式调节器的两个电感器，但在许多实施例中可使用两个以上电感器。
图2出于阐释目的展示图1的eVR的开关的样本布局以及实例性单相开关式调节器的部分电路图。在图2中，为了更清晰起见展示单相开关式调节器，应理解多相开关式调节器将包含额外开关及电感器。电感器结构可经构建以与这些开关的大小匹配。图2的eVR的布局针对具有高侧(HS)开关及低侧(LS)开关的开关式调节器，所述开关串联耦合于较高电压(VDD)与较低电压(GND)之间。电感器(其中为了便于理解，仅展示单个电感器)具有耦合到HS开关与LS开关之间的节点(LX)的一端。从电感器的另一端获取通过操作HS开关及LS开关调节的输出电压。在一些实施例中且图2的部分电路图中所展示，旁路开关耦合电感器的相对端。HS开关及LS开关位于VDD耦合221a与GND耦合221b之间。如通过与图1的比较可看到，图1中所展示的电感器结构119a、119b也位于VDD与GND连接之间，且因此电感器结构与HS及LS开关结构的大小基本上匹配。
图3提供根据本发明的方面的电感器结构的三维图及附属横截面。在一些实施例中且在图3中，电感器结构是针对图1的电感器119b。
电感器结构包含金属(在一些实施例中是铜)的平面基底311。可被视为铜束的铜迹线313a、313b沿着基底的相对边缘垂直向上延伸。铜平台315a从铜束313a水平向内延伸，而类似铜平台315b从铜束313b水平向内延伸。铜平台朝向且接近于但不到达彼此及由基底311的宽度的中点界定的中点线而延伸。其它铜束317a、317b分别从铜平台315a、315b的向内边缘垂直向上延伸。散置的其它铜平台319a、319b、323a、323b及327a、327b以及另一些铜束321a、321b及325a、325b以蛇形方式形成电感器。在图3的实施例中，铜之间的间隙填充有铁氧体材料。
在一些实施例中，利用(举例来说)铜层的电镀及铁氧体材料的电泳沉积在多层封装衬底的腔中形成所述结构。可使用电镀来形成厚的铜迹线以减小电阻。在铜迹线的顶部上电沉积铁氧体材料层，此在铜迹线的顶部上产生自对准的铁氧体材料层。重复所述过程直到形成包括铜迹线与在层之间的铁氧体材料且在一些实施例中由所述铜迹线与铁氧体材料组成的结构为止。对于500um的封装腔来说，此可具有5层20um厚的铜迹线与在铜层之间的4层100um厚的铁氧体材料。在本发明的各个方面中，所述结构形成用于开关式功率调节器的电感器。
图3中所展示的结构的方面在于其允许本发明的具有相位之间经增强互电感的多相实施方案实施例。图4展示根据本发明的方面的四相实施方案的三维图。四相实施方案可用于(举例来说)图1的装置中，其中图1的横截面展示具有四个相位中的两者的电感器。在图4中，第一电感器119a对应于图1的电感器119a，且第二电感器119b对应于图1的电感器119b。在图1中不可见的是电感器419a及419b，其中电感器419a及419b分别位于电感器119a及119b后面。所述电感器中的每一者具有关于图3所论述的电感器的形式。
对于图4的电感器来说，电感器119a提供相位1，电感器119b提供相位2，电感器419a提供相位3，且电感器419b提供相位4。图5展示图4的电感器的横截面以及磁场方向。针对B-B’，以箭头展示磁场方向。针对A-A’，磁场方向是垂直的且在图式的阴影区的表面中且不在图式的填充有平行线的表面中。如图5中可见，相位1与相位3彼此异相180度运行且其经堆叠以允许沿着B-B’的磁场在同一方向上。此将使磁场的变化最小化(在其180度异相时)。相位2与相位4同样如此。可从提供另一核心区域的结构的中心获取四相开关式转换器的输出，这是因为来自相位1及相位2的电流将从边缘到中心(相位3及相位4同样如此)。
中心处的OUT节点119c也可是单个固体金属区，且将具有从顶部到底部的电流并且此与在OUT节点119c周围的磁场线相一致。此将有助于增强整个4相位实施方案的电感。连接到OUT节点的底部且环绕结构的浅灰线为整个4相位阵列提供屏障。对于具有旁路晶体管的DC-DC转换器来说，实施旁路开关以将LXn节点连接到灰线。可将VDD与GND连接放置于灰线外侧，此有助于减小VDD及GND的寄生电感。
图6是利用图4的电感器的四相开关式调节器的部分电路图。开关式调节器包含电感器119a、119b及419a、419b。电感器119a、119b、419a、419b中的每一者分别具有耦合到Vout 621a的输出端及耦合到高侧开关624a到624d与626a到626d之间的节点的输入端。在图6的电路图中，旁路开关也用于耦合每一电感器的端，举例来说旁路开关632a、632b各自耦合电感器119b的端。
图7展示根据本发明的方面的8相实施方案的电感器结构的横截面。对于图7的电感器结构来说，图4的电感器结构经镜像以进一步增强两个4相位阵列之间的互电感。因此，在图7的B-B’横截面与图4的等效B-B’横截面相关的情况下，磁场方向由提供八个相位中的四者的四个电感器751、753、755及757的部分的箭头指示，其中磁场方向提供电感器之间的互电感。为完整起见，图7也包含与图4的等效A-A’横截面相关的A-A’横截面，其展示图7的电感器结构的电感器719a、719b的相同构造。
图8图解说明可用于形成根据本发明的方面的电感器结构的步骤。在多层封装811的腔中形成电感器结构。可使用偏置连接817来为电镀提供偏置。偏置连接817通常仅用于电镀且可是小迹线。铜电镀的图案可是薄的金属(举例来说金属818)层，其经沉积及蚀刻以界定其中铜将通过电镀生长的区。由电镀形成的铜迹线(举例来说，铜迹线813、819及821)可继而用于铁氧体材料(举例来说铁氧体材料815、823)的电泳沉积。通过交替地沉积铜及铁氧体材料来重复所述过程。可对最终铜层831进行抛光以在结构的顶部处产生平坦表面。因此，铁氧体材料的均匀度及实际厚度对于平坦的最终表面而言并不重要，且与用于硅凸块接合的封装顶部表面对准。铁氧体材料的沉积不必具选择性且在铁氧体层的沉积之间其它沉积技术也可与铜电镀一起使用。
在根据本发明的方面的另一实施例中，可使用封装衬底布线层来产生电感器结构，且可在每一分离层的腔中沉积铁氧体材料。图9是多层封装911的俯视图，其展示用于2相电感器阵列的第一腔915及用于4相电感器阵列的第二腔913。所述腔的横截面形状大体上呈矩形。如图9中所展示，用于4相阵列的第二腔具有基本上两倍于用于2相阵列的第一腔的宽度。
图10展示图9的多层封装的构造的第一横截面及第二横截面。第一横截面展示多层封装的第一层1011及第二层1013，其中第二层位于第一层的顶部上。第二层包含腔，所述腔具有铺设于第一层的顶部上的铜迹线图案1015，其中铁氧体沉积部107位于铜迹线图案的顶部上且填充腔。
第二横截面展示沿着第二层的腔的各侧的导通孔及位于第二层的顶部上的第三层1021。出于图解说明目的，第二横截面也展示多层封装中通常会存在的典型导通孔/金属布线1027的一部分。第三层包含位于第二层的腔上方的腔，其中两个腔具有基本上相同的尺寸。另一铜迹线图案1023位于第二层的腔的铁氧体沉积部上，且另一铁氧体1025已沉积于第三层的腔中、另一铜迹线图案的顶部上。以此方式，可使用铜迹线图案及铁氧体沉积部来形成电感器阵列。
在各种实施例中且至于关于图8所述的实例，可(举例来说)使用电镀将金属迹线安放于铁氧体沉积部上，接着将铜安放于金属迹线上。在一些实施例中，可在施加铜电镀之前在金属1图案的顶部上将不同厚度的金属2迹线图案化，其中在一些实施例中金属1与金属2是不同的金属，其(举例来说)可被选择性地蚀刻。此在最终铜表面上产生希望的凸块且增加层的表面积。当趋肤效应变成主要因素时，此可是有帮助的。
图11展示根据本发明的一些方面的封装的横截面，其图解说明产生具有凸块的铜表面的过程步骤。图11的第一横截面展示封装衬底1111，其中基底铜层1113位于所述衬底的顶部上。铁氧体1114已被沉积于基底铜层的至少一些部分上，且第一金属迹线图案1115位于铁氧体的顶部上。第二金属迹线图案位于第一金属迹线图案的选定部分上，其中第二金属迹线图案在第一金属迹线图案上有效地形成凸块(举例来说，凸块1117)。在一些实施例中，第二金属迹线图案具有与第一金属迹线图案不同的金属。在一些实施例中，可选择性地蚀刻不同金属，从而允许增加图案之间精度差。在一些实施例中，所述金属中的一者是钛钨(TiW)合金且所述金属中的另一者是铝。
图11的第二横截面展示位于金属迹线图案上方的铜表面1121(图11中所展示的两个部分之间有额外空间以允许便于观看)。可均匀地位于金属迹线图案上方的铜表面由于第二金属迹线图案的非均匀性而包含凸块。铜表面中的凸块也用于增加铜表面的表面积。
尽管已关于各种实施例论述了本发明，但应认识到本发明包括本发明支持的新颖且非显而易见的权利要求。

Claims (14)

1.一种集成芯片封装，其包括：
倒装芯片类型的集成电路IC芯片，其包含单芯片系统SoC及开关式电压调节器，所述开关式电压调节器包含串联耦合于较高电压电平连接与较低电压电平连接之间的至少第一开关及第二开关；
多层衬底，其具有腔，在所述腔中具有至少一个电感器，所述至少一个电感器具有散置着铁氧体材料的多个上部迹线层，所述电感器包含第一端及第二端；及
多个微凸块，其将所述IC芯片连接到所述衬底，包含将所述第一开关与所述第二开关之间的节点连接到所述电感器的所述第一端的微凸块。
2.根据权利要求1所述的集成芯片封装，其中所述电压调节器是多相电压调节器，且所述至少一个电感器包括多个电感器。
3.根据权利要求2所述的集成芯片封装，其中所述电压调节器包含多个开关对，所述开关对包含所述第一开关及所述第二开关，且所述多个电感器的面积与所述多个开关对的面积相同。
4.根据权利要求3所述的集成芯片封装，其中所述多个电感器被布置成电感器阵列，其中所述电感器阵列的至少电感器对经布置使得在所述电感器对以180度异相操作时所述电感器对的磁场的方向是对准的。
5.根据权利要求2所述的集成芯片封装，其中铜迹线中的至少一些铜迹线位于至少一个金属图案上方。
6.根据权利要求5所述的集成芯片封装，其中所述至少一个金属图案包含凸块。
7.根据权利要求6所述的方法，其中所述至少一个金属图案包括两个金属图案。
8.根据权利要求6所述的方法，其中所述两个金属图案各自具有不同金属。
9.一种倒装芯片封装，其包括：
倒装芯片类型的集成电路IC芯片，其包含单芯片系统SoC及多相电压调节器，所述多相电压调节器包含串联耦合的第一对晶体管及串联耦合的第二对晶体管；及
多层封装衬底，其具有多个重新分布层以及第一电感器及第二电感器，所述第一电感器及所述第二电感器由多个电镀迹线形成，所述第一电感器及所述第二电感器中的每一者包含第一端及第二端，所述多个电镀迹线由所述多层封装衬底的腔内的导电层形成，铁氧体材料在所述导电层中的至少一些导电层之间，且其中第一多个电镀迹线中的至少一者经配置以将所述第一电感器的所述第二端连接到所述第二电感器的所述第一端；及
多个凸块，其经配置以在多个节点处将所述IC芯片连接到所述多层封装衬底，所述多个节点包含供应节点、接地节点、负载输出节点及电感器节点，所述负载输出节点包含所述第一电感器的所述第二端与所述第二电感器的所述第一端之间的连接，所述电感器节点包含：经配置以将所述第一对晶体管之间的节点连接到第一电感器结构的所述第一端的节点；及经配置以将所述第二对晶体管之间的节点连接到第二电感器结构的所述第二端的节点。
10.根据权利要求9所述的倒装芯片封装，其中所述多相电压调节器进一步包含串联耦合的第三对晶体管及串联耦合的第四对晶体管，且
其中所述多层封装进一步具有由所述多个电镀迹线形成的第三电感器及第四电感器，所述第三电感器及所述第四电感器中的每一者包含第一端及第二端，且
其中所述第一多个电镀迹线中的所述至少一者进一步经配置以将所述第三电感器的所述第二端连接到所述第四电感器的所述第一端。
11.根据权利要求10所述的倒装芯片封装，其中所述多相电压调节器是四相电压调节器。
12.根据权利要求11所述的倒装芯片封装，其中所述四相电压调节器的第一相位及第三相位经配置以执行180度异相，且所述四相电压调节器的第二相位及第四相位经配置以执行180度异相。
13.根据权利要求9所述的倒装芯片封装，其中所述多个电镀迹线包括铜。
14.根据权利要求9所述的倒装芯片封装，其中所述第一电感器的大小经配置以与所述第一对晶体管中的每一者的大小匹配，且所述第二电感器的大小经配置以与所述第二对晶体管中的每一者的大小匹配。
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