CN107403826A - 薄膜晶体管及其制造方法和包括薄膜晶体管的显示设备 - Google Patents

薄膜晶体管及其制造方法和包括薄膜晶体管的显示设备 Download PDF

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CN107403826A
CN107403826A CN201710356806.8A CN201710356806A CN107403826A CN 107403826 A CN107403826 A CN 107403826A CN 201710356806 A CN201710356806 A CN 201710356806A CN 107403826 A CN107403826 A CN 107403826A
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tft
layer
gate electrode
semiconductor layer
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朴鲜
柳春基
权赫珣
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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Abstract

提供了一种薄膜晶体管及其制造方法和包括薄膜晶体管的显示设备，所述薄膜晶体管包括：基底；半导体层，设置在基底上方；栅极绝缘膜，设置在半导体层上方；以及栅电极。半导体层包括沟道区、源区和漏区。栅极绝缘膜包括第一区和第二区。第二区与第一区接界。栅电极设置在第一区上方。台阶形状形成在第二区和第一区相接处。

Description

薄膜晶体管及其制造方法和包括薄膜晶体管的显示设备
本申请要求于2016年5月20日提交到韩国知识产权局的第10-2016-0062171号韩国专利申请的优先权，通过引用将该韩国专利申请的公开内容全部包含于此。
技术领域
本发明涉及一种薄膜晶体管、制造该薄膜晶体管的方法和包括该薄膜晶体管的显示设备。
背景技术
显示设备可用于显示图像。各种显示设备包括液晶显示器(LCD)、电泳显示器、有机发光显示器(OLED)、无机发光显示器、场发射显示器、表面传导电子发射显示器、等离子体显示器和阴极射线显示器。
显示设备通常包括显示器件、多个薄膜晶体管(TFT)、多个电容器以及用于连接显示器件、TFT和电容器的布线。高品质的TFT可提高显示设备的质量。
发明内容
本发明的示例性实施例提供了一种显示设备。显示设备包括薄膜晶体管(TFT)、平坦化膜、像素电极、对电极和中间层。平坦化膜与TFT叠置。像素电极设置在平坦化膜上方。像素电极连接到TFT。对电极面向像素电极。中间层设置在像素电极和对电极之间。TFT包括半导体层、栅极绝缘膜和栅电极。半导体层设置在基底上方。半导体层包括源区、沟道区和漏区。栅极绝缘膜设置在半导体层上方。栅极绝缘膜包括第一区和第二区。第二区设置在第一区的侧部处。栅电极设置在第一区上方。第一区的厚度不同于第二区的厚度以形成台阶形状。
根据本发明的示例性实施例，第一区的上表面的面积可以大于栅电极的下表面的面积。
根据本发明的示例性实施例，栅电极的下表面的端部与第一区的上表面的端部之间的距离可以在从大约5nm至大约1000nm的范围内。
根据本发明的示例性实施例，第一区可以具有基本均匀的厚度。
根据本发明的示例性实施例，第二区的厚度可以沿着远离第一区的方向减小。
根据本发明的示例性实施例，半导体层可以包括氧化物半导体。
根据本发明的示例性实施例，栅极绝缘膜可以不覆盖半导体层的两个边缘。
根据本发明的示例性实施例，显示设备还可以包括像素限定层。像素限定层可以暴露像素电极的第一区，并覆盖像素电极的边缘。
根据本发明的示例性实施例，中间层可以包括有机发光层。
本发明的示例性实施例提供了一种制造薄膜晶体管的方法。所述方法包括：在基底上方形成半导体层；在基底上顺序形成栅极绝缘材料层和栅电极材料层以覆盖半导体层；在栅电极材料层上形成第一光致抗蚀剂图案；通过使用第一光致抗蚀剂图案作为掩摸蚀刻栅电极材料层来形成栅电极；形成覆盖栅电极的两个侧壁和上表面的第二光致抗蚀剂图案；以及通过使用第二光致抗蚀剂图案作为掩模蚀刻栅极绝缘材料层来形成栅极绝缘膜。
根据本发明的示例性实施例，可以通过使第一光致抗蚀剂图案回流来形成第二光致抗蚀剂图案。
根据本发明的示例性实施例，所述方法还可以包括执行传导工艺以增加半导体层的一部分的载流子浓度。
根据本发明的示例性实施例，蚀刻栅极绝缘材料层的步骤可以包括干法蚀刻工艺。传导工艺可以使用在干法蚀刻工艺中使用的气体。
根据本发明的示例性实施例，栅极绝缘膜可以包括第一区和第二区。第二区可以设置在第一区的侧部处。第一区的厚度可以不同于第二区的厚度以形成台阶形状。
根据本发明的示例性实施例，栅电极可以设置在第一区上。第一区的上表面的面积可以大于栅电极的下表面的面积。
根据本发明的示例性实施例，第二区的厚度可以沿着远离第一区的方向减小。
根据本发明的示例性实施例，半导体层可以包括氧化物半导体。
本发明的示例性实施例提供了一种薄膜晶体管。薄膜晶体管包括基底、半导体层、栅极绝缘膜和栅电极。半导体层设置在基底上。半导体层包括沟道区、源区和漏区。栅极绝缘膜设置在半导体层上。栅极绝缘膜包括第一区和第二区。第二区与第一区接界。栅电极设置在第一区上。台阶形状形成在第二区和第一区相接处。
根据本发明的示例性实施例，栅电极的下表面的端部与第一区的上表面的端部之间的距离可以在从大约5nm至大约1000nm的范围内。
根据本发明的示例性实施例，第一区可以具有基本均匀的厚度。
附图说明
通过参照附图详细地描述本发明的示例性实施例，本发明的这些和/或其它特征将变得更加明显，在附图中：
图1是示出根据本发明示例性实施例的薄膜晶体管(TFT)的示意性平面图；
图2是示出根据本发明示例性实施例的TFT的示意性平面图；
图3是示出根据本发明示例性实施例的沿线I-I’的图1和图2的TFT的剖视图；
图4是示出根据本发明示例性实施例的TFT的示意性剖视图；
图5A至图5G是示出根据本发明示例性实施例的制造TFT的方法的剖视图；
图6是示出根据本发明示例性实施例的显示设备的示意性平面图；
图7是示出根据本发明示例性实施例的显示设备的像素的等效电路图；以及
图8是示出根据本发明示例性实施例的图6的显示设备的显示区的一部分的剖视图。
具体实施方式
现在将参照附图描述本发明的示例性实施例。然而，本发明可以以许多不同的形式来实施，而不应该被理解为局限于在这里阐述的实施例。在附图中，同样的附图标记可以始终表示同样的元件。如在此所使用的，单数形式“一个”、“一种(者)”和“该(所述)”也意图包括复数形式，除非上下文另外明确表明。
在附图中，为便于解释，构成元件的尺寸可以被缩减或夸大。
将理解的是，可以以与描述的顺序不同地执行具体的工艺顺序。例如，可以基本上同时执行或者可以以与描述的顺序相反的顺序执行两个连续描述的工艺。
将理解的是，当层、区域或组件被称为“连接到”另一层、区域或组件或者“设置在”另一层、区域或组件“上”时，该层、区域或组件可以“直接连接到”所述另一层、区域或组件或“直接设置在”所述另一层、区域或组件“上”，或者该层、区域或组件可以“间接连接到”所述另一层、区域或组件或“间接设置在”所述另一层、区域或组件“上”，其间插入有其它层、区域或组件。
图1是示出根据本发明示例性实施例的薄膜晶体管(TFT)的示意性平面图。图2是示出根据本发明示例性实施例的TFT的示意性平面图。图3是根据本发明示例性实施例的沿线I-I’的图1和图2的TFT的剖视图。
参照图1至图3，TFT可以包括半导体层211、栅极绝缘膜120和栅电极213。半导体层211可以设置在基底100上。栅极绝缘膜120可以设置在半导体层211上。栅电极213可以设置在栅极绝缘膜120上。栅极绝缘膜120可以包括中心区121。栅极绝缘膜120还可以包括围绕区123。由于中心区121可以具有不同于围绕区123的厚度的厚度，因而它们之间可以形成台阶差异。
栅极绝缘膜120可以包括中心区121和围绕区123。围绕区123可以从中心区121延伸。中心区121的厚度t1可以不同于围绕区123的厚度t2。因此，可以形成台阶。
根据本发明的示例性实施例，TFT还可以包括缓冲层110、层间绝缘层130、源电极215s和漏电极215d。
基底100可以包括各种材料，诸如玻璃、金属或塑料；然而，本发明的示例性实施例不限于此。根据本发明的示例性实施例，基底100可以包括柔性基底。柔性基底可以包括能弯曲、折叠或卷起的基底。基底100可以包括各种柔性的或者可弯曲的材料。例如，基底100可以包括聚合树脂材料，诸如聚醚砜(PES)、聚丙烯酸酯(PAR)、聚醚酰亚胺(PEI)、聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二醇酯(PET)、聚苯硫醚(PPS)、聚芳酯、聚酰亚胺(PI)、聚碳酸酯(PC)或者醋酸丙酸纤维素(CAP)；然而，本发明的示例性实施例不限于此。
缓冲层110可以设置在基底100上。缓冲层110可以减少或可以阻止外来物质、水分或者外界空气从基底100的下表面渗透。缓冲层110还可以在基底100上提供基本平坦的表面。缓冲层110可以包括诸如氧化物或氮化物的无机材料、有机材料或者有机-无机复合材料；然而，本发明的示例性实施例不限于此。缓冲层110可以包括单层结构或多层结构。多层结构可以包括无机材料或者有机材料。半导体层211可以延伸至沟道区211c。半导体层211可以包括源区211s。半导体层211还可以包括漏区211d。源区211s和漏区211d可以形成在沟道区211c的相对侧上。半导体层211可以包括氧化物半导体。例如，半导体层211可以包括第12族、13族和14族的金属元素，诸如锌(Zn)、铟(In)、镓(Ga)、锡(Sn)、镉(Cd)、锗(Ge)和铪(Hf)。半导体层211还可以包括从第12族、13族和14族的金属元素(诸如锌(Zn)、铟(In)、镓(Ga)、锡(Sn)、镉(Cd)、锗(Ge)和铪(Hf))或它们的组合中选择的材料的氧化物。然而，本发明的示例性实施例不限于此。根据本发明的示例性实施例，半导体层211可以包括锌(Zn)的氧化物类材料，诸如氧化锌、In-Zn氧化物或Ga-In-Zn氧化物；然而，本发明的示例性实施例不限于此。根据本发明的示例性实施例，半导体层211可以是In-Ga-Zn-O(IGZO)半导体。In-Ga-Zn-O(IGZO)半导体可以通过包括诸如铟(In)和镓(Ga)的金属与氧化锌(ZnO)形成。
源区211s和漏区211d可以为导电区域。可以通过增加半导体层211中的载流子浓度来形成源区211s和漏区211d。如果半导体层211包括氧化物半导体，那么源区211s和漏区211d可以变成导电的。源区211s和漏区211d可以通过执行半导体层211的等离子体工艺变成导电的。因此，源区211s的载流子浓度和漏区211d的载流子浓度可以大于沟道区211c的载流子浓度。
沟道区211c的形状可以包括各种形式。如图2所示，沟道区211c可以具有弯曲形状。弯曲形状的沟道区211c可以确保沟道的长度。可以以各种方式修改沟道区211c，例如，形状或者形状；然而，本发明的示例性实施例不限于此。
栅电极213可以设置在栅极绝缘膜120的中心区121上。栅电极213可以对应于沟道区211c。栅电极213的一部分可以与沟道区211c叠置。栅电极213可以连接到布线。布线可以将ON/OFF信号施加到TFT。栅电极213可以包括低电阻金属。例如，栅电极213可以包括包含钼(Mo)、铝(Al)、铜(Cu)和/或钛(Ti)的导电材料；然而，本发明的示例性实施例不限于此。栅电极213可以包括单层膜或多层膜。根据本发明的示例性实施例，栅电极213可以包括钛/铜(Ti/Cu)的双层或钛/铝(Ti/Al)的双层；然而，本发明的示例性实施例不限于此。钛(Ti)层可以设置在钛/铜(Ti/Cu)或钛/铝(Ti/Al)的下侧表面上。钛(Ti)层的厚度可以小于铜(Cu)层和铝(Al)层的厚度。因此，钛(Ti)层可以被构造为阻挡件并起到阻挡件的作用。
栅极绝缘膜120可以设置在半导体层211和栅电极213之间。栅极绝缘膜120可以被构造为半导体层211和栅电极213之间的绝缘件。栅极绝缘膜120可以包括无机材料，例如，氧化硅、氮化硅和/或氧氮化硅；然而，本发明的示例性实施例不限于此。栅极绝缘膜120可以通过化学气相沉积(CVD)法或原子层沉积(ALD)法形成并可以进行图案化。
栅极绝缘膜120可以包括中心区121。栅极绝缘膜120还可以包括围绕区123。围绕区123可以从中心区121延伸。中心区121的厚度t1可以不同于围绕区123的厚度t2。因此，可以形成台阶。根据本发明的示例性实施例，栅极绝缘膜120可以不覆盖基底100的整个表面。栅极绝缘膜120可以被图案化为基本类似于栅电极213的形状。栅极绝缘膜120可以不覆盖半导体层211的侧表面。因此，源区211s和漏区211d可以被暴露。
栅电极213可以设置在中心区121上。中心区121具有厚度t1。围绕区123可以设置在中心区121的外部区域上。围绕区123可以从中心区121延伸。围绕区123可以围绕中心区121的至少一部分。中心区121的上表面的面积可以大于栅电极213的下表面的面积。如图3所示，栅电极213的下表面的宽度Wg可以小于中心区121的上表面的宽度Wi。例如，中心区121的上表面的边缘可以与栅电极213的下表面的边缘分离。中心区121的上表面可以为面向栅电极213的表面。栅电极213的下表面可以为面向基底100的表面。栅电极213的下表面的端部和中心区121的上表面的端部之间的分开距离d可以在从大约5nm至大约1000nm的范围内。分开距离d的最大值可以为栅电极213的下表面的端部与栅极绝缘膜120的上表面的端部之间的距离的大约90％。
围绕区123的厚度t2可以小于中心区121的厚度t1。由于厚度t1可以不同于厚度t2，所以在中心区121和围绕区123之间的边界处可以形成台阶差异。根据本发明的示例性实施例，中心区121的厚度t1可以在从大约50nm至大约200nm的范围内。围绕区123的厚度t2可以在从大约30nm至中心区121的厚度t1的大约90％的范围内。
由于根据本发明示例性实施例的制造TFT的工艺导致可能形成栅极绝缘膜120上的台阶差异。因为光致抗蚀剂图案可以围绕栅电极213的侧壁，所以可以防止在制造TFT的工艺期间在栅电极213和半导体层211之间短路的发生。
层间绝缘层130可以设置在栅电极213上。层间绝缘层130可以包括无机材料，例如，氧化硅、氮化硅和/或氧氮化硅；然而，本发明的示例性实施例不限于此。可以通过CVD法或ALD法形成层间绝缘层130。
源电极215s和漏电极215d可以设置在层间绝缘层130上。源电极215s和漏电极215d可以为单层膜或者多层膜。源电极215s和漏电极215d可以包括导电材料。导电材料可以具有高导电率。源电极215s和漏电极215d可以分别连接到源区211s和漏区211d。源电极215s可以包括单层结构。漏电极215d可以包括多层结构。源电极215s和漏电极215d可以包括包含铝(Al)、铜(Cu)和/或钛(Ti)的导电材料；然而，本发明的示例性实施例不限于此。源电极215s和漏电极215d可以通过接触孔CNT分别连接到源区211s和漏区211d。接触孔CNT可以穿过半导体层211。接触孔CNT也可以穿过层间绝缘层130。
图4是示出根据本发明示例性实施例的TFT的示意性剖视图。
参照图3，栅极绝缘膜120的围绕区123的厚度t2可以是基本上均匀的。然而，如图4所示，围绕区123的厚度可以沿着远离中心区121的方向逐渐减小。因为中心区121的厚度可以不同于围绕区123的厚度，所以可以形成台阶差异。台阶差异可以形成在中心区121和围绕区123之间的边界处。
图5A至图5G是示出根据本发明示例性实施例的制造TFT的方法的剖视图。这里，将以图3的TFT作为示例进行描述。
参照图5A，可以在基底100上形成缓冲层110和半导体层211。半导体层211可以包括氧化物半导体。半导体层211也可以包括第12族、13族和14族的金属元素，诸如锌(Zn)、铟(In)、镓(Ga)、锡(Sn)、镉(Cd)、锗(Ge)或铪(Hf)。半导体层也可以包括从第12族、13族和14族的金属元素(诸如锌(Zn)、铟(In)、镓(Ga)、锡(Sn)、镉(Cd)、锗(Ge)或铪(Hf))或者它们的组合中选择的材料的氧化物。然而，本发明的示例性实施例不限于此。根据本发明的示例性实施例，半导体层211可以包括锌(Zn)的氧化物类材料，诸如氧化锌(Zn)、In-Zn氧化物或Ga-In-Zn氧化物。根据本发明的示例性实施例，半导体层211可以是In-Ga-Zn-O(IGZO)半导体，所述In-Ga-Zn-O(IGZO)半导体通过包括诸如铟(In)和镓(Ga)的金属与氧化锌(ZnO)形成。
可以通过利用CVD法形成半导体层211。也可以通过利用脉冲激光沉积(PLD)法形成半导体层211。然而，本发明的示例性实施例不限于此。例如，可以通过CVD法由In-Ga-Zn-O(IGZO)形成膜。所述膜可以被图案化为与半导体层211基本相同的形状。可以通过湿法蚀刻工艺来执行所述膜的图案化。湿法蚀刻工艺可以使用酸溶液，例如，盐酸(HCl)、硝酸(HNO3)、稀硫酸(H2SO4)或者磷酸(H3PO4)、硝酸(HNO3)和醋酸(CH3COOH)的混合物；然而，本发明的示例性实施例不限于此。也可以通过使用干法蚀刻工艺来执行所述膜的图案化。也可以通过使用湿法蚀刻工艺和干法蚀刻工艺的组合来执行所述膜的图案化。
参照图5B，可以在基底100上形成栅极绝缘材料层120'。也可以在基底100上形成栅电极材料层213'。栅极绝缘材料层120'和栅电极材料层213'可以覆盖半导体层211。
栅极绝缘材料层120'可以包括无机材料，诸如氧化硅、氮化硅和/或氧氮化硅；然而，本发明的示例性实施例不限于此。可以通过CVD法或ALD法形成栅极绝缘材料层120'。
栅电极材料层213'可以包括钼(Mo)、铝(Al)、铜(Cu)和/或钛(Ti)；然而，本发明的示例性实施例不限于此。栅电极材料层213'可以形成为单层膜或者多层膜。可以通过利用沉积法(例如，CVD法、等离子体增强化学气相沉积(PECVD)法、低压化学气相沉积(LPCVD)法、物理气相沉积(PVD)法、溅射法或ALD法)形成栅电极材料层213'；然而，本发明的示例性实施例不限于此。
可以在栅电极材料层213'上形成第一光致抗蚀剂图案PR1。第一光致抗蚀剂图案PR1的位置可以对应于形成栅电极213的位置。
参照图5C，可以通过使用第一光致抗蚀剂图案PR1作为蚀刻掩模蚀刻栅电极材料层213'来形成栅电极213。如图5C所示，栅电极213的宽度可以小于第一光致抗蚀剂图案PR1的宽度；然而，本发明的示例性实施例不限于此。栅电极213的宽度可以基本上等于或大于第一光致抗蚀剂图案PR1的宽度。可以通过湿法蚀刻工艺、干法蚀刻工艺或者湿法蚀刻工艺和干法蚀刻工艺的组合来执行栅电极材料层213'的蚀刻。
参照图5D，可以形成第二光致抗蚀剂图案PR2。第二光致抗蚀剂图案PR2可以覆盖栅电极213的侧壁和上表面。可以通过使第一光致抗蚀剂图案PR1回流来形成第二光致抗蚀剂图案PR2。可以通过对其上形成有第一光致抗蚀剂图案PR1的基底100进行热处理来执行回流工艺。可以在大约130℃至大约250℃的范围内的温度氛围下对基底100进行热处理。可以在栅电极213的两个侧壁和上表面上形成第二光致抗蚀剂图案PR2。因此，第一光致抗蚀剂图案PR1可以通过利用回流工艺沿栅电极213的两个侧壁流动。
可选择地，可以通过使用额外的光刻方法形成第二光致抗蚀剂图案PR2。参照图5E和图5F，可以通过使用第二光致抗蚀剂图案PR2作为蚀刻掩模蚀刻栅极绝缘材料层120'来形成栅极绝缘膜120。半导体层211的源区211s和漏区211d可以通过执行刻蚀工艺变成导电的。刻蚀工艺可以是使用甲烷(CH4)或过硫烷(SH6)的等离子体气体的干法刻蚀；然而，本发明的示例性实施例不限于此。
半导体层211可以为氧化物半导体。如果半导体层211是氧化物半导体，则可以通过形成氧耗尽状态增加载流子浓度。因此，可以通过形成栅极绝缘膜120来增加源区211s的载流子浓度和漏区211d的载流子浓度。可以通过控制干法刻蚀的工艺时间并且通过对被暴露并且未被栅极绝缘膜120覆盖的半导体层211造成损坏来形成栅极绝缘膜120。
由于第二光致抗蚀剂图案PR2的边缘部分可以具有小厚度，所以可以形成栅极绝缘膜120的中心区121和围绕区123。栅极绝缘膜120的中心区121和围绕区123可以产生高度差。例如，栅极绝缘膜120可以包括中心区121。栅极绝缘膜120还可以包括围绕区123。围绕区123可以从中心区121延伸。中心区121的厚度t1可以不同于围绕区123的厚度t2。因此，可以形成台阶。栅电极213可以设置在中心区121上。中心区121的厚度t1可以基本不变。围绕区123可以是围绕中心区121的区域。根据本发明的示例性实施例，中心区121的厚度t1可以在从大约50nm至大约200nm的范围内。围绕区123的厚度t2可以在从大约30nm至中心区121的厚度t1的大约90％的范围内。
第二光致抗蚀剂图案PR2可以形成为围绕栅电极213的侧壁。因此，中心区121的上表面的面积可以大于栅电极213的下表面的面积。因此，中心区121的上表面的边缘可以与栅电极213的下表面的边缘分离。
如图5F所示，由于中心区121和围绕区123之间在竖直截面的高度差而可以形成台阶差异；然而，本发明的示例性实施例不限于此。可以根据第二光致抗蚀剂图案PR2的形状来对围绕区123的形状进行各种修改。例如，中心区121和围绕区123可以不形成台阶差异。围绕区123的厚度可以远离中心区121逐渐减小。
根据本发明的示例性实施例，第二光致抗蚀剂图案PR2可以防止在刻蚀工艺期间可以从半导体层211分离的铟(In)、镓(Ga)或者锌(Zn)累积在栅电极213的侧壁上。
如果第二光致抗蚀剂图案PR2没有围绕栅电极213的侧壁，则在刻蚀工艺中从半导体层211分离的诸如铟(In)、镓(Ga)或者锌(Zn)的金属材料可能累积在栅电极213的侧壁和栅极绝缘膜120上。金属材料也可能连接到半导体层211。结果，半导体层211和栅电极213之间可能发生短路。
根据本发明的示例性实施例，因为在栅极绝缘膜120的刻蚀工艺中和半导体层211的传导工艺中第二光致抗蚀剂图案PR2围绕栅电极213的侧壁，所以可以防止半导体层211和栅电极213之间短路。
栅电极213的下表面的端部和中心区121的上表面的端部之间的分开距离可以在从大约5nm至大约1000nm的范围内。最大分开距离可以为栅电极213的下表面的端部与栅极绝缘膜120的上表面的端部之间的距离的大约90％。如果分开距离小于大约5nm，则第二光致抗蚀剂图案PR2不能充分地围绕栅电极213。因此，半导体层211和栅电极213之间可能发生短路。
一旦形成栅极绝缘膜120并且源区211s和漏区211d变成导电的，就可以去除第二光致抗蚀剂图案PR2。
参照图5G，可以在栅电极213上形成层间绝缘层130。可以在基底100的基本上整个表面上方形成层间绝缘层130。层间绝缘层130可以包括无机材料，例如，氧化硅、氮化硅和/或氧氮化硅；然而，本发明的示例性实施例不限于此。可以通过CVD法或ALD法形成层间绝缘层130。
可以形成通孔CNT。通孔CNT可以穿过层间绝缘层130。通孔CNT可以暴露源区211s和漏区211d。
可以形成源电极215s和漏电极215d。源电极215s和漏电极215d可以包括钼(Mo)、铝(Al)、铜(Cu)和/或钛(Ti)；然而，本发明的示例性实施例不限于此。源电极215s和漏电极215d可以形成为单层膜或者多层膜。可以通过采用各种沉积工艺(例如，CVD法、PECVD法、LPCVD法、PVD法、溅射法或者ALD法)形成导电材料层；然而，本发明的示例性实施例不限于此。可以通过对导电材料层图案化来形成源电极215s和漏电极215d。
以上描述的TFT和TFT的改进方式可以应用于显示设备。在下文中，现在将描述图3的TFT应用于显示设备的示例。
显示设备显示图像并且可以包括液晶显示器、电泳显示器、有机发光显示器、无机发光显示器、场发射显示器、表面传导电子发射显示器、等离子体显示器和阴极射线显示器。
在下文中，作为根据当前实施例的显示设备，描述了有机发光显示器。然而，根据当前实施例的显示设备不限于此，因此，可以使用各种方法的显示设备。
图6是根据本发明示例性实施例的显示设备的示意性平面图。如图6所示，显示设备可以包括基底100。基底100可以包括显示区DA。基底100也可以包括外围区PA。外围区PA可以设置在显示区DA外面。例如有机发光器件(OLED)的各种显示器件可以布置在基底100的显示区DA上。各种布线可以布置在基底100的外围区PA上。各种布线可以被构造为发送将被施加到基底100的显示区DA的电信号。
图7是示出根据本发明示例性实施例的图6的显示设备的像素的等效电路图。在图7中，示出了包括OLED的像素；然而，本发明的示例性实施例不限于此。
参照图7，每个像素PX可以包括像素电路PC。像素电路PC可以连接至扫描线SL。像素电路PC也可以连接至数据线DL。每个像素PX还可以包括OLED。OLED可以连接至像素电路PC。
像素电路PC可以包括第一TFT TFT1、第二TFT TFT2和电容器CAP。第一TFT TFT1可以连接到扫描线SL。第一TFT TFT1也可以连接到数据线DL。第一TFT TFT1可以被构造为将通过数据线DL输入的数据信号Dm发送至第二TFT TFT2。可以响应于通过扫描线SL输入的扫描信号Sn将通过数据线DL输入的数据信号Dm发送至第二TFT TFT2。
电容器CAP可以连接到第一TFT TFT1。电容器CAP也可以连接到驱动电压线PL。电容器CAP可以存储电压。所述电压可以对应于从第一TFT TFT1传输的电压和供应到驱动电压线PL的驱动电压ELVDD之间的差。像素PX可以接收电压ELVSS。电压ELVSS可以连接到OLED。
第二TFT TFT2可以连接至驱动电压线PL。第二TFT TFT2也可以连接至电容器CAP。第二TFT TFT2可以控制从驱动电压线PL流入OLED的驱动电流。第二TFT TFT2可以对应于电容器CAP中存储的电压值来控制驱动电流。OLED可以发光。通过OLED发射的光可以具有依据驱动电流的预定亮度。
图8是示出根据本发明示例性实施例的图6的显示设备的显示区DA的一部分的剖视图。
参照图8，除TFT之外，显示设备还可以包括显示器件(例如OLED 300)和电容器CAP。
电容器CAP可以包括第一电极C1、第二电极C2和绝缘膜。绝缘膜可以插入在第一电极C1和第二电极C2之间。根据本发明的示例性实施例，第一电极C1可以设置在与采用用于形成第一电极C1基本相同材料的源电极215s和漏电极215d相同的层上。第二电极C2可以设置在与采用用于形成第二电极C2基本相同材料的栅电极213相同的层上。层间绝缘层130可以插入在第一电极C1和第二电极C2之间。
在图8中，电容器CAP可以不与TFT叠置。然而，电容器CAP可以通过形成在TFT上而与TFT叠置。
平坦化层140可以形成在TFT上。平坦化层140可以形成在电容器CAP上。平坦化层140也可以形成在TFT和电容器CAP上。例如，如图8所示，如果OLED 300设置在TFT上，则平坦化层140可以使保护膜的上表面平坦化。保护膜可以覆盖半导体器件。平坦化层140可以包括有机材料，诸如亚克力、苯并环丁烯(BCB)或者六甲基二硅醚(HMDSO)；然而，本发明的示例性实施例不限于此。在图8中，平坦化层140示出为单层；然而，平坦化层140可以进行各种改进。例如，平坦化层140可以包括多层。
OLED 300可以设置在平坦化层140上。OLED 300可以包括像素电极310、对电极330和中间层320。中间层320可以包括发光层。如图8所示，像素电极310可以连接至TFT。像素电极310可以通过形成在平坦化层140中的开口接触源电极215s和漏电极215d之一而连接到TFT。因此，像素电极310可以连接到漏电极215d。
像素电极310可以为透明电极。可选择地，像素电极310可以为反射电极。当像素电极310为透明电极时，像素电极310可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)或者氧化铟(III)(In2O3)；然而，本发明的示例性实施例不限于此。当像素电极310形成为反射电极时，像素电极310可以包括反射膜。反射膜可以包括银(Ag)、镁(Mg)、铝(Al)、铂(Pt)、钯(Pd)、金(Au)、镍(Ni)、钕(Nd)、铱(Ir)、铬(Cr)或者它们的组合；然而，本发明的示例性实施例不限于此。像素电极310还可以包括透明膜。透明膜可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)或者氧化铟(III)(In2O3)；然而，本发明的示例性实施例不限于此。根据本发明的实施例，像素电极310可以包括氧化铟锡(ITO)/银(Ag)/氧化铟锡(ITO)结构。
像素限定层150可以设置在平坦化层140上。像素限定层150可以用来限定像素。像素限定层150可以通过包括与每个子像素对应的开口来限定像素。例如，开口至少暴露像素电极310的中心部分。如图8所示，像素限定层150可以通过增加从像素电极310的边缘到像素电极310上的对电极330的距离来防止在像素电极310的边缘上出现电弧。像素限定层150可以包括有机材料，诸如聚酰亚胺(PI)或者六甲基二硅醚(HMDSO)；然而，本发明的示例性实施例不限于此。
OLED 300的中间层320可以包括低分子量材料或者聚合物材料。如果中间层320包括低分子量材料，则中间层320可以以单层或复合结构形成，所述复合结构包括空穴注入层(HIL)、空穴传输层(HTL)、发射层(EML)、电子传输层(ETL)和电子注入层(EIL)。中间层320可以包括各种有机材料，诸如铜酞菁(CuPc)、N,N'-二(1-萘基)-N,N'-二苯基联苯胺(NPB)和三(8-羟基喹啉)铝(Alq3)；然而，本发明的示例性实施例不限于此。可以通过蒸发法形成上述层；然而，本发明的示例性实施例不限于此。
当中间层320包括聚合物材料时，中间层320可以具有包括空穴传输层(HTL)和发射层(EML)的结构。空穴传输层(HTL)可以包括聚-(3,4)-乙烯-二氧噻吩(PEDOT)。发射层(EML)可以包括聚合物材料，诸如聚对苯撑乙烯(PPV)或者聚芴。然而，本发明的示例性实施例不限于此。中间层320可以通过利用丝网印刷法、喷墨印刷法或者激光诱导热成像(LITI)法形成；然而，本发明的示例性实施例不限于此。
中间层320可以包括各种结构。中间层320可以包括单体层。单体层可以设置在基本上全部多个像素电极310的上方。可选择地，中间层320可以包括被图案化为对应于每个像素电极310的多个层。
对电极330可以面向像素电极310。中间层320可以设置在对电极330和像素电极310之间。对电极330可以通过形成为单体而对应于多个像素电极310。对电极330可以设置在多个OLED上。例如，像素电极310可以图案化至每个像素。对电极330可以形成为将共电压施加到全部像素。对电极330可以为透明电极。可选择地，对电极330可以为反射电极。
空穴和电子可以分别从OLED 300的像素电极310和对电极330注入。空穴和电子可以在中间层320中结合。因此，可以从中间层320的发光层发出光。
OLED 300可能被外部水分或者氧气损坏。因此，薄膜包封层400可以覆盖OLED300。薄膜包封层400可以保护OLED 300免受外部水分或氧气影响。薄膜包封层400可以包括至少一个有机包封层。薄膜包封层400也可以包括至少一个无机包封层。例如，如图8所示，薄膜包封层400可以包括第一无机包封层410、有机包封层420和第二无机包封层430。
第一无机包封层410可以覆盖对电极330。第一无机包封层410可以包括氧化硅、氮化硅和/或氧氮化硅；然而，本发明的示例性实施例不限于此。可以在第一无机包封层410和对电极330之间插入另一层，例如，覆盖层。第一无机包封层410的形状可以根据设置在下面的结构的形状来形成。因此，如图8所示，第一无机包封层410的上表面可以不是基本平坦的。有机包封层420可以覆盖第一无机包封层410。然而，与第一无机包封层410不同，有机包封层420的上表面可以形成为基本平坦的。有机包封层420可以包括从由聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、聚碳酸酯、聚酰亚胺(PI)、聚乙烯磺酸盐、聚甲醛(POM)、聚芳酯和六甲基二硅醚(HMDSO)组成的组中选择的至少一种；然而，本发明的示例性实施例不限于此。第二无机包封层430可以覆盖有机包封层420。第二无机包封层430可以包括氧化硅、氮化硅和/或氧氮化硅；然而，本发明的示例性实施例不限于此。
由于薄膜包封层400可以具有包括第一无机包封层410、有机包封层420和第二无机包封层430的多层结构，所以尽管在薄膜包封层400中可能出现裂缝，通过多层结构裂缝在第一无机包封层410和有机包封层420之间或者在有机包封层420和第二无机包封层430之间也不会连接。因此，可以防止外部水分或者氧气进入OLED 300的渗透路径的形成，或者可以将渗透路径的形成最小化。
薄膜包封层400可以被密封基底所替代。密封基底可以包括玻璃。密封基底可以结合至密封剂。密封剂可以设置为围绕基底100。密封剂也可以设置为围绕显示区DA。偏振板、滤色器或者触摸面板可以进一步设置在薄膜包封层400上。可选择地，偏振板、滤色器或者触摸面板可以设置在密封基底上。
根据本发明的示例性实施例，第二光致抗蚀剂图案PR2可以形成为围绕栅电极213的侧壁。第二光致抗蚀剂图案PR2可以设置为防止在制造工艺中在栅电极213和半导体层211之间的短路。因此，可以形成高品质TFT和包括该TFT的显示设备。
尽管已经参照附图描述了本发明的一个或更多个示例性实施例，但是本领域普通技术人员将理解的是，在不脱离如由权利要求书限定的本发明的精神和范围的情况下，可做出形式上和细节上的各种改变。

Claims (20)

1.一种显示设备，所述显示设备包括：
薄膜晶体管；
平坦化膜，与所述薄膜晶体管叠置；
像素电极，设置在所述平坦化膜上方并连接至所述薄膜晶体管；
对电极，面向所述像素电极；以及
中间层，设置在所述像素电极和所述对电极之间，
其中，所述薄膜晶体管包括：半导体层，设置在基底上方并包括沟道区、源区和漏区；栅极绝缘膜，设置在所述半导体层上方并包括第一区和第二区，所述第二区设置在所述第一区的侧部处；栅电极，设置在所述第一区上方，其中，所述第一区的厚度不同于所述第二区的厚度以形成台阶形状。
2.根据权利要求1所述的显示设备，其中，所述第一区的上表面的面积大于所述栅电极的下表面的面积。
3.根据权利要求1所述的显示设备，其中，所述栅电极的下表面的端部与所述第一区的上表面的端部之间的距离在从5nm至1000nm的范围内。
4.根据权利要求1所述的显示设备，其中，所述第一区具有基本均匀的厚度。
5.根据权利要求1所述的显示设备，其中，所述第二区的所述厚度沿着远离所述第一区的方向减小。
6.根据权利要求1所述的显示设备，其中，所述半导体层包括氧化物半导体。
7.根据权利要求1所述的显示设备，其中，所述栅极绝缘膜不覆盖所述半导体层的两个边缘。
8.根据权利要求1所述的显示设备，所述显示设备还包括像素限定层，所述像素限定层暴露所述像素电极的第一区，并覆盖所述像素电极的边缘。
9.根据权利要求1所述的显示设备，其中，所述中间层包括有机发光层。
10.一种制造薄膜晶体管的方法，所述方法包括：
在基底上方形成半导体层；
在所述基底上顺序形成栅极绝缘材料层和栅电极材料层以覆盖所述半导体层；
在所述栅电极材料层上形成第一光致抗蚀剂图案；
通过使用所述第一光致抗蚀剂图案作为掩摸蚀刻所述栅电极材料层来形成栅电极；
形成覆盖所述栅电极的两个侧壁和上表面的第二光致抗蚀剂图案；以及
通过使用所述第二光致抗蚀剂图案作为掩模蚀刻所述栅极绝缘材料层来形成栅极绝缘膜。
11.根据权利要求10所述的方法，其中，通过使所述第一光致抗蚀剂图案回流来形成所述第二光致抗蚀剂图案。
12.根据权利要求10所述的方法，所述方法还包括执行传导工艺以增加所述半导体层的一部分的载流子浓度。
13.根据权利要求12所述的方法，其中，蚀刻所述栅极绝缘材料层的步骤包括干法蚀刻工艺，所述传导工艺使用在所述干法蚀刻工艺中使用的气体。
14.根据权利要求10所述的方法，其中，所述栅极绝缘膜包括第一区和设置在所述第一区的侧部处的第二区，所述第一区的厚度不同于所述第二区的厚度以形成台阶形状。
15.根据权利要求14所述的方法，其中，所述栅电极设置在所述第一区上，所述第一区的上表面的面积大于所述栅电极的下表面的面积。
16.根据权利要求14所述的方法，其中，所述第二区的所述厚度沿着远离所述第一区的方向减小。
17.根据权利要求10所述的方法，其中，所述半导体层包括氧化物半导体。
18.一种薄膜晶体管，所述薄膜晶体管包括：
基底；
半导体层，设置在所述基底上，所述半导体层包括沟道区、源区和漏区；
栅极绝缘膜，设置在所述半导体层上，所述栅极绝缘膜包括第一区和第二区，所述第二区与所述第一区接界；以及
栅电极，设置在所述第一区上，
其中，台阶形状形成在所述第二区和所述第一区相接处。
19.根据权利要求18所述的薄膜晶体管，其中，所述栅电极的下表面的端部与所述第一区的上表面的端部之间的距离在从5nm至1000nm的范围内。
20.根据权利要求18所述的薄膜晶体管，其中，所述第一区具有基本均匀的厚度。
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