CN107367926B - A kind of high-precision Pixel-level time-to-amplitude converter of wide dynamic range - Google Patents
A kind of high-precision Pixel-level time-to-amplitude converter of wide dynamic range Download PDFInfo
- Publication number
- CN107367926B CN107367926B CN201710750704.4A CN201710750704A CN107367926B CN 107367926 B CN107367926 B CN 107367926B CN 201710750704 A CN201710750704 A CN 201710750704A CN 107367926 B CN107367926 B CN 107367926B
- Authority
- CN
- China
- Prior art keywords
- input terminal
- source follower
- switch
- voltage
- pixels
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
A kind of high-precision Pixel-level time-to-amplitude converter of wide dynamic range, belongs to Analogous Integrated Electronic Circuits technical field.Pixel array including ramp signal generation module, triangular signal generation module and multiple blocks of pixels composition, ramp signal generation module is used to generate ramp signal RAMP and is output to the first input end of block of pixels, triangular signal generation module is used to generate triangular signal TRIANGLE and is output to the second input terminal of block of pixels, block of pixels is for sampling and obtaining ramp voltage and triangle wave voltage, the ramp voltage wherein sampled is used for a high position for quantization time, and the triangle wave voltage of sampling is used for the low level of quantization time.The present invention is capable of measuring the time interval in wide dynamic range while realizing the precise measurement time；And the circuit in block of pixels is fairly simple, the area of each block of pixels is simultaneously little, convenient for integrating time-to-amplitude converter TAC on a large scale on the same chip.
Description
Technical field
The invention belongs to Analogous Integrated Electronic Circuits technical fields, and in particular to a kind of Pixel-level time-to-amplitude converter TAC.
Background technique
Since the mankind find out the world, time interval measurement technology is just come into being, in the civilized history of mankind's more than one thousand years,
People constantly seek and continuously improve the new method of time interval measurement.In nowadays people's daily life, clock and watch, mobile phone etc. are just
Prompt tool has successfully met the demand that most people measure the time, however in some emerging fields, such as three-dimensional imaging skill
Art, traditional time counting mode have been far from satisfying requirement, in order to restore clearly 3-D image as far as possible, no
It only needs the result of time interval measurement to have very high precision, but also needs that there is wider dynamic range, this is to traditional
Time interval measurement technology brings great challenge.
Time-to-amplitude converter (Time-to-Amplitude Converter, TAC) is a kind of survey in integrated circuit fields
The method for measuring time interval.Conventional pixel grade time-to-amplitude converter TAC as shown in Figure 1, include ramp signal generation module and
Block of pixels is pushed in block of pixels the basic principle is that generating a ramp signal outside block of pixels, when in block of pixels
Stop signal STOP come interim, then sampling hold circuit sampling in block of pixels ramp signal corresponding voltage at this time is used
The size quantization time of sampled voltage every length.The amplitude of oscillation of obvious ramp signal is limited to supply voltage, in this case, when
Between amplitude converter TAC dynamic range and precision be difficult to balance, if wanting to realize high-precision time-to-amplitude converter TAC, that
The time of integration of ramp voltage must be very short, and the dynamic range of time-to-amplitude converter TAC will be very narrow；If wanting to realize wide dynamic
The time-to-amplitude converter TAC of state range, then the time of integration on slope will be very long, the precision of time-to-amplitude converter TAC
It will be very low.Therefore, application high-precision for wide dynamic range, such as 3 dimension imaging technology, conventional pixel grade time
Amplitude converter TAC is far from satisfying requirement.
Summary of the invention
There is the deficiency for being difficult to balance between dynamic range and precision for conventional pixel grade time-to-amplitude converter TAC
Place, the present invention propose a kind of novel Pixel-level time-to-amplitude converter TAC, same with wide dynamic range in high precision realizing
When but also with the low in energy consumption and small advantage of chip area.
The technical scheme is that
A kind of high-precision Pixel-level time-to-amplitude converter of wide dynamic range, the pixel including multiple blocks of pixels composition
Array, ramp signal generation module and triangular signal generation module,
The ramp signal generation module is used to generate ramp signal RAMP and is output to the first defeated of the block of pixels
Enter end, the triangular signal generation module is used to generate triangular signal TRIANGLE and is output to the of the block of pixels
Two input terminals, the block of pixels is for sampling and obtaining ramp voltage and triangle wave voltage；
The block of pixels includes the first source follower, the second source follower, first switch S1, second switch S2, first capacitor
C1 and the second capacitor C2,
First input end of the input terminal of first source follower as the block of pixels, the electricity of first switch S1 and first
Hold C1 series connection, series connection point exports the ramp voltage as the first output end of the block of pixels, and first switch S1's is another
The output end of one termination first source follower, the other end ground connection of first capacitor C1；
Second input terminal of the input terminal of second source follower as the block of pixels, the electricity of second switch S2 and second
Hold C2 series connection, series connection point exports the triangle wave voltage as the second output terminal of the block of pixels, second switch S2's
The output end of another termination second source follower, the other end ground connection of the second capacitor C2.
Specifically, first source follower and the second source follower are N-shaped source follower,
First source follower includes the first NMOS tube MN1 and the first current source IB1, the grid of the first NMOS tube MN1
Input terminal of the pole as first source follower, drain electrode connect supply voltage, output of the source electrode as first source follower
It holds and is grounded after passing through the first current source IB1；
Second source follower includes the second NMOS tube MN2 and the second current source IB2, the grid of the second NMOS tube MN2
Input terminal of the pole as second source follower, drain electrode connect supply voltage, output of the source electrode as second source follower
It holds and is grounded after passing through the second current source IB2.
Specifically, the ramp signal generation module include the first operational amplifier AMP1, second operational amplifier AMP2,
Third capacitor C3, third switch S3, the 4th switch S4 and third current source IB3,
The non-inverting input terminal of first operational amplifier AMP1 connects reference voltage VREF, and inverting input terminal is opened by third
The cathode of third current source IB3, the plus earth of third current source IB3 are connected after the S3 of pass；
Third capacitor C3 and the 4th switch S4 parallel connection are attempted by the inverting input terminal and output of the first operational amplifier AMP1
Between end；
The non-inverting input terminal of second operational amplifier AMP2 connects the output end of the first operational amplifier AMP1, output end
It connects its inverting input terminal and exports the ramp signal RAMP as the output end of the ramp signal generation module.
Specifically, the triangular signal generation module includes third operational amplifier AMP3, four-operational amplifier
AMP4, first comparator COMP1, the second comparator COMP2, the 4th current source IB4, the 5th current source IB5, the 5th switch S5,
6th switch S6, the 4th capacitor C4, control switch and rest-set flip-flop,
The cathode of 4th current source IB4 connects supply voltage, and anode connects one end of control switch；
The cathode of 5th current source IB5 connects the other end of control switch and is put by connecting third operation after the 5th switch S5
The inverting input terminal of big device AMP3, plus earth；
The non-inverting input terminal of third operational amplifier AMP3 connects reference voltage VREF, and output end connects first comparator
The homophase input of the inverting input terminal of COMP1, the non-inverting input terminal of the second comparator COMP2 and four-operational amplifier AMP4
End；
6th switch S6 and the 4th capacitor C4 parallel connection are attempted by the inverting input terminal and output of third operational amplifier AMP3
Between end；
The non-inverting input terminal of first comparator COMP1 connects upper limit voltage VH, and output end connects the R input of rest-set flip-flop
End；
The inverting input terminal of second comparator COMP2 connects lower voltage limit VL, and output end connects the S input of rest-set flip-flop
End；
The control terminal of the Q output connection control switch of rest-set flip-flop；
The output end of four-operational amplifier AMP4 connects its inverting input terminal and generates mould as the triangular signal
The output end of block exports the triangular signal TRIANGLE.
Specifically, the current value of the 4th current source IB4 is twice of the current value of the 5th current source IB5.
Specifically, the voltage value of the lower voltage limit VL is equal to the voltage value of the reference voltage VREF.
Specifically, the third switch S3 and the 5th switch S5 is controlled by time initial signal START, the 4th switch
S4 and the 6th switch S6 reset signal RESET control again, the first switch S1 and second switch S2 are by time termination signal
STOP control.
Specifically, first source follower and the second source follower are p-type source follower,
First source follower includes the first PMOS tube MP1 and the 6th current source IB6, the grid of the first PMOS tube MP1
Input terminal of the pole as first source follower, grounded drain, source electrode as first source follower output end and lead to
It crosses the 6th current source IB6 and is followed by supply voltage；
Second source follower includes the second PMOS tube MP2 and the 7th current source IB7, the grid of the second PMOS tube MP2
Input terminal of the pole as second source follower, grounded drain, source electrode as second source follower output end and lead to
It crosses the 7th current source IB7 and is followed by supply voltage.
The operation principle of the present invention is that:
When time initial signal START temporarily, to generate ramp signal RAMP and triangular wave letter respectively outside block of pixels
Number TRIANGLE, is then pushed in each block of pixels by buffer respectively.It is that two samplings keep electricity in block of pixels
Road, when time termination signal STOP comes temporarily, two sampling hold circuits difference sampling time termination signal STOP moment are corresponding
Ramp signal RAMP and triangular signal TRIANGLE voltage.The ramp voltage and triangular wave electricity then obtained according to sampling
The size of the voltage value of pressure judges time interval, wherein the ramp voltage sampled is used to judge the high position of time, the triangle of sampling
Wave voltage is used to judge the low level of time, and the precise measurement of wide dynamic range time interval can be realized.
The invention has the benefit that proposing a kind of novel wide dynamic range high-precision Pixel-level time-to-amplitude conversion
Device TAC while realizing the precise measurement time, and is capable of measuring the time interval in wide dynamic range；And in block of pixels
Circuit is fairly simple, and the area of each block of pixels is simultaneously little, convenient for integrated time-amplitude turns on a large scale on the same chip
Parallel operation TAC.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of conventional pixel grade time-to-amplitude converter TAC；
Fig. 2 is a kind of structure of the high-precision Pixel-level time-to-amplitude converter TAC of wide dynamic range provided by the invention
Schematic diagram；
Fig. 3 is ramp generator structural schematic diagram in embodiment；
Fig. 4 is the signal sequence control figure of ramp generator in embodiment；
Fig. 5 is the structural schematic diagram of embodiment intermediate cam wave producer；
Fig. 6 is the timing control figure of embodiment intermediate cam wave producer；
Fig. 7 is in embodiment using the structural schematic diagram of the block of pixels of N-shaped source follower；
Fig. 8 is the timing control figure of block of pixels in embodiment；
Fig. 9 is in embodiment using the structural schematic diagram of the block of pixels of p-type source follower.
Specific embodiment
A specific embodiment of the invention is described in the following with reference to the drawings and specific embodiments.
It is illustrated in figure 2 a kind of high-precision Pixel-level time-to-amplitude converter TAC of wide dynamic range provided by the invention
Structural schematic diagram compared with conventional pixel grade time-to-amplitude converter TAC, the present invention sampling ramp voltage quantization time
A high position, to judge that the time is in that section, the triangle wave voltage of sampling is used to the low level of quantization time.Due to only with oblique
Slope voltage judges which section the time is in, and does not need its precise quantification time, in this way can be the integral of ramp voltage
Time becomes very long, to realize big dynamic range；The triangle wave voltage of sampling can make the precision of time quantization become simultaneously
Must be very high, it just solves conventional pixel grade time-to-amplitude converter TAC problem encountered in this way, the present invention is described in detail below
Each module.
Ramp signal generation module in the present embodiment uses ramp generator, and Fig. 3 and Fig. 4 are ramp generator respectively
Structural schematic diagram and timing control figure, ramp generator include the first operational amplifier AMP1, second operational amplifier AMP2, the
Three capacitor C3, third switch S3, the 4th switch S4 and third current source IB3, the non-inverting input terminal of the first operational amplifier AMP1
Connect reference voltage VREF, cathode of the inverting input terminal by connection third current source IB3 after third switch S3, third electric current
The plus earth of source IB3；Third capacitor C3 and the 4th switch S4 parallel connection are attempted by the anti-phase input of the first operational amplifier AMP1
Between end and output end；The non-inverting input terminal of second operational amplifier AMP2 connects the output end of the first operational amplifier AMP1,
Its output end connects its inverting input terminal and exports the ramp signal as the output end of the ramp signal generation module
RAMP。
The basic principle of ramp generator is as follows, and when reset signal RESET is effective, third capacitor C3 is short-circuited, and first
Operational amplifier AMP1 is connected into the form of unit gain negative-feedback, and the output end of the first operational amplifier AMP1 is set to base at this time
Quasi- voltage VREF.
While reset signal RESET becomes low from height, time initial signal START from low to high, at this time first
Operational amplifier AMP1 and third capacitor C3 forms a first integrator, if the gain of amplifier and bandwidth are sufficiently large, then this
When first integrator output end will generate an ideal slope, the variation relation of voltage V (t) t at any time is:
Wherein I1 is the current value of third current source IB3, when time initial signal START is low by height displacement, at this time not
There is electric current to flow through third capacitor C3 again, first integrator output end voltage will remain unchanged, if time initial signal START is height
Level time length is T, i.e. the effective time of first integrator charging is T, then the electricity after first integrator output end is stable
Pressure are as follows:
Since the driving capability of ramp generator is not strong enough, very big capacitive load can not be driven, it is therefore desirable to the second fortune
It calculates amplifier AMP2 and makees buffer, match the load of front stage.Second operational amplifier AMP2 is connected into unit gain negative-feedback
Form, output end voltage follows input terminal voltage to change and change, if the gain of second operational amplifier AMP2 and bandwidth are enough
Height, then output end voltage can be completely the same with input terminal voltage, therefore, second operational amplifier AMP2 can completely by
The slope that front stage circuits generate is pushed in block of pixels.
The present embodiment intermediate cam wave signal generator module uses triangular-wave generator, and Fig. 5 and Fig. 6 are triangular wave respectively
The structural schematic diagram and timing control figure of device, triangular-wave generator include third operational amplifier AMP3, four-operational amplifier
AMP4, first comparator COMP1, the second comparator COMP2, the 4th current source IB4, the 5th current source IB5, the 5th switch S5,
The cathode of 6th switch S6, the 4th capacitor C4, control switch and rest-set flip-flop, the 4th current source IB4 connects supply voltage, anode
Connect one end of control switch；The cathode of 5th current source IB5 connects the other end of control switch and by connecting after the 5th switch S5
The inverting input terminal of third operational amplifier AMP3, plus earth；The non-inverting input terminal of third operational amplifier AMP3 connects
Reference voltage VREF, output end connect the inverting input terminal of first comparator COMP1, the second comparator COMP2 it is same mutually defeated
Enter end and the non-inverting input terminal of four-operational amplifier AMP4；6th switch S6 and the 4th capacitor C4 parallel connection are attempted by third operation
Between the inverting input terminal and output end of amplifier AMP3；The non-inverting input terminal of first comparator COMP1 connects upper limit voltage VH,
The R input of its output end connection rest-set flip-flop；The inverting input terminal of second comparator COMP2 connects lower voltage limit VL, defeated
The S input terminal of outlet connection rest-set flip-flop；The control terminal of the Q output connection control switch of rest-set flip-flop；4th operation amplifier
The output end of device AMP4 connects its inverting input terminal and as the output end of triangular signal generation module output described three
Angle wave signal TRIANGLE.Wherein the current value of the 4th current source IB4 is twice of the current value of the 5th current source IB5, so that
Triangular wave charging time and discharge time are equal.
The basic principle of triangular signal generator is as follows, while reset signal RESET is effective, time initial signal
START is low level, similar with the principle on slope at this time, and third operational amplifier AMP3 is connected into the shape of current potential gain negative feedback
Formula, output end voltage are set to reference voltage VREF.
Similar with slope, third operational amplifier AMP3 and the 4th capacitor C4 form a second integral device, reset signal
RESET and time initial signal START are inverted simultaneously, at this time since the Q output of rest-set flip-flop is low level, then at this time the 4th
The electric current 2I of current source IB4 does not flow through second integral device, and the electric current I of only the 5th current source IB5 extracts electric current, second integral
Device output end will generate upward oblique wave, i.e., second integral device output voltage is at this time
Wherein, I2 is the current value of the 5th current source IB5, when output end voltage reaches upper limit voltage VH, at this time first
Comparator COMP1 output end will be inverted to low level, the i.e. R=0 of rest-set flip-flop from high level, due to the second comparator COMP2
Output end voltage maintain high level constant, i.e. the S=1 of rest-set flip-flop, then the Q output of rest-set flip-flop will be reversed to high electricity
Flat, i.e. Q=1, at this point, the electric current of the 4th current source IB4 also begins to flow through second integral device, two strands of electric currents flow through the second product simultaneously
Divide device, since the electric current of the 4th current source IB4 is twice of the 5th current source IB5 electric current, equivalent total current is downward
It pours into, size is the electric current of I, and second integral device output voltage constantly declines at this time, generates downward oblique wave, then has
When second integral device output voltage is again below upper limit voltage VH, first comparator COMP1 output end voltage is by low
Level overturning is high level, and the R=1 of rest-set flip-flop, S=1, rest-set flip-flop are in hold mode at this time, and Q output remains height
Level is constant, and since the conversion process time is very short, the overturning of first comparator COMP1 output voltage shows as burst pulse letter
Number.
When second integral device output end voltage drops to lower voltage limit VL, the second comparator COMP2 output end is turned to
Low level, the i.e. S=0 of rest-set flip-flop, since the output end voltage of first comparator COMP1 maintains high level constant, i.e. RS touching
The R=1 of device is sent out, then rest-set flip-flop Q output will overturn as low level, i.e. Q=0, at this point, the electric current of the 4th current source IB4
2I shutdown, is no longer flow through second integral device, and the electric current I of only the 5th current source IB5 extracts electric current, the output of second integral device at this time
End will generate upward oblique wave, i.e. second integral device output voltage at this time
Similar, triangular wave output voltage can be higher than lower voltage limit VL again, the second comparator COMP2 output end voltage by
Low level overturning is high level, and the R=1 of rest-set flip-flop, S=1, rest-set flip-flop are in hold mode at this time, and Q output remains
Low level is constant, and since the conversion process time is very short, the overturning of the second comparator COMP2 output voltage also shows as a burst pulse
Signal.
The bias voltage level lower voltage limit of the bias voltage VREF of third operational amplifier AMP3 and the second comparator COMP2
VL is same value, i.e.,
VREF=VL (6)
The process that an integral rises so just is repeated at this time, so is repeated down, is just produced triangular wave.
When the time, initial signal START became low from height, there is no electric currents to flow through the 4th capacitor C4, and second integral device is defeated
Outlet is maintained a certain voltage and remains unchanged.
The effect of four-operational amplifier AMP4 is similar with ramp generator, matches the load of front stage, by generation
Triangular wave is pushed in each pixel.
Fig. 7 is using the circuit structure diagram of the block of pixels of N-shaped source follower, and the first source follower includes the first NMOS tube MN1
With the first current source IB1, input terminal of the grid of the first NMOS tube MN1 as first source follower, drain electrode connects electricity
Source voltage, source electrode as first source follower output end and by being grounded after the first current source IB1；Second source with
Device includes the second NMOS tube MN2 and the second current source IB2, and the grid of the second NMOS tube MN2 is as second source follower
Input terminal, drain electrode connects supply voltage, source electrode as second source follower output end and pass through the second current source IB2
After be grounded.
Fig. 9 is using the circuit structure diagram of the block of pixels of p-type source follower, and the first source follower includes the first PMOS tube MP1
With the 6th current source IB6, input terminal of the grid of the first PMOS tube MP1 as the first source follower, grounded drain, source electrode work
For the first source follower output end and supply voltage is followed by by the 6th current source IB6；Second source follower includes the second PMOS tube
MP2 and the 7th current source IB7, input terminal of the grid of the second PMOS tube MP2 as the second source follower, grounded drain, source
Pole as the second source follower output end and supply voltage is followed by by the 7th current source IB7.
Timing control figure in Fig. 8 block of pixels, the effect of source follower are when the switching of late-class circuit is isolated to preceding
The influence of grade circuit, switch and capacitor constitute a simple sampling hold circuit, when time termination signal STOP is high level,
Voltage constantly follows the voltage of oblique wave and triangular wave on capacitor, when time termination signal STOP be switched to by high level it is low level
Moment, the voltage on capacitor no longer change with ramp signal RAMP and the corresponding voltage of triangular signal TRIANGLE,
That is sampling hold circuit sampling time termination signal STOP switching moment ramp signal RAMP and TRIANGLE pairs of triangular signal
The voltage answered quantifies the voltage on sampling capacitance respectively, can obtain time initial signal START and time termination signal
The time interval of STOP, the result of such time quantization not only have very high precision, while but also with very wide dynamic range.
Circuit in block of pixels is only made of source follower and simple sampling hold circuit, block of pixels each so only need compared with
Low power consumption and chip area can be realized.
Wide dynamic range cannot be achieved for tradition split-second precision amplitude converter TAC in the present invention, and width dynamic model
High-precision cannot be achieved in the time-to-amplitude converter TAC enclosed, proposes a high position for a kind of ramp voltage quantization time with sampling,
With the high-precision time-to-amplitude converter TAC of the wide dynamic range of the low level of the triangle wave voltage quantization time of sampling, so just
It is realizing that time measurement is high-precision simultaneously, and big dynamic range may be implemented, simultaneously as the circuit ratio in block of pixels
Relatively simple, the area of each block of pixels is simultaneously little, convenient for integrating TAC on a large scale on the same chip, can realize in this way
Wide dynamic range high-precision Pixel-level TAC.
Those of ordinary skill in the art will understand that the embodiments described herein, which is to help reader, understands this hair
Bright principle, it should be understood that protection scope of the present invention is not limited to such specific embodiments and embodiments.This field
Those of ordinary skill disclosed the technical disclosures can make according to the present invention and various not depart from the other each of essence of the invention
The specific variations and combinations of kind, these variations and combinations are still within the scope of the present invention.
Claims (8)
1. a kind of high-precision Pixel-level time-to-amplitude converter of wide dynamic range, the pixel battle array including multiple blocks of pixels composition
Column and ramp signal generation module, which is characterized in that the time-to-amplitude converter further includes triangular signal generation module,
The ramp signal generation module is used to generate ramp signal (RAMP) and is output to the first input of the block of pixels
End, the triangular signal generation module are used to generate triangular signal (TRIANGLE) and are output to the of the block of pixels
Two input terminals, the block of pixels is for sampling and obtaining ramp voltage and triangle wave voltage；
The block of pixels includes the first source follower, the second source follower, first switch (S1), second switch (S2), first capacitor
(C1) and the second capacitor (C2),
First input end of the input terminal of first source follower as the block of pixels, first switch (S1) and first capacitor
(C1) it connects, series connection point exports the ramp voltage as the first output end of the block of pixels, first switch (S1)
The output end of another termination first source follower, the other end ground connection of first capacitor (C1)；
Second input terminal of the input terminal of second source follower as the block of pixels, second switch (S2) and the second capacitor
(C2) it connects, series connection point exports the triangle wave voltage, second switch (S2) as the second output terminal of the block of pixels
Another termination second source follower output end, the second capacitor (C2) the other end ground connection.
2. the high-precision Pixel-level time-to-amplitude converter of wide dynamic range according to claim 1, which is characterized in that institute
It states the first source follower and the second source follower is N-shaped source follower,
First source follower includes the first NMOS tube (MN1) and the first current source (IB1), first NMOS tube (MN1)
Input terminal of the grid as first source follower, drain electrode connect supply voltage, and source electrode is defeated as first source follower
Outlet is simultaneously grounded by the first current source (IB1) afterwards；
Second source follower includes the second NMOS tube (MN2) and the second current source (IB2), second NMOS tube (MN2)
Input terminal of the grid as second source follower, drain electrode connect supply voltage, and source electrode is defeated as second source follower
Outlet is simultaneously grounded by the second current source (IB2) afterwards.
3. the high-precision Pixel-level time-to-amplitude converter of wide dynamic range according to claim 1, which is characterized in that institute
State ramp signal generation module include the first operational amplifier (AMP1), second operational amplifier (AMP2), third capacitor (C3),
Third switchs (S3), the 4th switch (S4) and third current source (IB3),
The non-inverting input terminal of first operational amplifier (AMP1) connects reference voltage (VREF), and inverting input terminal is opened by third
Close the cathode that (S3) connects third current source (IB3) afterwards, the plus earth of third current source (IB3)；
Third capacitor (C3) and the 4th switch (S4) parallel connection are attempted by the inverting input terminal of the first operational amplifier (AMP1) and defeated
Between outlet；
The output end of the non-inverting input terminal connection the first operational amplifier (AMP1) of second operational amplifier (AMP2), output end
It connects its inverting input terminal and exports the ramp signal (RAMP) as the output end of the ramp signal generation module.
4. the high-precision Pixel-level time-to-amplitude converter of wide dynamic range according to claim 1, which is characterized in that institute
Stating triangular signal generation module includes third operational amplifier (AMP3), four-operational amplifier (AMP4), first comparator
(COMP1), the second comparator (COMP2), the 4th current source (IB4), the 5th current source (IB5), the 5th switch (S5), the 6th open
(S6), the 4th capacitor (C4), control switch and rest-set flip-flop are closed,
The cathode of 4th current source (IB4) connects supply voltage, and anode connects one end of control switch；
The cathode of 5th current source (IB5) connects the other end of control switch and connects third operation afterwards by the 5th switch (S5) and puts
The inverting input terminal of big device (AMP3), plus earth；
The non-inverting input terminal of third operational amplifier (AMP3) connects reference voltage (VREF), and output end connects first comparator
(COMP1) inverting input terminal, the non-inverting input terminal of the second comparator (COMP2) and the same phase of four-operational amplifier (AMP4)
Input terminal；
6th switch (S6) and the 4th capacitor (C4) parallel connection are attempted by the inverting input terminal of third operational amplifier (AMP3) and defeated
Between outlet；
The non-inverting input terminal of first comparator (COMP1) connects upper limit voltage (VH), and output end connects the R input of rest-set flip-flop
End；
The inverting input terminal of second comparator (COMP2) connects lower voltage limit (VL), and output end connects the S input of rest-set flip-flop
End；
The control terminal of the Q output connection control switch of rest-set flip-flop；
The output end of four-operational amplifier (AMP4) connects its inverting input terminal and as the triangular signal generation module
Output end export the triangular signal (TRIANGLE).
5. the high-precision Pixel-level time-to-amplitude converter of wide dynamic range according to claim 4, which is characterized in that institute
The current value for stating the 4th current source (IB4) is twice of current value of the 5th current source (IB5).
6. the high-precision Pixel-level time-to-amplitude converter of wide dynamic range according to claim 5, which is characterized in that institute
The voltage value for stating lower voltage limit (VL) is equal to the voltage value of the reference voltage (VREF).
7. the high-precision Pixel-level time-to-amplitude converter of wide dynamic range according to claim 3 or 4, feature exist
In the third switch (S3) and the 5th switch (S5) are controlled by time initial signal (START), (S4) and the 6th switch (S6)
It is controlled by reset signal (RESET), the first switch (S1) and second switch (S2) are controlled by time termination signal (STOP)
System.
8. the high-precision Pixel-level time-to-amplitude converter of wide dynamic range according to claim 1, which is characterized in that institute
It states the first source follower and the second source follower is p-type source follower,
First source follower includes the first PMOS tube (MP1) and the 6th current source (IB6), first PMOS tube (MP1)
Input terminal of the grid as first source follower, grounded drain, source electrode as first source follower output end simultaneously
Supply voltage is followed by by the 6th current source (IB6)；
Second source follower includes the second PMOS tube (MP2) and the 7th current source (IB7), second PMOS tube (MP2)
Input terminal of the grid as second source follower, grounded drain, source electrode as second source follower output end simultaneously
Supply voltage is followed by by the 7th current source (IB7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710750704.4A CN107367926B (en) | 2017-08-28 | 2017-08-28 | A kind of high-precision Pixel-level time-to-amplitude converter of wide dynamic range |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710750704.4A CN107367926B (en) | 2017-08-28 | 2017-08-28 | A kind of high-precision Pixel-level time-to-amplitude converter of wide dynamic range |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107367926A CN107367926A (en) | 2017-11-21 |
| CN107367926B true CN107367926B (en) | 2019-05-21 |
Family
ID=60312276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710750704.4A Active CN107367926B (en) | 2017-08-28 | 2017-08-28 | A kind of high-precision Pixel-level time-to-amplitude converter of wide dynamic range |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107367926B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110568749B (en) * | 2019-08-30 | 2021-04-09 | 华中师范大学 | Time-to-digital converter circuit, time-to-digital converter device, time-to-digital converter apparatus, and method of controlling time-to-digital converter device |
| CN113485506B (en) * | 2021-07-06 | 2022-05-17 | 一念传感科技(深圳)有限公司 | Voltage current generator, generating method and generator application system |
-
2017
- 2017-08-28 CN CN201710750704.4A patent/CN107367926B/en active Active
Non-Patent Citations (6)
| Title |
|---|
| A 32x32-pixel array with in-pixel photon counting and arrival time measurement in the analog domain;David Stoppa et.al.;《2009 Proceedings of ESSCIRC》;20090918;第2-4页 * |
| A 9.8 μm sample and hold time to amplitude converter CMOS SPAD pixel;Luca Parmesan et.al.;《2014 44th European Solid State Device Research Conference (ESSDERC)》;20140926;全文 * |
| A pixel front-end ASIC in 0.13 μm CMOS for the NA62 experiment with on pixel 100 ps Time-to-Digital Converter;S. Martoiu et.al.;《2009 IEEE Nuclear Science Symposium Conference Record (NSS/MIC)》;20091101;全文 * |
| DC/DC变换器中的斜坡补偿法扩展及其理论分析;杨金;《盐城工学院学报（自然科学版）》;20071231;全文 * |
| High precision time-to-amplitude converter for diffuse optical tomography applications;Moez Kanoun et.al.;《2008 International Conference on Design&Technology of Integrated Systems in Nanoscale Era》;20081231;全文 * |
| Implementation of a High-Precision and Wide-Range;Jin Wu et.al.;《IEEE Transactions on Circuits and Systems II: Express Briefs》;20160415;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107367926A (en) | 2017-11-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103546123B (en) | A kind of relaxation oscillator of high linearity | |
| CN105842526B (en) | A kind of zero current detecting circuit and method and voltage conversion circuit | |
| CN108574410B (en) | Realize the circuit and method of self-adaptable slop compensation quick high accuracy | |
| CN105301284B (en) | A kind of low power consumption digital accelerometer interface circuit system | |
| CN107367926B (en) | A kind of high-precision Pixel-level time-to-amplitude converter of wide dynamic range | |
| CN108023557B (en) | Common mode feedback structure of switch capacitor | |
| CN103023461A (en) | RC (remote control) oscillating circuit | |
| CN102931913B (en) | High-precision oscillator | |
| CN104821716A (en) | Constant turn-on time controller | |
| CN103605397A (en) | Voltage follower circuit | |
| CN102394565A (en) | Oscillating circuit and oscillating system | |
| CN103279162B (en) | Low-power-consumption reference voltage buffer based on assembly line ADC | |
| CN101281792A (en) | Sampling-hold circuit | |
| CN104333352A (en) | Ramp signal generating circuit and image sensor | |
| Yue et al. | Performance optimization of SSHC rectifiers for piezoelectric energy harvesting | |
| Zhao et al. | Parallel synchronized septuple bias-flip circuit for piezoelectric energy harvesting enhancement | |
| CN106208981A (en) | A kind of infrared image sensor input stage electric capacity trsanscondutance amplifier structure | |
| CN204156831U (en) | Ramp generator and imageing sensor | |
| CN100433515C (en) | Charge pump device | |
| CN203588106U (en) | Improved voltage following circuit | |
| CN105103444B (en) | Signal output apparatus | |
| CN103152048A (en) | Differential input successive approximation type analog-digital converter | |
| CN102882374A (en) | Mixed-signal pseudo-three-type compensation circuit with optimized area | |
| CN103001607B (en) | There is the triangular wave generator of the difference output synchronous with external timing signal | |
| CN114071034B (en) | Composite dielectric gate double-transistor pixel reading circuit based on switched capacitor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |