CN101281792A - Sampling-hold circuit - Google Patents
Sampling-hold circuit Download PDFInfo
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- CN101281792A CN101281792A CNA200710065177XA CN200710065177A CN101281792A CN 101281792 A CN101281792 A CN 101281792A CN A200710065177X A CNA200710065177X A CN A200710065177XA CN 200710065177 A CN200710065177 A CN 200710065177A CN 101281792 A CN101281792 A CN 101281792A
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- hold circuit
- operational amplifier
- sampling
- sampling hold
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Abstract
The present invention discloses a sampling hold circuit, which comprises an operation amplifier, a sampling capacitor Cs, an additional capacitor C1, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4; the top electrode plate of the sampling capacitor Cs is connected to the inverted input terminal of the operation amplifier, and the bottom electrode plate of the sampling capacitor Cs is connected to the first switch S1; the input voltage from the sampling hold circuit is connected via the first switch S1 and the sampling capacitor Cs to the inverted input terminal of the operation amplifier; the top electrode plate of the additional capacitor C1 is connected to the non-inverted input terminal of the operation amplifier, and the bottom electrode plate of the additional capacitor C1 is connected to a fixed electric level; the input voltage from the sampling hold circuit is connected via the fourth switch S4 and the additional capacitor C1 to the fixed electric level; the input voltage from the sampling hold circuit is connected via S1 and S3 to the output terminal of the operation amplifier; the sampling capacitors Cs and S2 are connected via S1 to the output terminal of the operation amplifier, and are connected via S4 to the non-inverted input terminal of the operation amplifier. The sampling hold circuit in the present invention can effectively reduce power consumption.
Description
Technical field
The present invention relates to the sampling hold circuit technical field in the production line analog-digital converter (ADC), relate in particular to a kind of low-power consumption sampling hold circuit of using gain compensation technique, reduced the requirement of sampling hold circuit significantly, reduced the power consumption of sampling hold circuit the operational amplifier gain.
Background technology
Along with the market expansion of portable type electronic product, more and more higher to the low-power consumption requirement of circuit.As shown in Figure 1, Fig. 1 is the structural representation of traditional sampling hold circuit.Ph1 and ph2 are the two-phase clock that do not overlap, and ph1e represents to shift to an earlier date a little than ph1 negative edge.In the ph1 phase, sampling capacitance Cs sole plate connects input voltage vin, top crown connects the inverting input of operational amplifier, at this moment operational amplifier inverting input and output terminal are connected together becomes a unity gain structure, the offset voltage of operational amplifier is represented by a voltage source V os who is connected on inverting input that in the drawings the DC current gain of supposing operational amplifier is A
0, and ignore other non-ideal factor, at this moment output voltage is:
Sampling finished when ph1e became low level.In the ph2 phase, sampling capacitance Cs top crown connects the operational amplifier inverting input, and the sole plate connects operational amplifier output terminal, and at this moment remained unchanged by the electric charge of electric capacity to get that output voltage is:
The error of the output voltage that is caused by the operational amplifier finite gain is Vin/ (1+A
0), approximate DC current gain with operational amplifier is inversely proportional to.As seen, design a high-precision sampling hold circuit, need the operational amplifier of a high dc gain.And the operational amplifier of a high-gain needs the structure of more complicated usually, and power consumption is than higher.Simultaneously, reset because each sampling phase operational amplifier all will be connected into the unity gain structure, set up mutually keeping, when input and common mode electrical level differ far away, keep setting up mutually and need the experience large-signal to set up process and small-signal is set up process, speed is set up in influence.
So, improve the structure of sample sampling/retaining circuit, reach higher precision with simple low gaining operating amplifier, thereby the power consumption that reduces sampling hold circuit significantly is very necessary.
Summary of the invention
(1) technical matters that will solve
The object of the present invention is to provide a kind of structure of sampling hold circuit, so that traditional sampling hold circuit is improved, when having same precision, reduce the power consumption of sampling hold circuit with traditional sampling hold circuit.
(2) technical scheme
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of sampling hold circuit, this sampling hold circuit comprise an operational amplifier, a sampling capacitance Cs, an additional capacitor C1, first switch S 1, second switch S2, the 3rd switch S 3 and the 4th switch S 4;
The top crown of described sampling capacitance Cs connects the inverting input of operational amplifier, and the sole plate connects first switch S 1, and the input voltage of described sampling hold circuit connects the inverting input of operational amplifier by first switch S 1 and sampling capacitance Cs;
The top crown of described additional capacitor C1 connects the in-phase input end of operational amplifier, and the sole plate connects fixed level, and the input voltage of described sampling hold circuit connects fixed level by the 4th switch S 4 and additional capacitor C1;
The input voltage of described sampling hold circuit connects the output terminal of operational amplifier by first switch S 1 and the 3rd switch S 3, connect the output terminal of operational amplifier by first switch S 1, sampling capacitance Cs and second switch S2, and connect the in-phase input end of operational amplifier by the 4th switch S 4.
In the such scheme, described second switch S2 is connected between the inverting input and output terminal of operational amplifier, and described the 4th switch S 4 is connected between the in-phase input end of the input of sampling hold circuit and operational amplifier.
In the such scheme, sample phase at described sampling hold circuit, first switch S 1, second switch S2 and the 4th switch S 4 closures, the 3rd switch S 3 disconnects, the sole plate of described sampling capacitance Cs connects the input of sampling hold circuit, the inverting input of operational amplifier is connected with output terminal, and in-phase input end is connected with the input of sampling hold circuit, thereby makes the output tracking input of sampling hold circuit.
In the such scheme, in the maintenance stage of described sampling hold circuit, first switch S 1, second switch S2 and the 4th switch S 4 disconnect, the 3rd switch S 3 closures, the input of operational amplifier in-phase input end and sampling hold circuit disconnects, voltage on the additional capacitor C1 remains a magnitude of voltage when finishing mutually, and the inverting input of operational amplifier and the output terminal of operational amplifier disconnect, and the output terminal that the sole plate of sampling capacitance Cs is received operational amplifier keeps.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, utilizes the present invention, owing to adopt simple low gaining operating amplifier structure can reach the precision that the traditional sampling holding circuit adopts high gain operational amplifier, thereby under the situation that guarantees the sampling hold circuit precision, effectively reduced the power consumption of sampling hold circuit.
2, utilize the present invention, because the output of sampling hold circuit is imported at sampling phase output tracking, keep output mutually only to experience small-signal and set up process, so effectively raise sampling hold circuit in the speed of setting up that keeps phase.
3, utilize the present invention, because operational amplifier is simple in structure, effectively shortened the design cycle, the area that also reduced chip has greatly reduced cost.
Description of drawings
Fig. 1 is the structural representation of traditional sampling hold circuit;
Fig. 2 is the structural representation of sampling hold circuit of the present invention;
Fig. 3 is the sequential relationship synoptic diagram of sampling hold circuit.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 2, Fig. 2 is the structural representation of sampling hold circuit of the present invention.This sampling hold circuit comprises an operational amplifier, a sampling capacitance Cs, an additional capacitor C1, first switch S 1, second switch S2, the 3rd switch S 3 and the 4th switch S 4.
Wherein, the top crown of sampling capacitance Cs connects the inverting input of operational amplifier, and the sole plate connects first switch S 1, and the input voltage of sampling hold circuit connects the inverting input of operational amplifier by first switch S 1 and sampling capacitance Cs.The top crown of additional capacitor C1 connects the in-phase input end of operational amplifier, and the sole plate connects fixed level, and the input voltage of sampling hold circuit connects fixed level by the 4th switch S 4 and additional capacitor C1.The input voltage of sampling hold circuit connects the output terminal of operational amplifier by first switch S 1 and the 3rd switch S 3, connect the output terminal of operational amplifier by first switch S 1, sampling capacitance Cs and second switch S2, and connect the in-phase input end of operational amplifier by the 4th switch S 4.
Sample phase at described sampling hold circuit, first switch S 1, second switch S2 and the 4th switch S 4 closures, the 3rd switch S 3 disconnects, input voltage samples on the sole plate of two electric capacity simultaneously, the inverting input of operational amplifier and output short circuit, make output voltage follow the tracks of input voltage, suppose that there is an offset voltage Vos in the inverting input of operational amplifier, the DC current gain of operational amplifier is A
0, output voltage at this moment is:
The sole plate of described sampling capacitance Cs connects the input of sampling hold circuit, the inverting input of operational amplifier is connected with output terminal, in-phase input end is connected with the input of sampling hold circuit, thereby make the output tracking input of sampling hold circuit, the voltage error that operational amplifier finite gain simultaneously causes is stored on sampling capacitance Cs and the additional capacitor C1.
Because output tracking input in sampling phase sampler holding circuit, reset mutually and compare in sampling with the traditional sampling holding circuit, sampling hold circuit of the present invention has reduced operational amplifier and has set up the required time keeping the phase operational amplifier not experience large-signal foundation.
In the maintenance stage of described sampling hold circuit, first switch S 1, second switch S2 and the 4th switch S 4 disconnect, and the 3rd switch S 3 closures because the output voltage at two electric capacity two ends all remains unchanged, can calculate output voltage at this moment:
The error of the output voltage that is caused by the finite gain of operational amplifier is Vin/ (1+A
0)
2, square being inversely proportional to of approximate and operational amplifier DC current gain, promptly this sampling hold circuit can reach the traditional sampling holding circuit in theory and adopts gain to be A
0 2The identical precision of operational amplifier.So greatly reduce the difficulty of operational amplifier design, make the compromise ratio of operational amplifier between gain, bandwidth, power consumption, the amplitude of oscillation be easier to.
The input of operational amplifier in-phase input end and sampling hold circuit disconnects, voltage on the additional capacitor C1 remains a magnitude of voltage when finishing mutually, the inverting input of operational amplifier and the output terminal of operational amplifier disconnect, the output terminal that the sole plate of sampling capacitance Cs is received operational amplifier keeps, because sampling has been stored the voltage error that is caused by the operational amplifier finite gain on two electric capacity mutually, so keep the error of the output voltage that causes by the operational amplifier finite gain to reduce greatly, with square being inversely proportional to that operational amplifier gains.
The sequential of sampling hold circuit as shown in Figure 3, the action of switch S 1 lags behind S2 and S4.After S2 and S4 disconnected, under the negligible situation of stray capacitance, the sole plate electric charge of Cs remained unchanged, and the voltage at Cs two ends is also just fixing, so the closure of the disconnection of S1 and S3 can not exert an influence to final output voltage.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. a sampling hold circuit is characterized in that, this sampling hold circuit comprises an operational amplifier, a sampling capacitance Cs, an additional capacitor C1, first switch S 1, second switch S2, the 3rd switch S 3 and the 4th switch S 4;
The top crown of described sampling capacitance Cs connects the inverting input of operational amplifier, and the sole plate connects first switch S 1, and the input voltage of described sampling hold circuit connects the inverting input of operational amplifier by first switch S 1 and sampling capacitance Cs;
The top crown of described additional capacitor C1 connects the in-phase input end of operational amplifier, and the sole plate connects fixed level, and the input voltage of described sampling hold circuit connects fixed level by the 4th switch S 4 and additional capacitor C1;
The input voltage of described sampling hold circuit connects the output terminal of operational amplifier by first switch S 1 and the 3rd switch S 3, connect the output terminal of operational amplifier by first switch S 1, sampling capacitance Cs and second switch S2, and connect the in-phase input end of operational amplifier by the 4th switch S 4.
2. sampling hold circuit according to claim 1, it is characterized in that, described second switch S2 is connected between the inverting input and output terminal of operational amplifier, and described the 4th switch S 4 is connected between the in-phase input end of the input of sampling hold circuit and operational amplifier.
3. sampling hold circuit according to claim 1, it is characterized in that, sample phase at described sampling hold circuit, first switch S 1, second switch S2 and the 4th switch S 4 closures, the 3rd switch S 3 disconnects, and the sole plate of described sampling capacitance Cs connects the input of sampling hold circuit, and the inverting input of operational amplifier is connected with output terminal, in-phase input end is connected with the input of sampling hold circuit, thereby makes the output tracking input of sampling hold circuit.
4. sampling hold circuit according to claim 1, it is characterized in that, in the maintenance stage of described sampling hold circuit, first switch S 1, second switch S2 and the 4th switch S 4 disconnect, the 3rd switch S 3 closures, the input of operational amplifier in-phase input end and sampling hold circuit disconnects, voltage on the additional capacitor C1 remains a magnitude of voltage when finishing mutually, the inverting input of operational amplifier and the output terminal of operational amplifier disconnect, and the output terminal that the sole plate of sampling capacitance Cs is received operational amplifier keeps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200710065177XA CN101281792A (en) | 2007-04-05 | 2007-04-05 | Sampling-hold circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200710065177XA CN101281792A (en) | 2007-04-05 | 2007-04-05 | Sampling-hold circuit |
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| CN101281792A true CN101281792A (en) | 2008-10-08 |
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| CNA200710065177XA Pending CN101281792A (en) | 2007-04-05 | 2007-04-05 | Sampling-hold circuit |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420612A (en) * | 2011-12-16 | 2012-04-18 | 电子科技大学 | Time-interleaving analogue-to-digital converter capable of suppressing sampling time mismatching |
| CN104300924A (en) * | 2014-10-17 | 2015-01-21 | 中国科学院微电子研究所 | Envelope tracking power source and envelope tracking radio-frequency power amplifier |
| CN106331542A (en) * | 2016-08-29 | 2017-01-11 | 长春长光辰芯光电技术有限公司 | High dynamic focal plane readout circuit and sampling method thereof |
| CN107070411A (en) * | 2017-01-04 | 2017-08-18 | 深圳市紫光同创电子有限公司 | A kind of unit gain sample circuit and the method for improving sampling precision |
| CN107911118A (en) * | 2017-12-08 | 2018-04-13 | 成都聚利中宇科技有限公司 | A kind of multi-channel sampling tracking keeps equipment and signal sampling method |
| CN108141220A (en) * | 2015-10-30 | 2018-06-08 | 索尼半导体解决方案公司 | The MOS linear resistors of state machine control |
| CN112600543A (en) * | 2020-12-09 | 2021-04-02 | 屹世半导体(上海)有限公司 | Sampling circuit based on switch control |
-
2007
- 2007-04-05 CN CNA200710065177XA patent/CN101281792A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420612A (en) * | 2011-12-16 | 2012-04-18 | 电子科技大学 | Time-interleaving analogue-to-digital converter capable of suppressing sampling time mismatching |
| CN104300924A (en) * | 2014-10-17 | 2015-01-21 | 中国科学院微电子研究所 | Envelope tracking power source and envelope tracking radio-frequency power amplifier |
| CN104300924B (en) * | 2014-10-17 | 2017-09-01 | 中国科学院微电子研究所 | A kind of envelope-tracking power supply and envelope-tracking radio-frequency power amplifier |
| CN108141220A (en) * | 2015-10-30 | 2018-06-08 | 索尼半导体解决方案公司 | The MOS linear resistors of state machine control |
| CN108141220B (en) * | 2015-10-30 | 2022-04-12 | 索尼半导体解决方案公司 | MOS linear resistor controlled by state machine |
| CN106331542A (en) * | 2016-08-29 | 2017-01-11 | 长春长光辰芯光电技术有限公司 | High dynamic focal plane readout circuit and sampling method thereof |
| CN106331542B (en) * | 2016-08-29 | 2019-02-26 | 长春长光辰芯光电技术有限公司 | High dynamic circuit of focal plane readout and its method of sampling |
| CN107070411A (en) * | 2017-01-04 | 2017-08-18 | 深圳市紫光同创电子有限公司 | A kind of unit gain sample circuit and the method for improving sampling precision |
| CN107070411B (en) * | 2017-01-04 | 2023-02-24 | 深圳市紫光同创电子有限公司 | Unit gain sampling circuit and method for improving sampling precision |
| CN107911118A (en) * | 2017-12-08 | 2018-04-13 | 成都聚利中宇科技有限公司 | A kind of multi-channel sampling tracking keeps equipment and signal sampling method |
| CN112600543A (en) * | 2020-12-09 | 2021-04-02 | 屹世半导体(上海)有限公司 | Sampling circuit based on switch control |
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Open date: 20081008 |