CN107359205A - Thin film transistor (TFT) and preparation method, array base palte and preparation method, display panel - Google Patents
Thin film transistor (TFT) and preparation method, array base palte and preparation method, display panel Download PDFInfo
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- CN107359205A CN107359205A CN201710637890.0A CN201710637890A CN107359205A CN 107359205 A CN107359205 A CN 107359205A CN 201710637890 A CN201710637890 A CN 201710637890A CN 107359205 A CN107359205 A CN 107359205A
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- 239000010409 thin film Substances 0.000 title claims abstract description 40
- 238000002360 preparation method Methods 0.000 title claims abstract description 36
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 112
- 239000010408 film Substances 0.000 claims abstract description 108
- 239000010410 layer Substances 0.000 claims abstract description 91
- 238000005530 etching Methods 0.000 claims abstract description 63
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 230000000717 retained effect Effects 0.000 claims abstract description 34
- 239000011229 interlayer Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims description 33
- 238000009413 insulation Methods 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 16
- 238000002161 passivation Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- -1 grid Substances 0.000 claims description 2
- 230000003628 erosive effect Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 13
- 239000000463 material Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910000809 Alumel Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910001182 Mo alloy Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003851 corona treatment Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
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- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Embodiments of the invention provide a kind of thin film transistor (TFT) and preparation method thereof, array base palte and preparation method thereof, display panel, are related to display technology field, in the manufacturing process of thin film transistor (TFT), without carrying out large area etching to grid insulating film.The preparation method of thin film transistor (TFT), including：Grid insulating film, grid metal film and photoresist are sequentially formed on active layer；Photoresist is exposed using half-tone mask plate, the region that part is located at grid to be formed is fully retained in photoresist, photoresist removes part and the both sides of part is fully retained positioned at photoresist and are located at other regions positioned at the top of active layer, the member-retaining portion of photoresist half completely；Grid metal film and grid insulating film are performed etching using etching technics；The member-retaining portion of photoresist half is removed, grid metal film corresponding to the member-retaining portion of photoresist half is performed etching, forms grid, and remove the photoresist and part is fully retained；Form interlayer insulating film, source electrode and drain electrode.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of thin film transistor (TFT) and preparation method thereof, array base palte and
Its preparation method, display panel.
Background technology
Top gate type thin film transistor has that manufacture craft is simple, and the breadth length ratio (W/L) of raceway groove is larger, and grid and source electrode,
The advantages that parasitic capacitance (Cgs) between drain electrode is small and be widely used.
The Making programme figure of existing top gate type thin film transistor, comprises the following steps：
S10, as shown in Figure 1a, over the substrate 10, active layer 20 is formed using patterning processes.
S11, as shown in Figure 1 b, on the substrate 10 of active layer 20 is formed, sequentially form grid insulating film 301 and grid metal
Film 401.
S12, as shown in Fig. 1 c and Fig. 1 d, the coating photoresist 501 in grid metal film 401, and pass through photoetching process shape
Into photoetching agent pattern 50.
S13, as shown in fig. le, is performed etching using etching technics to grid metal film 401, forms grid 40.
S14, as shown in Figure 1 f, is performed etching using etching technics to grid insulating film 301, forms gate insulation layer 30.
S15, as shown in Figure 1 g, photoetching agent pattern 50 is removed, and in the substrate 10 formed with grid 40, gate insulation layer 30
On, interlayer insulating film 60 is formed using patterning processes, the interlayer insulating film 60 is included positioned at the top of 40 both sides active layer of grid 20
Via.
S16, as shown in figure 1h, source electrode 71 and drain electrode 72 are formed using patterning processes, source electrode 71 and drain electrode 72 pass through respectively
Above-mentioned via contacts with active layer 20.
However, there is problems with the preparation method of above-mentioned top gate type thin film transistor：Using etching technics to gate insulation
Film 301 performs etching, it is necessary to which being performed etching to grid insulating film 301 for large area, can so make when forming gate insulation layer 30
It is uneven into etching, so as to when the thin film transistor (TFT) is incorporated in display device, cause display uneven (Mura).
The content of the invention
Embodiments of the invention provide a kind of thin film transistor (TFT) and preparation method thereof, array base palte and preparation method thereof, shown
Show panel, in the manufacturing process of thin film transistor (TFT), without carrying out large area etching to grid insulating film.
To reach above-mentioned purpose, embodiments of the invention adopt the following technical scheme that：
First aspect, there is provided a kind of preparation method of thin film transistor (TFT), including：Active layer is formed on substrate；Formed
On the substrate of the active layer, grid insulating film, grid metal film and photoresist are sequentially formed；Using half-tone mask plate to institute
State photoresist to be exposed, formation photoresist is fully retained part, the member-retaining portion of photoresist half and photoresist and gone completely after development
Except part；Wherein, the region that part is located at grid to be formed is fully retained in the photoresist, and the photoresist removes part completely
The both sides of part are fully retained and positioned at the top of the active layer, the member-retaining portion position of photoresist half positioned at the photoresist
In other regions；The corresponding grid metal film in part and the grid are removed using etching technics pair completely with the photoresist
Insulation film performs etching；Wherein, after being performed etching to the grid insulating film, the gate insulation layer for including the first via is formed；
The member-retaining portion of photoresist half is removed, the grid metal film corresponding to the member-retaining portion of photoresist half is performed etching,
The grid is formed, and removes the photoresist and part is fully retained；Layer insulation is formed on the substrate for forming the grid
Layer, the interlayer insulating film include second via overlapping with first via；Forming the substrate of the interlayer insulating film
Upper formation source electrode and drain electrode, the source electrode and the drain electrode pass through second via on the interlayer insulating film, the grid
First via on insulating barrier contacts with the active layer.
Preferably, using etching technics pair and the photoresist remove completely the corresponding grid metal film in part and
After the grid insulating film performs etching, formed before the interlayer insulating film, the preparation method also includes：To what is exposed
The active layer enters column conductorization processing.
Optionally, the member-retaining portion of photoresist half is removed, including：The photoresist half is removed using cineration technics to retain
Part；Or portion is fully retained using the ultraviolet irradiation member-retaining portion of photoresist half of certain light intensity and the photoresist
Point, the member-retaining portion of photoresist half is removed after development completely, makes photoresist that the segment thickness of part be fully retained and retains.
Preferably, the corresponding grid metal film in part and institute are removed using etching technics pair and the photoresist completely
Grid insulating film is stated to perform etching, including：The corresponding institute in part is removed using wet-etching technology pair and the photoresist completely
Grid metal film is stated to perform etching；The grid insulating film exposed is performed etching using dry etch process；Or；Using
Dry etch process pair and the photoresist remove the corresponding grid metal film in part and performed etching completely；Carved using dry method
Etching technique performs etching to the grid insulating film exposed.
Based on above-mentioned, it is preferred that the preparation method also includes：The shape on the substrate for forming the source electrode and the drain electrode
Into passivation layer.
Second aspect, there is provided a kind of preparation method of array base palte, including using the preparation method system described in first aspect
Standby thin film transistor (TFT).
The third aspect, there is provided a kind of thin film transistor (TFT), the preparation method of the thin film transistor (TFT) described in first aspect can be passed through
Obtain.The thin film transistor (TFT) includes：Substrate, the active layer being set in turn on the substrate, gate insulation layer, grid, interlayer are exhausted
Edge layer, source electrode and drain electrode；Wherein, the gate insulation layer is laid on the substrate, including exposes and have described in the grid both sides
First via of active layer；The interlayer insulating film is laid on the substrate, including second mistake overlapping with first via
Hole；The source electrode and the drain electrode pass through described on second via on the interlayer insulating film, the gate insulation layer
First via contacts with the active layer.
Preferably, the active layer with the electric conductivity of the source electrode and the drain contact portions is higher than the active layer
The electric conductivity of remainder.
Fourth aspect, there is provided a kind of array base palte, including the thin film transistor (TFT) described in the third aspect.
5th aspect, there is provided a kind of display panel, including the array base palte described in fourth aspect.
Embodiments of the invention provide a kind of thin film transistor (TFT) and preparation method thereof, array base palte and preparation method thereof, shown
Show panel, using half-tone mask plate, can be retained the gate insulation layer large area to be formed, i.e. only while grid is formed
Partial etching above the active layer of grid both sides is removed, it is so, then exhausted to grid without large area when forming gate insulation layer
Edge film performs etching, thus also just in the absence of the problem of causing to etch inequality due to large area gate insulator film.
It is exhausted to grid with respect to large area when using dry etch process gate insulator film, and forming gate insulation layer on the basis of this
Edge film carries out dry etching, and etching speed can be caused slow, and needs equipment to export larger RF energy, seriously
The life-span of dry etching equipment is reduced, the problems such as so as to increase the cost of display device, the present invention can avoid this problem.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 a~Fig. 1 h are a kind of process schematic for preparing top gate type thin film transistor that prior art provides；
Fig. 2 is a kind of schematic flow sheet for preparing thin film transistor (TFT) provided by the invention；
Fig. 3 forms active layer, grid insulating film, grid metal film and photoresist for one kind provided by the invention on substrate
Schematic diagram；
Fig. 4 is the schematic diagram after being exposed on the basis of Fig. 3 using half-tone mask plate to photoresist；
Fig. 5 is pair to remove the corresponding grid metal film in part and grid insulating film completely with photoresist on the basis of Fig. 4
Schematic diagram after performing etching；
Fig. 6 is that the schematic diagram after the member-retaining portion of photoresist half is removed on the basis of Fig. 5；
Fig. 7 forms grid to be performed etching on the basis of Fig. 6 to grid metal film corresponding to the member-retaining portion of photoresist half
Schematic diagram；
Fig. 8 is the schematic diagram that interlayer insulating film is formed on the basis of Fig. 7；
Fig. 9 is a kind of schematic diagram one of thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 10 a are a kind of schematic diagram one for entering column conductor to active layer provided by the invention；
Figure 10 b are a kind of schematic diagram two for entering column conductor to active layer provided by the invention；
Figure 10 c are a kind of schematic diagram three for entering column conductor to active layer provided by the invention；
Figure 11 is a kind of schematic diagram two of thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 12 is a kind of schematic diagram three of thin film transistor (TFT) provided in an embodiment of the present invention；
Figure 13 is a kind of schematic diagram four of thin film transistor (TFT) provided in an embodiment of the present invention.
Reference：
10- substrates；20- active layers；30- gate insulation layers；301- grid insulating films；40- grids；401- grid metal films；
50- photoetching agent patterns；Part is fully retained in 51- photoresists；The member-retaining portion of 52- photoresists half；501- photoresists；60- interlayers are exhausted
Edge layer；71- source electrodes；72- drains；80- half-tone mask plates；The complete opaque sections of 81-；82- translucent portions；83- is complete
Transparent part；90- passivation layers.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of preparation method of thin film transistor (TFT), as shown in Fig. 2 comprising the following steps：
S20, as shown in figure 3, over the substrate 10 formed active layer 20.
Specifically, active layer 20 can be formed by a patterning processes.Patterning processes include film forming, exposure, development,
The processing steps such as etching.
The material of active layer 20 can be the material such as non-crystalline silicon, polysilicon, oxide, organic.
S21, as shown in figure 3, formed active layer 20 substrate 10 on, it is thin to sequentially form grid insulating film 301, grid metal
Film 401 and photoresist 501.
Example, depositing operation deposition grid insulating film 301 and grid metal film 401 can be used.Afterwards, using coating work
Skill is coated with one layer of photoresist 501.
The material of grid insulating film 301 can be silicon nitride, can also use silica, silicon oxynitride etc..Grid metal film
401 can use the metal materials such as molybdenum, aluminium, chromium, titanium, tungsten, copper, alumel, molybdenum and tungsten alloy or tungsten-copper alloy, can also make
With the combination of above-mentioned different materials.
S22, as shown in figure 4, being exposed using half-tone mask plate 80 to photoresist 501, photoresist is formed after development
Part 51, the member-retaining portion 52 of photoresist half and photoresist is fully retained and removes part completely；Wherein, part is fully retained in photoresist
51 are located at the region of grid to be formed, and photoresist removes part and the both sides of part 51 are fully retained positioned at photoresist and are located at completely
The top of active layer 20, the member-retaining portion 52 of photoresist half are located at other regions.
With reference to shown in figure 4, half-tone mask plate 80 includes complete opaque section 81, translucent portion 82, fully transparent
Part 83；I.e.：Half-tone mask plate 80 refers to form lighttight light shield layer in some regions on non-transparent substrate material, another
Some outer regions form semi-transparent light shield layer, and other regions do not form any light shield layer；Wherein, the shading of translucent portion 82
Thickness degree is less than the light shield layer thickness of complete opaque section 81；Furthermore, it is possible to the light shield layer by adjusting translucent portion 82
Thickness changes transmitance of the light shield layer of translucent portion 82 to ultraviolet light.
Based on this, the operation principle of half-tone mask plate 80 is described as follows：It is different on half-tone mask plate 80 by controlling
The thickness of light shield layer at region, make the intensity through light for being exposed on different zones different, so that photoresist 501 is carried out
After selectively exposure, development, formed with the complete opaque section 81 of half-tone mask plate 80, translucent portion 82 and
Corresponding photoresist is fully retained part 51, the member-retaining portion 52 of photoresist half and photoresist and gone completely respectively for fully transparent part 83
Except part.
Wherein, it is above-mentioned to be illustrated by positive photoresist of photoresist.Certainly, photoresist can also be negative photoresist, in this situation
Under, after exposure, photoresist is fully retained that part 51 is corresponding with the fully transparent part 83 of half-tone mask plate 80, and photoresist is complete
Full removal part is corresponding with the complete opaque section 81 of half-tone mask plate 80, and concrete principle is consistent with the above, herein no longer
Repeat.
S23, as shown in figure 5, removed completely with photoresist using etching technics pair the corresponding grid metal film 401 in part and
Grid insulating film 301 performs etching；Wherein, after being performed etching to grid insulating film 301, the gate insulation for including the first via is formed
Layer 30.
Herein, the corresponding grid metal film 401 in part can be first removed completely with photoresist using wet-etching technology pair to enter
Row etching, afterwards, is performed etching using dry etch process to the grid insulating film 301 exposed.
Or it can first remove the corresponding grid metal film 401 in part completely with photoresist using dry etch process pair and enter
Row etching, afterwards, is performed etching using dry etch process to the grid insulating film 301 exposed.
S24, as shown in Figure 6 and Figure 7, the member-retaining portion 52 of photoresist half is removed, to corresponding to the member-retaining portion 52 of photoresist half
Grid metal film 401 performs etching, and forms grid 40, and remove photoresist and part 51 is fully retained.
Because thickness of the thickness more than the member-retaining portion 52 of photoresist half of part 51 is fully retained in photoresist, thus, inciting somebody to action
When the member-retaining portion 52 of photoresist half removes completely, what photoresist was fully retained part 51 is more than the part of half member-retaining portion of photoresist 52
Thickness be retained.
On this basis, the grid metal exposed after being removed by wet-etching technology to the member-retaining portion 52 of photoresist half is thin
Film 401 performs etching, and is retained so that being photo-etched glue and the grid metal film 401 that part 51 covers being fully retained, and shape
Into grid 40.
Wherein, cineration technics can be used to remove the member-retaining portion 52 of photoresist half.
Or it can use the member-retaining portion 52 of ultraviolet irradiation light photoresist half of certain light intensity and photoresist that part is fully retained
51, the member-retaining portion 52 of photoresist half is removed after development completely, makes photoresist that the photoresist half that is more than of part 51 be fully retained and retains
The thickness of the part of part 52 is retained.Herein, part 51 is fully retained to the member-retaining portion 52 of photoresist half and photoresist
Exposure should be controlled rationally, so that the member-retaining portion 52 of photoresist half exposes completely, and it is only exposure that part 51, which is fully retained, in photoresist
The part equal with photoresist half member-retaining portion, 52 thickness.
S25, as shown in figure 8, formed grid 40 substrate 10 on formed interlayer insulating film 60；Interlayer insulating film 60 includes
Second via overlapping with first via.
Short circuit will not occur with grid 40 when source electrode and drain electrode to ensure to be subsequently formed, the second via should be between grid 40
With a certain distance.
Example, depositing operation deposition interlayer insulating film can be used, afterwards, and by exposing, developing, etching technics, shape
Into the second via.
The material of interlayer insulating film 60 can be silicon nitride, can also use silica, silicon oxynitride etc..
S26, as shown in figure 9, formed interlayer insulating film 60 substrate 10 on formed source electrode 71 and drain electrode 72；The He of source electrode 71
Drain electrode 72 is contacted by the second via on interlayer insulating film 60, the first via on gate insulation layer 30 with active layer 20.
Example, depositing operation deposition drain metallic film can be used, afterwards, and by exposing, developing, etching technics, shape
Into source electrode 71 and drain electrode 72.
Wherein, drain metallic film can use molybdenum, aluminium, chromium, titanium, tungsten, copper, alumel, molybdenum and tungsten alloy or tungsten copper to close
The metal materials such as gold, the combination of above-mentioned different materials can also be used.
The embodiment of the present invention provides a kind of preparation method of thin film transistor (TFT), using half-tone mask plate, can form grid
While pole 40, it is retained the large area of gate insulation layer 30 to be formed, i.e. only by the part of the top of 40 both sides active layer of grid 20
Etching is removed, and so, then grid insulating film 301 is performed etching without large area when forming gate insulation layer 30, thus
Just in the absence of the problem of causing to etch inequality due to large area gate insulator film 301.On this basis, when using dry method
Etching technics gate insulator film 301, and when forming gate insulation layer 30, grid insulating film 301 is carried out with respect to large area
Dry etching, etching speed can be caused slow, and need equipment to export larger RF energy, serious reduction dry etching is set
In the standby life-span, the problems such as so as to increase the cost of display device, the present invention can avoid this problem.
Preferably, the corresponding grid metal film 401 in part is being removed with photoresist using etching technics pair completely and grid are exhausted
After edge film 301 performs etching, formed before interlayer insulating film 60, the preparation method also includes：To the active layer exposed
20 enter column conductorization processing.To reduce source electrode 71, drain electrode 72 and the contact resistance of active layer 20.
Wherein, conductor method can be corona treatment.
Example, as shown in Figure 10 a, the corresponding grid metal in part can removed with photoresist completely using etching technics pair
After film 401 and grid insulating film 301 perform etching, before removing the member-retaining portion 52 of photoresist half, to the active layer exposed
20 enter column conductorization processing.
Or as shown in fig. lob, can be after the member-retaining portion 52 of photoresist half be removed, to the member-retaining portion 52 of photoresist half
Corresponding grid metal film 401 is performed etching, and is formed before grid 40, and column conductorization processing is entered to the active layer 20 exposed.
Or as shown in figure l0c, formed after grid 40, formed before interlayer insulating film 60, to the active layer 20 exposed
Enter column conductorization processing.
Afterwards, above-mentioned processing step is can refer to, forms the thin film transistor (TFT) of structure as shown in figure 11.
On the basis of the above, as shown in Figure 12 and Figure 13, passivation is formed on the substrate 10 for forming source electrode 71 and drain electrode 72
Layer 90, to protect source electrode 71 and drain electrode 72, avoid aoxidizing.
The material of passivation layer 90 can be silicon nitride, can also use silica, silicon oxynitride etc..
The embodiment of the present invention also provides a kind of preparation method of array base palte, including prepares film by above-mentioned preparation method
Transistor.On this basis, transparency electrode can also be formed.
Wherein, the transparency electrode can include pixel electrode, can also further include public electrode；Pixel electrode
Electrically connected with drain electrode 72.
Or the transparency electrode can include anode and negative electrode, anode electrically connects with drain electrode 72.
The embodiment of the present invention also provides a kind of thin film transistor (TFT), as shown in figure 9, including：Substrate 10, it is set in turn in substrate
Active layer 20, gate insulation layer 30, grid 40, interlayer insulating film 60, source electrode 71 and drain electrode 72 on 10；Wherein, gate insulation layer 30
It is laid on substrate 10, including exposes the first via of the both sides active layer 20 of grid 40；Interlayer insulating film 60 is laid in substrate 10
On, including second via overlapping with the first via；Source electrode 71 and drain electrode 72 pass through the second via, the grid on interlayer insulating film 60
The first via on insulating barrier 30 contacts with active layer 20.
Because the thin film transistor (TFT) of the embodiment of the present invention can be prepared by the preparation method of above-mentioned thin film transistor (TFT), because
And with the preparation method identical beneficial effect with above-mentioned thin film transistor (TFT), it will not be repeated here.
Preferably, as shown in figure 11, active layer 20 with the electric conductivity of source electrode 71 and 72 contact portions that drain higher than active
The electric conductivity of 20 remainder of layer.So, source electrode 71, drain electrode 72 and the contact resistance of active layer 20 can be reduced.
It is preferred that as shown in Figure 12 and Figure 13, the thin film transistor (TFT) also includes blunt above source electrode 71 and drain electrode 72
Change layer 90, to protect source electrode 71 and drain electrode 72, avoid aoxidizing.
The embodiment of the present invention also provides a kind of array base palte, including above-mentioned array base palte.
On this basis, the array base palte can also form transparency electrode.
Wherein, the transparency electrode can include pixel electrode, can also further include public electrode；Pixel electrode
Electrically connected with drain electrode 72.
Or the transparency electrode can include anode and negative electrode, anode electrically connects with drain electrode 72.
The embodiment of the present invention also provides a kind of display panel, including above-mentioned array base palte.
Wherein, the display panel can be liquid crystal display panel or organic electroluminescent LED display panel.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all be contained
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
- A kind of 1. preparation method of thin film transistor (TFT), it is characterised in that including：Active layer is formed on substrate；On the substrate of the active layer is formed, grid insulating film, grid metal film and photoresist are sequentially formed；The photoresist is exposed using half-tone mask plate, photoresist is formed after development part, photoresist is fully retained Half member-retaining portion and photoresist remove part completely；Wherein, the area that part is located at grid to be formed is fully retained in the photoresist Domain, the photoresist remove part and the both sides of part are fully retained and positioned at the upper of the active layer positioned at the photoresist completely Side, the member-retaining portion of photoresist half are located at other regions；The corresponding grid metal film in part is removed with the photoresist using etching technics pair completely and the gate insulation is thin Film performs etching；Wherein, after being performed etching to the grid insulating film, the gate insulation layer for including the first via is formed；The member-retaining portion of photoresist half is removed, the grid metal film corresponding to the member-retaining portion of photoresist half is carved Erosion, forms the grid, and remove the photoresist and part is fully retained；Interlayer insulating film is formed on the substrate for forming the grid, the interlayer insulating film includes overlapping with first via The second via；Source electrode and drain electrode are formed on the substrate for forming the interlayer insulating film, the source electrode and the drain electrode pass through the interlayer First via on second via, the gate insulation layer on insulating barrier contacts with the active layer.
- 2. preparation method according to claim 1, it is characterised in that complete using etching technics pair and the photoresist After the grid metal film and the grid insulating film corresponding to removing part perform etching, formed the interlayer insulating film it Before, the preparation method also includes：Enter column conductorization processing to the active layer exposed.
- 3. preparation method according to claim 1, it is characterised in that the member-retaining portion of photoresist half is removed, including：The member-retaining portion of photoresist half is removed using cineration technics；OrThe member-retaining portion of photoresist half is irradiated using the ultraviolet of certain light intensity and part is fully retained in the photoresist, is developed Remove the member-retaining portion of photoresist half completely afterwards, make photoresist that the segment thickness of part be fully retained and retain.
- 4. preparation method according to claim 1, it is characterised in that gone completely using etching technics pair and the photoresist Except the grid metal film corresponding to part and the grid insulating film perform etching, including：The corresponding grid metal film in part is removed completely using wet-etching technology pair and the photoresist to perform etching；Adopt The grid insulating film exposed is performed etching with dry etch process；Or；The corresponding grid metal film in part is removed completely using dry etch process pair and the photoresist to perform etching；Adopt The grid insulating film exposed is performed etching with dry etch process.
- 5. according to the preparation method described in claim any one of 1-4, it is characterised in that also include：Formed the source electrode and Passivation layer is formed on the substrate of the drain electrode.
- 6. a kind of preparation method of array base palte, it is characterised in that including using the preparation side described in claim any one of 1-5 Method prepares thin film transistor (TFT).
- A kind of 7. thin film transistor (TFT), it is characterised in that including：Substrate, the active layer being set in turn on the substrate, gate insulation Layer, grid, interlayer insulating film, source electrode and drain electrode；Wherein, the gate insulation layer is laid on the substrate, including exposes the first mistake of active layer described in the grid both sides Hole；The interlayer insulating film is laid on the substrate, including second via overlapping with first via；The source electrode and the drain electrode pass through described on second via on the interlayer insulating film, the gate insulation layer First via contacts with the active layer.
- 8. thin film transistor (TFT) according to claim 7, it is characterised in that the active layer with the source electrode and the leakage The electric conductivity of pole contact portion is higher than the electric conductivity of the active layer remainder.
- 9. a kind of array base palte, it is characterised in that including the thin film transistor (TFT) described in claim 7 or 8.
- 10. a kind of display panel, it is characterised in that including the array base palte described in claim 9.
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| CN110676265A (en) * | 2019-09-25 | 2020-01-10 | 南京中电熊猫平板显示科技有限公司 | Manufacturing method of display panel |
| CN111201590A (en) * | 2017-12-07 | 2020-05-26 | 深圳市柔宇科技有限公司 | Thin film transistor, preparation method thereof, array substrate and display device |
| CN111261588A (en) * | 2020-02-04 | 2020-06-09 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor array panel and manufacturing method thereof |
| CN111308850A (en) * | 2020-02-21 | 2020-06-19 | 京东方科技集团股份有限公司 | Mask plate, TFT preparation method, TFT and array substrate |
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| US20130069070A1 (en) * | 2011-09-19 | 2013-03-21 | Samsung Mobile Display Co., Ltd. | Manufacturing method for display device having a plurality of thin film transistors and display device formed thereby |
| CN105932067A (en) * | 2016-06-07 | 2016-09-07 | 京东方科技集团股份有限公司 | Top gate type film transistor, preparation method, array substrate and display panel |
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| US20130069070A1 (en) * | 2011-09-19 | 2013-03-21 | Samsung Mobile Display Co., Ltd. | Manufacturing method for display device having a plurality of thin film transistors and display device formed thereby |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111201590A (en) * | 2017-12-07 | 2020-05-26 | 深圳市柔宇科技有限公司 | Thin film transistor, preparation method thereof, array substrate and display device |
| CN110676265A (en) * | 2019-09-25 | 2020-01-10 | 南京中电熊猫平板显示科技有限公司 | Manufacturing method of display panel |
| CN110676265B (en) * | 2019-09-25 | 2022-02-08 | 南京京东方显示技术有限公司 | Manufacturing method of display panel |
| CN111261588A (en) * | 2020-02-04 | 2020-06-09 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor array panel and manufacturing method thereof |
| CN111261588B (en) * | 2020-02-04 | 2023-06-02 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor array panel and manufacturing method thereof |
| CN111308850A (en) * | 2020-02-21 | 2020-06-19 | 京东方科技集团股份有限公司 | Mask plate, TFT preparation method, TFT and array substrate |
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| CN107359205B (en) | 2019-12-20 |
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