CN105932067A - Top gate type film transistor, preparation method, array substrate and display panel - Google Patents
Top gate type film transistor, preparation method, array substrate and display panel Download PDFInfo
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- CN105932067A CN105932067A CN201610403651.4A CN201610403651A CN105932067A CN 105932067 A CN105932067 A CN 105932067A CN 201610403651 A CN201610403651 A CN 201610403651A CN 105932067 A CN105932067 A CN 105932067A
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- 239000000758 substrate Substances 0.000 title claims abstract description 32
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 239000004020 conductor Substances 0.000 claims abstract description 36
- 239000010410 layer Substances 0.000 claims description 106
- 239000010409 thin film Substances 0.000 claims description 71
- 230000004888 barrier function Effects 0.000 claims description 36
- 239000012212 insulator Substances 0.000 claims description 33
- 239000010408 film Substances 0.000 claims description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 229910044991 metal oxide Inorganic materials 0.000 claims description 21
- 150000004706 metal oxides Chemical class 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000002161 passivation Methods 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 238000004380 ashing Methods 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract 5
- 238000010586 diagram Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000007788 liquid Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 102100035366 Centromere protein M Human genes 0.000 description 1
- 101000737696 Homo sapiens Centromere protein M Proteins 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- -1 before graphical Substances 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
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- Thin Film Transistor (AREA)
Abstract
The application discloses a top gate type film transistor, a preparation method, an array substrate and a display panel. The resistance between the source electrode and the drain electrode of the top gate type film transistor is reduced, and the electric property of the top gate type film transistor is improved. The top gate type film transistor disclosed by the application forms a first electrode and a second electrode between an active layer and a grid electrode insulation layer, the source electrode is connected with the first electrode through a first through hole formed on each of the grid electrode insulation layer and the source/drain electrode insulation layer, the drain electrode is connected with the second electrode through a second through hole formed on the grid electrode insulation layer and the source/drain electrode insulation layer; and the first electrode at least partially covers the first conductor area of the active layer, and the second electrode at least partially covers the second conductor area of the active layer.
Description
Technical field
The application relates to technical field of semiconductors, particularly relate to a kind of top gate type thin film transistor, preparation method,
Array base palte and display floater.
Background technology
Flat-panel screens (F1at Pane1Disp1ay, FPD) oneself become the main product on market, plane show
Show that the kind of device also gets more and more, such as liquid crystal display (Liquid Crysta1Disp1ay, LCD), organic
Light emitting diode (Organic Light Emitted Diode, OLED) display, plasma display
(P1asma Disp1ay Pane1, PDP) and Field Emission Display (Field Emission Display, FED)
Deng.Thin film transistor (TFT) (Thin Film Transistor, TFT) backboard as FPD industry core technology
Technology, is also experiencing deep change.Especially metal oxide thin-film transistor (Metal Oxide Thin
Film Transistor, MOTFT), owing to having higher mobility (5～about 50cm2/Vs), system
Make that technique is simple, cost is relatively low, and there is the feature such as large-area uniformity of excellence, therefore MOTFT skill
Art has just attracted much industry attention since being born.
As it is shown in figure 1, be existing top gate type thin film transistor structure, including: underlay substrate 1, it is formed at
Active layer 2 on underlay substrate 1, it is formed at the gate insulator 3 on active layer 2, is formed at grid
Gate electrode 4 on pole insulating barrier 3, it is formed at the source-drain electrode insulating barrier 5 on gate electrode 4 and is formed
Source electrode 6 on source-drain electrode insulating barrier 5 and drain electrode 7, wherein, source electrode 6 and drain electrode 7 lead to
Cross different vias to be connected with active layer 2.
Wherein, in order to reduce parasitic capacitance, improve the charge/discharge rates of pixel capacitance, the source electrode 6 of setting,
Drain electrode 7 does not generally overlap with gate electrode 4.See Fig. 1, the thin film transistor (TFT) of this kind of structure, active layer
The first conductor region D-11 is there is between channel region C-0 and the link position of source electrode 6 of 2, and
The second conductor region D-12, now, source is there is between the link position of channel region C-0 and drain electrode 7
Resistance between electrode 6 and drain electrode 7 is:
RDS=ROhm+RChannel+RD,
Wherein, ROhmBeing made up of two parts contact resistance, a part is source electrode 6 and the contacting of active layer 2
Resistance, another part is the contact resistance of drain electrode 7 and active layer 2, RChannelDitch for active layer 2
The resistance of region, road C-0, RDThe first conductor region D-11 resistance and the second conductor for active layer 2
The resistance sum of region D-12 resistance, generally, RDThe biggest, the electric property of device can be the poorest.
In sum, existing top gate type thin film transistor makes source electrode 6 and drain electrode 7 and gate electrode 4
When not overlapping, there is the first bigger conductor region D11 of resistance and the second conductor region in active layer 2
D12 so that the resistance between top gate type thin film transistor source electrode 6 and drain electrode 7 is relatively big, reduces device
The electric property of part.
Summary of the invention
The purpose of the embodiment of the present application is to provide a kind of top gate type thin film transistor, preparation method, array base palte
And display floater, to reduce the resistance between top gate type thin film transistor source electrode and drain electrode, improve top-gated
The electric property of type thin film transistor (TFT).
The embodiment of the present application provides a kind of top gate type thin film transistor, including: underlay substrate, is formed at institute
State the active layer on underlay substrate, be formed at the gate insulator of described active layer, be formed at institute
State there is on gate insulator the gate electrode of gate electrode, to be formed at the source-drain electrode on described gate electrode exhausted
Edge layer and be formed at the source electrode on described source-drain electrode insulating barrier and drain electrode, wherein,
The first electrode and the second electrode it is also formed with between described active layer and described gate insulator, described
Source electrode is by being arranged on the first via on described gate insulator and described source-drain electrode insulating barrier with described
First electrode connects, and described drain electrode is by being arranged on described gate insulator and described source-drain electrode insulating barrier
On the second via be connected with described second electrode, and, described first electrode at least partly covers described
First conductor region of active layer, what described second electrode at least partly covered described active layer second leads
Body region.
The top gate type thin film transistor that the embodiment of the present application provides, at described active layer and described gate insulator
Being also formed with the first electrode and the second electrode between Ceng, described first electrode covers the first of described active layer
Conductor region, described second electrode covers the second conductor region of described active layer, due to the first electricity
The resistance of pole and the second electrode is less than the first conductor region and the resistance in the second conductor region of active layer,
And then the electronics resistance by source electrode arrival drain electrode can be reduced, reduce top gate type thin film transistor source electrode
And the resistance between drain electrode, improves the electric property of top gate type thin film transistor.
Preferably, on the direction being perpendicular to described underlay substrate, the projection of described gate electrode and described the
The projection of one electrode and described second electrode does not overlaps.
The top gate type thin film transistor that the application provides, the projection of institute's gate electrode and described first electrode and institute
The projection stating the second electrode does not overlaps, and the first electrode or the second electrode can be avoided to be formed with gate electrode and hand over
Folded electric capacity, reduces the electric property of device.
Preferably, it is also formed with passivation layer between described underlay substrate and described active layer.
Preferably, be also formed with between described underlay substrate and described passivation layer bottom light shield layer, wherein,
On the direction being perpendicular to described underlay substrate, the projection of described bottom light shield layer covers described gate electrode
Projection.
The top gate type thin film transistor that the embodiment of the present application provides, the projection of described bottom light shield layer covers institute
State the projection of gate electrode, the semiconductor light-receiving of top gate type thin film transistor active layer channel region can be avoided
According to rear generation photo-generated carrier, thus affect device performance.
Preferably, it is also formed with protective layer on described source electrode and described drain electrode.
Preferably, the material of described first electrode and described second electrode is any one in aluminum, molybdenum, titanium
Kind.
The embodiment of the present application provides a kind of array base palte, the described top gate type provided including the embodiment of the present application
Thin film transistor (TFT).
The embodiment of the present application provides a kind of display floater, the described array base provided including the embodiment of the present application
Plate.
The embodiment of the present application provides the preparation method of a kind of top gate type thin film transistor, is used for preparing the application
The described top gate type thin film transistor that embodiment provides, described method includes:
Active layer and the first electrode of described active layer and the second electrode it is formed with on underlay substrate,
Further, described first electrode at least partly covers the first conductor region of described active layer, described second electricity
Best small part covers the second conductor region of described active layer；
Gate insulator is formed on described first electrode and described second electrode；
Gate electrode is formed on described gate insulator；
Source-drain electrode insulating barrier is formed on described gate electrode；
The first via and the second via is formed at described source-drain electrode insulating barrier and described gate insulator, described
First via is extended to described first electrode by described source-drain electrode insulating barrier and exposes described first electrode, institute
State the second via extended to described second electrode by described source-drain electrode insulating barrier and expose described second electrode；
Forming source electrode and drain electrode on described source-drain electrode insulating barrier, wherein, described source electrode is passed through
Described first via and described first electrode connect, and described drain electrode is by described second via and described the
Two electrodes connect.
Preferably, be formed on underlay substrate active layer and described active layer the first electrode and
Second electrode, specifically includes:
Underlay substrate sequentially forms metal-oxide film, metallic film and photoresist, by half
Tone mask or gray tone cover technique makes the formation of described photoresist have the first thickness area and the second thickness
The photoresist figure layer in region；
By first step etching technics make described metallic film formed have the first pattern the first figure layer and
Described metal-oxide film is made to form described active layer；
Process to remove by ashing and there are whole photoresists of the second thickness area and there is the first caliper zones
The part photoresist in territory；
Described first figure layer is made to form described first electrode and the second electrode by second step etching technics.
The preparation method of top gate type thin film transistor that the embodiment of the present application provides, by use half perspective or
Gray tone masking process, can improve top gate type thin film crystal on the premise of not increasing mask exposure number of times
Pipe performance, manufacturing process is simple.
Preferably, described second step etching technics is dry etching.
The preparation method of the top gate type thin film transistor that the embodiment of the present application provides, described second step etching work
Skill is dry etching, can modify the channel region of active layer, improve the electric property of device.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing top gate type thin film transistor；
The structural representation of a kind of top gate type thin film transistor that Fig. 2 provides for the embodiment of the present application；
The structural representation of the another kind of top gate type thin film transistor that Fig. 3 provides for the embodiment of the present application；
The Making programme figure of a kind of top gate type thin film transistor that Fig. 4 provides for the embodiment of the present application；
Fig. 5 is the embodiment of the present application during making top gate type thin film transistor, is formed over the passivation layer
The schematic diagram of metal-oxide film, metallic film and photoresist；
Fig. 6 is the embodiment of the present application during making top gate type thin film transistor, makes photoresist form tool
There is the schematic diagram of the photoresist figure layer of the first thickness area and the second thickness area；
Fig. 7 is the embodiment of the present application during making top gate type thin film transistor, makes conductor thin film shape
Become there is the first figure layer of the first pattern and make metal-oxide film be formed with the schematic diagram of active layer；
Fig. 8 is the embodiment of the present application during making top gate type thin film transistor, removes that to have second thick
The whole photoresists spending region and the schematic diagram of the part photoresist with the first thickness area；
Fig. 9 is the embodiment of the present application during making top gate type thin film transistor, makes the first figure layer be formed
First electrode and the schematic diagram of the second electrode；
Figure 10 is the embodiment of the present application during making top gate type thin film transistor, at the first electrode and
The schematic diagram of gate insulator is formed on second electrode；
Figure 11 is the embodiment of the present application during making top gate type thin film transistor, at gate insulator
On form the schematic diagram of gate electrode；
Figure 12 is the embodiment of the present application during making top gate type thin film transistor, on gate electrode
Form the schematic diagram of source-drain electrode insulating barrier；
Figure 13 is the embodiment of the present application during making top gate type thin film transistor, insulate at source-drain electrode
Layer and gate insulator form the first via and the schematic diagram of the second via；
Figure 14 is the embodiment of the present application during making top gate type thin film transistor, insulate at source-drain electrode
Source electrode and the schematic diagram of drain electrode is formed on Ceng.
Detailed description of the invention
Below in conjunction with Figure of description, the embodiment of the present application is realized process to be described in detail.Should be noted that
, the most same or similar label represents same or similar element or has same or like merit
The element of energy.The embodiment described below with reference to accompanying drawing is exemplary, is only used for explaining the application,
And it is not intended that restriction to the application.
Seeing Fig. 2, the embodiment of the present application provides a kind of top gate type thin film transistor, including: underlay substrate 1,
It is formed at the active layer 2 on underlay substrate 1, is formed at the gate insulator 3 on active layer 2, shape
Become the gate electrode 4 on gate insulator 3, be formed at source-drain electrode insulating barrier 5 on gate electrode 4 with
And it is formed at the source electrode 6 on source-drain electrode insulating barrier 5 and drain electrode 7, wherein,
The first electrode 8 and the second electrode 9, source electrode it is also formed with between active layer 2 and gate insulator 3
6 by the first via 10 and the first electrode 8 being arranged on gate insulator 3 and source-drain electrode insulating barrier 5
Connecting, drain electrode 7 is by the second via 11 being arranged on gate insulator 3 and source-drain electrode insulating barrier 5
It is connected with the second electrode 9, and, the first electrode 8 is at least partly coated with the first conductor district of active layer 2
Territory D-11, the second electrode 9 is at least partly coated with the second conductor region D-12 of active layer 2.
Wherein, the material of active layer 2 is usually quasiconductor, is specifically as follows amorphous silicon hydride (a-Si:H), also
Can be low temperature polycrystalline silicon (Low Temperature Poly-silicon, LTPS), it is also possible to for burning
Thing.Preferably, the material metal-oxide of active layer 2.Concrete metal-oxide can be containing In,
The metal-oxide of at least one in Zn, Ga and Sn, such as, be specifically as follows InGaZnO or
InSnZnO.Concrete, the material of the first electrode 8 and the second electrode 9 can be metal.It is said that in general,
Resistance due to metal is less than the resistance of quasiconductor, thus selects the first electrode and second electrode of metal material
The electronics that can make source electrode 6 is easier to arrive drain electrode 7, i.e. reduce top gate type thin film transistor source electricity
Resistance between pole 6 and drain electrode 7, and then improve the electric property of device.Preferably, the first electrode 8
It is any one in aluminum, molybdenum, titanium with the material of the second electrode 9.
It should be noted that on the direction being perpendicular to underlay substrate 1, the first electrode 8 and the second electrode 9
Projection and the projection of gate electrode 4 can overlap, it is also possible to do not overlap.Preferably, the first electrode 8 and
The projection of two electrodes 9 and the projection of gate electrode 4 do not overlap.The projection of the first electrode 8 and the second electrode 9 and
When the projection of gate electrode 4 does not overlaps, the first electrode 8 or the second electrode 9 can be avoided to be formed with gate electrode 4
Parasitic capacitance, it is to avoid reduce the electric property of device.
See Fig. 3, in the particular embodiment, the top gate type thin film transistor that the embodiment of the present application provides,
Passivation layer 12 can also be formed with, at source electrode 6 and drain electrode 7 between underlay substrate 1 and active layer 2
On can also be formed with protective layer (not shown), and between underlay substrate 1 and passivation layer 12
Can also be formed with bottom light shield layer 13, wherein, on the direction being perpendicular to underlay substrate 1, bottom hides
The projection of the projection covering grid electrode 4 of photosphere 13.The throwing of the projection covering grid electrode 4 of bottom light shield layer 13
Shadow, can avoid the semiconductor light-receiving of top gate type thin film transistor channel region C-0 to shine rear photo-generated carrier,
Thus avoid affecting device performance.
The embodiment of the present application provides a kind of array base palte, the top gate type thin film provided including the embodiment of the present application
Transistor.
The embodiment of the present application provides a kind of display floater, the array base palte provided including the embodiment of the present application.
Seeing Fig. 4, the embodiment of the present application provides the preparation method of a kind of top gate type thin film transistor, is used for making
The top gate type thin film transistor that standby the embodiment of the present application provides, method includes:
401, on underlay substrate, it is formed with active layer and the first electrode of active layer and the second electrode,
Further, the first electrode is at least partly coated with the first conductor region of active layer, and the second electrode at least partly covers
It is stamped the second conductor region of active layer.
Preferably, in order to improve top gate type thin film transistor on the premise of not increasing mask exposure number of times
Can, obtained channel region and the conductor region of top gate type thin film transistor by patterning processes, simplify
Manufacturing process, is formed with active layer and the first electrode of active layer and the second electrode on underlay substrate
Step, be specifically as follows:
Underlay substrate sequentially forms metal-oxide film, metallic film and photoresist, by half
Tone mask or gray tone cover technique makes photoresist formation have the first thickness area and the second thickness area
Photoresist figure layer；
Make metallic film be formed by first step etching technics there is the first figure layer of the first pattern and make gold
Belong to sull and be formed with active layer；
Process to remove by ashing and there are whole photoresists of the second thickness area and there is the first caliper zones
The part photoresist in territory；
The first figure layer is made to form the first electrode and the second electrode by second step etching technics.In order to active
The channel region of layer is modified, and improves the electric property of device, it is preferred that second step etching technics is dry
Method etches.
402, on the first electrode and the second electrode, form gate insulator.
403, on gate insulator, form gate electrode.
404, on gate electrode, form source-drain electrode insulating barrier.
405, form the first via and the second via, the first via at source-drain electrode insulating barrier and gate insulator
Being extended and expose the first electrode by source-drain electrode insulating barrier to the first electrode, the second via is by source-drain electrode insulating barrier
Extend to the second electrode and expose the second electrode.
406, on source-drain electrode insulating barrier, form source electrode and drain electrode, wherein, source electrode passes through first
Via and the first electrode connect, and drain electrode is connected by the second via and the second electrode.
For the preparation method of array base palte in the clearer description present invention, have with top gate type thin film transistor
As a example by having the structure shown in Fig. 2, describe in detail as follows in conjunction with Fig. 5 to Figure 14:
Step one, underlay substrate 1 sequentially forms metal-oxide film 21, metallic film 22 and
Photoresist 23, as shown in Figure 5.
The conductor thin film 22 that the application is formed on metal-oxide film, before graphical, metal foil
Film 22 element can be diffused to metal-oxide film 21, can improve active layer 2 ditch of later stage formation
The electric property of region, road C-0, the electric property of optimised devices.
Step 2, covers technique by intermediate tone mask or gray tone and makes photoresist 23 formation have the first thickness
Degree region 231 and the photoresist figure layer 24 of the second thickness area 232, as shown in Figure 6.
Step 3, makes conductor thin film 22 be formed by first step etching technics and has the first of the first pattern
Figure layer 32 and make metal-oxide film 21 be formed with active layer 2, as shown in Figure 7.
Concrete, suitable etching liquid can be selected, make conductor thin film 22 form tool by once etching
There is the first figure layer 32 of the first pattern and make metal-oxide film 21 be formed with active layer 2.Can also lead to
Cross and select different etching liquids, make conductor thin film 22 be formed by twice etching and there is the of the first pattern
One figure layer 32 and make metal-oxide film 21 be formed with active layer 2.For making conductor by twice etching
Change thin film 22 formation there is the first figure layer 32 of the first pattern and make metal-oxide film 21 be formed
Active layer 2, can first etch conductor thin film 22, makes conductor thin film 22 etch formation and has the first pattern
The first figure layer 32, then etch metal-oxide film 21, make metal-oxide film 21 be formed with active layer
2。
Step 4, is removed by ashing process and has whole photoresists of the second thickness area 232 and have
The part photoresist of the first thickness area 231, as shown in Figure 8.
Step 5, makes the first figure layer 32 form the first electrode 8 and the second electrode 9 by second step etching technics,
As shown in Figure 9.Remove residue photoresist.
Preferably, the first figure layer 32 can be made to form the first electrode 8 and the second electrode 9 by dry etching.
While can forming the first electrode 8 and the second electrode 9 making the first figure layer 32 by dry etching, also
The channel region of active layer can be improved, be conducive to improving the electric property of device.
Step 6, forms gate insulator 3, as shown in Figure 10 on the first electrode 8 and the second electrode 9.
Step 7, forms gate electrode 4, as shown in figure 11 on gate insulator 3.
Concrete, gate metal thin film can be formed on gate insulator 3, make grid by patterning processes
Pole metallic film forms gate electrode 4.
Step 8, forms source-drain electrode insulating barrier 5, as shown in figure 12 on gate electrode 4.
Step 9, forms the first via 10 and the second via at source-drain electrode insulating barrier 3 and gate insulator 5
11, the first via 10 is extended to the first electrode 8 and exposes the first electrode 8 by source-drain electrode insulating barrier 5, and second
Via 11 is extended and exposes the second electrode 9 by source-drain electrode insulating barrier 5 to the second electrode 9, as shown in figure 13.
Step 10, forms source electrode 6 and drain electrode 7, as shown in figure 14 on source-drain electrode insulating barrier 5.
Wherein, source electrode 6 is connected by the first via 10 and the first electrode 8, and drain electrode 7 is by the second via
11 and second electrode 9 connect.
The top gate type thin film transistor that the application provides, is also formed between active layer 2 and gate insulator 3
Having the first electrode 8 and the second electrode 9, the first electrode 8 is coated with the first conductor region of active layer 2
D-11, the second electrode 9 is coated with the second conductor region D-12 of active layer 2, due to the first electrode 8 He
The resistance of the second electrode 9 is less than the first conductor region D-11 and the second conductor region of active layer 2
The resistance of D-12, and then electronics can be reduced arrived the resistance of drain electrode 7 by source electrode 6, and then can drop
Low top gate type thin film transistor source electrode 6 and the resistance of drain electrode 7, improve the electricity of top gate type thin film transistor
Learn performance.
Obviously, those skilled in the art can carry out various change and modification without deviating from this Shen to the application
Spirit and scope please.So, if the application these amendment and modification belong to the application claim and
Within the scope of its equivalent technologies, then the application is also intended to comprise these change and modification.
Claims (11)
1. a top gate type thin film transistor, it is characterised in that including: underlay substrate, be formed at described
Active layer on underlay substrate, it is formed at the gate insulator of described active layer, is formed at described grid
Gate electrode on the insulating barrier of pole, it is formed at the source-drain electrode insulating barrier on described gate electrode and is formed at institute
State the source electrode on source-drain electrode insulating barrier and drain electrode, wherein,
The first electrode and the second electrode, described source it is also formed with between described active layer and described gate insulator
Electrode is by the first via of being arranged on described gate insulator and described source-drain electrode insulating barrier and described the
One electrode connects, and described drain electrode is by being arranged on described gate insulator and described source-drain electrode insulating barrier
Second via is connected with described second electrode, and, described first electrode at least partly covers described active layer
The first conductor region, described second electrode at least partly covers the second conductor district of described active layer
Territory.
2. top gate type thin film transistor as claimed in claim 1, it is characterised in that described in being perpendicular to
On the direction of underlay substrate, projection and described first electrode and the projection of described second electrode of described gate electrode
Do not overlap.
3. profit requires the top gate type thin film transistor described in 1, it is characterised in that described underlay substrate and institute
State and between active layer, be also formed with passivation layer.
4. profit requires the top gate type thin film transistor described in 3, it is characterised in that described underlay substrate and institute
State and between passivation layer, be also formed with bottom light shield layer, wherein, on the direction being perpendicular to described underlay substrate,
The projection of described bottom light shield layer covers the projection of described gate electrode.
5. top gate type thin film transistor as claimed in claim 1, it is characterised in that described source electrode and
It is also formed with protective layer on described drain electrode.
6. top gate type thin film transistor as claimed in claim 1, it is characterised in that described first electrode
It is any one in aluminum, molybdenum, titanium with the material of described second electrode.
7. an array base palte, it is characterised in that include the top as described in the arbitrary claim of claim 1～6
Gate type thin film transistor.
8. a display floater, it is characterised in that include array base palte as claimed in claim 7.
9. the preparation method of a top gate type thin film transistor, it is characterised in that want for preparation such as right
The top gate type thin film transistor described in 1, described method is asked to include:
Active layer and the first electrode of described active layer and the second electrode it is formed with on underlay substrate,
Further, described first electrode at least partly covers the first conductor region of described active layer, described second electricity
Best small part covers the second conductor region of described active layer；
Gate insulator is formed on described first electrode and described second electrode；
Gate electrode is formed on described gate insulator；
Source-drain electrode insulating barrier is formed on described gate electrode；
The first via and the second via is formed at described source-drain electrode insulating barrier and described gate insulator, described
One via is extended to described first electrode and exposes described first electrode by described source-drain electrode insulating barrier, and described
Two vias are extended to described second electrode by described source-drain electrode insulating barrier and expose described second electrode；
Forming source electrode and drain electrode on described source-drain electrode insulating barrier, wherein, described source electrode passes through institute
Stating the first via and described first electrode connects, described drain electrode is by described second via and described second electricity
Pole connects.
10. preparation method as claimed in claim 9, it is characterised in that be formed on underlay substrate
Active layer and the first electrode of described active layer and the second electrode, specifically include:
Underlay substrate sequentially forms metal-oxide film, metallic film and photoresist, by half color
Adjusting mask or gray tone to cover technique makes the formation of described photoresist have the first thickness area and the second caliper zones
The photoresist figure layer in territory；
By first step etching technics make described metallic film formed have the first pattern the first figure layer and
Described metal-oxide film is made to form described active layer；
Process to remove by ashing and there are whole photoresists of the second thickness area and there is the first caliper zones
The part photoresist in territory；
Described first figure layer is made to form described first electrode and described second electrode by second step etching technics.
11. preparation methoies as claimed in claim 10, it is characterised in that described second step etching technics
For dry etching.
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