CN113097233A

CN113097233A - Display substrate, preparation method thereof and display device

Info

Publication number: CN113097233A
Application number: CN202110356602.0A
Authority: CN
Inventors: 李栋; 张慧娟
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2021-04-01
Filing date: 2021-04-01
Publication date: 2021-07-09
Anticipated expiration: 2041-04-01
Also published as: CN113097233B

Abstract

The embodiment of the invention discloses a display substrate, a preparation method thereof and a display device, relates to the technical field of display, and is used for improving the extrusion resistance of the display substrate. The display substrate includes: a substrate and at least one transistor disposed on one side of the substrate. The transistor includes: the active layer, the first gate insulating layer, the first gate electrode, the interlayer insulating layer, the source drain electrode layer and the flat layer are sequentially stacked. The source drain electrode layer comprises a source electrode and a drain electrode. Wherein the interlayer insulating layer includes a first portion and a second portion. An orthographic projection of the first part of the interlayer insulating layer on the substrate and an orthographic projection of the first gate electrode on the substrate at least partially overlap. Relative to the substrate, the surface of the side, away from the substrate, of the first part of the interlayer insulating layer is lower than the surface of the side, away from the substrate, of the second part of the interlayer insulating layer. The display substrate, the preparation method thereof and the display device are used for displaying images.

Description

Display substrate, preparation method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to a display substrate, a preparation method of the display substrate and a display device.

Background

Organic Light Emitting Diodes (OLEDs) have been widely used in the display field because of their advantages of self-luminescence, low driving voltage, high luminous efficiency, fast response speed, flexible display, etc.

With the development of display technology, LTPS (Low Temperature polysilicon) backplane technology has a better display effect than a display panel based on a-Si (amorphous silicon) technology due to its high aperture ratio caused by its high mobility and the fact that GOA (Gate Drive on Array) can be implemented, and is receiving more and more attention.

At present, due to the structure of the LTPS backplane, poor display problems such as bright and dark spots caused by instability of transistors are easy to occur when the display device is longitudinally extruded in the display device manufactured by adopting the LTPS backplane technology.

Disclosure of Invention

The embodiment of the invention aims to provide a display substrate, a preparation method thereof and a display device, which are used for improving the extrusion resistance of the display substrate.

In order to achieve the above purpose, the embodiment of the present invention provides the following technical solutions:

in one aspect, an embodiment of the present invention provides a display substrate, which includes a substrate and at least one transistor disposed on one side of the substrate. The transistor includes: the active layer, the first gate insulating layer, the first gate electrode, the interlayer insulating layer, the source drain electrode layer and the flat layer are sequentially stacked. The source drain electrode layer comprises a source electrode and a drain electrode. Wherein the interlayer insulating layer includes a first portion and a second portion. An orthographic projection of the first part of the interlayer insulating layer on the substrate and an orthographic projection of the first gate electrode on the substrate at least partially overlap. Relative to the substrate, the surface of the side, away from the substrate, of the first part of the interlayer insulating layer is lower than the surface of the side, away from the substrate, of the second part of the interlayer insulating layer.

In the display substrate provided by some embodiments of the present disclosure, by disposing the first portion of the interlayer insulating layer corresponding to the first gate and the second portion of the interlayer insulating layer, the surface of the first portion of the interlayer insulating layer on the side away from the substrate may be recessed with respect to the second portion of the interlayer insulating layer, and the thickness of the portion of the planarization layer corresponding to the first portion of the interlayer insulating layer may be greater than the thickness of the portion of the planarization layer corresponding to the second portion of the interlayer insulating layer.

When above-mentioned display substrate received vertical extrusion stress like this, because the less position of flattening layer thickness, the extrusion stress who transmits to interlayer insulating layer is big more, this vertical extrusion stress is after flattening layer transmits to interlayer insulating layer, the pressure that receives that can make interlayer insulating layer's the first portion be less than the pressure that receives of interlayer insulating layer's the second portion, and then can reduce the pressure that the channel part of first grid and active layer received, thereby can alleviate the whole pressure that receives of transistor, guarantee the stability of transistor, improve display substrate's resistant extrusion ability, and then can avoid display substrate to appear bright dark spot etc. and show bad problem, promote the product yield.

In some embodiments, a distance between a surface of a side of the first portion of the interlayer insulating layer away from the substrate and a surface of a side of the second portion of the interlayer insulating layer away from the substrate is greater than 0nm and less than or equal to 200 nm.

In some embodiments, an orthographic projection of the first gate electrode on the substrate is located within an orthographic projection range of the first portion of the interlayer insulating layer on the substrate.

In some embodiments, an orthographic projection of the source and the drain on the substrate does not overlap with an orthographic projection of the first portion of the interlayer insulating layer on the substrate.

In some embodiments, the transistor further comprises a second gate electrode disposed between the active layer and the first gate insulating layer. The orthographic projection of the second grid electrode on the substrate is located in the orthographic projection range of the first part of the interlayer insulating layer on the substrate.

In some embodiments, the display substrate further comprises: the pixel defining layer and the plurality of spacers are arranged on one side of the flat layer, which is far away from the substrate, and are sequentially stacked. Orthographic projections of the plurality of spacers on the substrate do not overlap orthographic projections of the first portions of the interlayer insulating layers on the substrate.

In some embodiments, the second portion of the interlayer insulating layer has a thickness ranging from 500nm to 1500 nm.

In some embodiments, the interlayer insulating layer includes: the first interlayer sub-layer insulating layer and the second interlayer sub-layer insulating layer are sequentially stacked. Wherein, relative to the substrate, a surface of a side, away from the substrate, of a first sub-portion of the second inter-sub-layer insulating layer corresponding to the first portion of the inter-layer insulating layer is lower than a surface of a side, away from the substrate, of a second sub-portion of the second inter-sub-layer insulating layer corresponding to the second portion of the inter-layer insulating layer.

In some embodiments, the material of the interlayer insulating layer includes an inorganic insulating material. The material of the planarization layer includes an organic insulating material.

In some embodiments, the number of the transistors is plural, and the plural transistors include at least one of a driving transistor, a compensation transistor, and a reset transistor.

In another aspect, an embodiment of the invention provides a method for manufacturing a display substrate. The display substrate comprises at least one transistor, and the preparation method comprises the following steps: providing a substrate; an active layer, a gate insulating film, a first gate electrode and an interlayer insulating film are sequentially formed on the substrate. And in the one-time composition process, patterning the interlayer insulating film and the gate insulating film to obtain a first gate insulating layer and an interlayer insulating layer. Wherein the interlayer insulating layer includes a first portion and a second portion. An orthographic projection of a first part of the interlayer insulating layer on the substrate and an orthographic projection of the first grid electrode on the substrate are at least partially overlapped; relative to the substrate, the surface of the side, away from the substrate, of the first part of the interlayer insulating layer is lower than the surface of the side, away from the substrate, of the second part of the interlayer insulating layer. And sequentially forming a source drain electrode layer and a flat layer on one side of the interlayer insulating layer far away from the substrate. The source drain electrode layer comprises a source electrode and a drain electrode. In the one-step composition process, the patterning process is performed on the interlayer insulating film to obtain an interlayer insulating layer, and the method comprises the following steps: forming a photoresist layer on the surface of one side, away from the substrate, of the interlayer insulating film; exposing and developing the photoresist layer through a gray scale mask plate to form a patterned photoresist layer; the patterned photoresist layer is provided with a complete reserved area and a partial reserved area; the completely reserved area of the patterned photoresist layer corresponds to a second part to be formed in the interlayer insulating film, and the partially reserved area of the patterned photoresist layer corresponds to a first part to be formed in the interlayer insulating film; and etching the interlayer insulating film by taking the patterned photoresist layer as a mask to reduce the thickness of a first part to be formed in the interlayer insulating film, so as to obtain the interlayer insulating layer comprising the first part and a second part.

The beneficial effects of the preparation method of the display substrate provided by the embodiment of the invention are the same as those of the display substrates in some embodiments, and are not repeated herein.

In some embodiments, forming an interlayer insulating film includes: and sequentially forming a first inter-sub-layer insulating layer and a second inter-sub-layer insulating film on one side of the first grid electrode, which is far away from the substrate, so as to obtain the inter-layer insulating film. In a one-step composition process, the patterning process is performed on the interlayer insulating film to obtain an interlayer insulating layer, and the method comprises the following steps: forming a photoresist layer on the surface of one side, far away from the substrate, of the second interlayer insulating film; exposing and developing the photoresist layer through a gray scale mask plate to form a patterned photoresist layer; the patterned photoresist layer is provided with a complete reserved area and a partial reserved area; the completely reserved area of the patterned photoresist layer corresponds to a second sub-portion to be formed in the second interlayer insulating film, and the partially reserved area of the patterned photoresist layer corresponds to a first sub-portion to be formed in the second interlayer insulating film; etching the second inter-sub-layer insulating film by taking the patterned photoresist layer as a mask to reduce the thickness of a first sub-part to be formed in the second inter-sub-layer insulating film, so as to obtain a second inter-sub-layer insulating layer comprising the first sub-part and the second sub-part; wherein a first sub-section of the second inter-sub layer insulation layer corresponds to a first portion of the inter-layer insulation layer and a second sub-section of the second inter-sub layer insulation layer corresponds to a second portion of the inter-layer insulation layer; with respect to the substrate, a surface of a side of the first sub-portion of the second interlayer insulating layer, which is away from the substrate, is lower than a surface of a side of the second sub-portion of the second interlayer insulating layer, which is away from the substrate.

In another aspect, an embodiment of the present invention provides a display device, including the display substrate described in any one of the above embodiments.

The display substrate included in the display device has the same structure and beneficial technical effects as those of the display substrate provided in some embodiments, and details are not repeated herein.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams and are not intended to limit the actual size of products, the actual flow of methods, and the like, involved in the embodiments of the present disclosure.

Fig. 1 is a structural view of a display substrate according to a related art;

FIG. 2 is a block diagram of a display substrate according to some embodiments of the invention;

FIG. 3 is a force analysis diagram of a display substrate according to some embodiments of the invention;

FIG. 4 is a block diagram of another display substrate according to some embodiments of the invention;

FIG. 5 is a block diagram of yet another display substrate in accordance with some embodiments of the invention;

FIG. 6 is a block diagram of yet another display substrate in accordance with some embodiments of the invention;

FIG. 7 is a block diagram of yet another display substrate in accordance with some embodiments of the invention;

FIG. 8 is a block diagram of a pixel driving circuit according to some embodiments of the invention;

FIG. 9 is a flow chart of a method of fabricating a display substrate according to some embodiments of the present invention;

FIG. 10 is a flowchart of one of S300 of the flowchart of FIG. 9;

fig. 11 is another flowchart of S300 in the flowchart shown in fig. 9;

FIGS. 12 a-12 e are flow charts illustrating the preparation of a display substrate according to some embodiments of the present invention;

fig. 13 is a block diagram of a display device according to some embodiments of the invention.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "an example" or "some examples" or the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

"at least one of A, B and C" has the same meaning as "A, B or at least one of C," each including the following combination of A, B and C: a alone, B alone, C alone, a and B in combination, a and C in combination, B and C in combination, and A, B and C in combination.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

As shown in fig. 1, the display substrate in the related art generally includes: a substrate 1 ' and a transistor 2 ' arranged on one side of the substrate 1 '. The transistor 2 ' includes an active layer 21 ', a gate insulating layer 22 ', a gate electrode 23 ', an interlayer insulating layer 24 ', a source electrode, and a drain electrode, which are sequentially stacked.

In the display substrate, the thickness of the interlayer insulating layer 24' is uniform. Due to the presence of the gate electrode 23 ', a portion of the interlayer insulating layer 24 ' opposite to the gate electrode 23 ' may be made convex.

Thus, when the display substrate is longitudinally pressed, the pressure f1 'borne by the convex portion of the interlayer insulating layer 24' is greater than the pressure f2 'borne by the other portion of the interlayer insulating layer 24'. Since the protruding portion of the interlayer insulating layer 24 ' is opposite to the channel portions of the gate 23 ' and the active layer 21 ', the channel portions of the gate 23 ' and the active layer 21 ' are subjected to a large pressure, and thus the performance of the transistor is unstable, and poor display phenomena such as bright and dark spots on the display substrate are easily caused.

Based on this, the embodiment of the invention provides a display substrate 100.

In some examples, as shown in fig. 2-8, the display substrate 100 includes a substrate 1.

The structure of the substrate 1 includes various structures, and can be selectively arranged according to actual needs. For example, the substrate 1 is a blank substrate base plate. As another example, the substrate 1 includes a blank substrate base plate and a functional thin film (which may include a buffer layer, for example) provided on the blank substrate base plate.

The types of the blank substrate base plate include various types, and the arrangement can be selected according to actual needs.

For example, the blank substrate may be a rigid substrate. The rigid substrate may be, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate. In this case, the display substrate 100 may be a rigid display substrate.

As another example, the blank substrate may be a flexible substrate. The flexible substrate may be, for example, a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate) substrate, or a PI (Polyimide) substrate. In this case, the display substrate 100 may be a flexible display substrate.

In some examples, as shown in fig. 2-7, the display substrate 100 further includes at least one transistor 2 disposed on one side of the substrate 1. Each transistor 2 may include an active layer 21, a first gate insulating layer 22, a first gate electrode 23, an interlayer insulating layer 24, a source/drain electrode layer 25, and a planarization layer 26, which are sequentially stacked. The source drain electrode layer 25 includes a source electrode 251 and a drain electrode 252.

Illustratively, the material of the active layer 21 may be LTPS or metal oxide, etc. The metal Oxide may be IGZO (Indium Gallium Zinc Oxide).

Illustratively, the material of the first gate insulating layer 22 is an inorganic material. For example, the inorganic material may be at least one of silicon nitride and silicon oxide. The thickness of the first gate insulating layer 22 is uniform.

Illustratively, the material of the interlayer insulating layer 24 is an inorganic material. For example, the inorganic material may be at least one of silicon nitride and silicon oxide.

In some examples, as shown in fig. 2, the interlayer insulating layer 24 includes a first portion and a second portion. Wherein a first portion of the interlayer insulating layer 24 may be located at the thinned region C1, and a second portion of the interlayer insulating layer 24 may be located at the non-thinned region C2.

Illustratively, as shown in fig. 2 and 4, in the cross-sectional view of the transistor 2, the boundary between the aforementioned thinned region C1 and the non-thinned region C2 is located at a position where the thickness of the interlayer insulating layer 24 has just changed in a direction parallel to the substrate 1 and directed toward the first gate 23 from the source 251 or directed toward the first gate 23 from the drain 252. Here, in a cross-sectional view of the transistor, the non-thinned region C2 can be considered to include two portions, one of which is located between the source 251 and the thinned region C1, and the other of which is located between the drain 252 and the thinned region C1.

Illustratively, as shown in fig. 3, with respect to the substrate 1, a surface of a side of the first portion of the interlayer insulating layer 24 away from the substrate 1 is lower than a surface of a side of the second portion of the interlayer insulating layer 24 away from the substrate 1. That is, the distance H1 between the surface of the first portion of the interlayer insulating layer 24 on the side away from the substrate 1 and the substrate 1 is smaller than the distance H2 between the surface of the second portion of the interlayer insulating layer 24 on the side away from the substrate 1 and the substrate 1. "pitch" refers to the distance between two surfaces in a direction perpendicular to the substrate 1.

This makes it possible to reduce the space between the substrate 1 and the surface of the first portion of the interlayer insulating layer 24 on the side away from the substrate 1, and to make the first portion of the interlayer insulating layer 24 in a recessed state compared to the second portion of the interlayer insulating layer 24.

It is to be noted that the surface of the first portion of the interlayer insulating layer 24 on the side away from the substrate 1 may include two portions of the surface in consideration of the process of preparing the interlayer insulating layer 24. Wherein, a part of the surface may be parallel to the substrate 1, and another part of the surface may have an angle with the substrate 1 and is used for connecting the part of the surface parallel to the substrate 1 and the surface of the second part of the interlayer insulating layer 24 on the side away from the substrate 1.

The "surface of the first portion of the interlayer insulating layer 24 on the side away from the substrate 1" referred to herein means parallel to a part of the surface of the substrate 1. Where "parallel" is not strictly parallel, the portion of the surface and the substrate 1 may have a deviation of, for example, ± 5 ° (or other degrees) due to process tolerances, and may also be considered parallel.

Illustratively, an orthographic projection of the first portion of the interlayer insulating layer 24 on the substrate 1 and an orthographic projection of the first gate electrode 23 on the substrate 1 at least partially overlap. That is, the position of the first portion of the interlayer insulating layer 24 corresponds to the position of the first gate electrode 23.

For example, an orthogonal projection of the first portion of the interlayer insulating layer 24 on the substrate 1 and an orthogonal projection of the first gate electrode 23 on the substrate 1 overlap.

As another example, as shown in fig. 4, an orthogonal projection of the first portion of the interlayer insulating layer 24 on the substrate 1 and an orthogonal projection of the first gate electrode 23 on the substrate 1 overlap. At this time, an orthographic projection area of the first portion of the interlayer insulating layer 24 on the substrate 1 and an orthographic projection area of the first gate electrode 23 on the substrate 1 are equal, and an orthographic projection shape of the first portion of the interlayer insulating layer 24 on the substrate 1 and an orthographic projection shape of the first gate electrode 23 on the substrate 1 are equal.

As another example, as shown in fig. 2 and 6, an orthogonal projection of the first gate 23 on the substrate 1 is located within an orthogonal projection range of the first portion of the interlayer insulating layer 24 on the substrate 1. At this time, an orthographic projection area of the first gate electrode 23 on the substrate 1 is smaller than an orthographic projection area of the first portion of the interlayer insulating layer 24 on the substrate 1.

Illustratively, the material of the planarization layer 26 is an organic material, and may be any one of an organic resin and polyimide, for example.

For example, as shown in fig. 3, the surface of the side of the planarization layer 26 away from the substrate 1 is a relatively flat surface.

Since the distance H1 between the surface of the first portion of the interlayer insulating layer 24 on the side away from the substrate 1 and the substrate 1 is smaller than the distance H2 between the surface of the second portion of the interlayer insulating layer on the side away from the substrate 1 and the substrate 1, after the planarization layer 26 is formed on the side of the interlayer insulating layer 24 away from the substrate 1, the thickness H3 of the portion of the planarization layer 26 corresponding to the first portion of the interlayer insulating layer 24 can be made larger than the thickness H4 of the portion of the planarization layer 26 corresponding to the second portion of the interlayer insulating layer 24.

Note that the young's modulus E1 of the inorganic material is much larger than the young's modulus E2 of the organic material.

When the display substrate 100 in this embodiment is longitudinally pressed (at least with a force in a direction perpendicular to the substrate 1), since the material of the interlayer insulating layer 24 is an inorganic material and the material of the planarization layer 26 is an organic material, the interlayer insulating layer 24 is hardly deformed or the deformation is small, which can be ignored, and the thickness variation of the planarization layer 26 at different positions is uniform, for example.

Illustratively, when the display substrate 100 is subjected to the longitudinal pressing force F transmitted to the interlayer insulating layer 24 through the planarization layer 26, the distribution and magnitude of the pressing force transmitted to the interlayer insulating layer 24 through different thickness positions of the planarization layer 26 are different. Law and formula of transmission and distribution of stress

(where f is the pressure transmitted to the interlayer insulating layer 24, E is the Young's modulus of the planarization layer 26, Δ H is the amount of change in thickness of the planarization layer 26 after being pressed, and H is the thickness of the planarization layer 26). As can be seen, E and Δ H are constant values, the smaller the thickness of the planarization layer 26 is, the smaller the thickness thereof isThe greater the pressure transmitted to the interlayer insulating layer 24.

Since the thickness H3 of the portion of the planarization layer 26 corresponding to the first portion of the interlayer insulating layer 24 is increased, and the thickness H3 of the portion of the planarization layer 26 corresponding to the first portion of the interlayer insulating layer 24 is greater than the thickness H4 of the portion of the planarization layer 26 corresponding to the second portion of the interlayer insulating layer 24, the pressure transmitted to the first portion of the interlayer insulating layer 24 through the planarization layer 26 is less than the pressure transmitted to the second portion of the interlayer insulating layer 24 through the planarization layer 26, that is, the longitudinal compressive stress F is mainly borne by the second portion of the interlayer insulating layer 24, which reduces the pressure borne by the channel portions of the first gate electrode 23 and the active layer 21.

Therefore, according to the display substrate 100 provided by some embodiments of the present disclosure, by disposing the first portion of the interlayer insulating layer 24 corresponding to the first gate 23 and the second portion of the interlayer insulating layer 24, the surface of the first portion of the interlayer insulating layer 24 away from the substrate 1 is opposite to the surface of the substrate 1 lower than the surface of the second portion of the interlayer insulating layer 24 away from the substrate 1, so that the first portion of the interlayer insulating layer 24 is recessed relative to the second portion of the interlayer insulating layer 24, and the thickness H3 of the portion of the planarization layer 26 corresponding to the first portion of the interlayer insulating layer 24 is greater than the thickness H4 of the portion of the planarization layer 26 corresponding to the second portion of the interlayer insulating layer 24.

Thus, when the display substrate 100 receives the longitudinal extrusion stress F, the extrusion stress transmitted to the interlayer insulating layer 24 is larger at the position where the thickness of the flat layer 26 is smaller, and after the longitudinal extrusion stress F is transmitted to the interlayer insulating layer 24 through the flat layer 26, the pressure received by the first portion of the interlayer insulating layer 24 is smaller than the pressure received by the second portion of the interlayer insulating layer 24, so that the pressures received by the channel portions of the first gate 23 and the active layer 21 can be reduced, thereby relieving the pressure received by the transistor 2 as a whole, ensuring the stability of the transistor 2, improving the extrusion resistance of the display substrate 100, further avoiding the display defects such as bright and dark spots of the display substrate 100, and improving the product yield.

In some embodiments, as shown in fig. 3, a distance Δ h between a surface of a first portion of the interlayer insulating layer 24 on a side away from the substrate 1 and a surface of a second portion of the interlayer insulating layer 24 on a side away from the substrate 1 is greater than 0nm and less than or equal to 200 nm.

Illustratively, Δ h may be 1nm, 50nm, 100nm, 150nm, or 200nm, etc.

By setting Δ h to the above range, the display substrate 100 in this embodiment can ensure that the first portion of the interlayer insulating layer 24 still has good insulating performance or crosstalk prevention capability while ensuring that the beneficial effects in the above embodiments are achieved, and the situation that the signal interference occurs between the trace on the side of the interlayer insulating layer 24 away from the substrate 1 and the first gate 23 is prevented from affecting the working performance of the transistor 2.

In some embodiments, as shown in FIG. 3, the thickness H5 of the second portion of the interlayer insulating layer 24 ranges from 500nm to 1500 nm.

Illustratively, H5 may be 500nm, 1000nm, 1500nm, or the like.

By making the second portion of the interlayer insulating layer 24 have a larger thickness, the first portion of the interlayer insulating layer 24 can be made to have a larger thickness while the thickness of the first portion of the interlayer insulating layer 24 is smaller than the thickness of the second portion of the interlayer insulating layer 24. This is advantageous in ensuring that the first portion of the interlayer insulating layer 24 has good crosstalk prevention capability.

The interlayer insulating layer 24 may have various structures, for example, a single-layer structure or a multilayer structure, and may be provided as needed.

In the case that the interlayer insulating layer 24 has a single-layer structure, the manner of disposing the interlayer insulating layer 24 may refer to the description in some of the above examples, and will not be described herein again.

When the interlayer insulating layer 24 has a structure in which a plurality of layers are stacked, a structure in which the interlayer insulating layer 24 has two layers will be described as an example.

In some embodiments, as shown in fig. 5, the interlayer insulating layer 24 includes: the first interlayer insulating layer 241 and the second interlayer insulating layer 242 are sequentially stacked. With respect to the substrate 1, a surface of a side, away from the substrate 1, of a first sub-portion of the second inter-sub-layer insulating layer 242 corresponding to the first portion of the inter-layer insulating layer 24 is lower than a surface of a side, away from the substrate 1, of a second sub-portion of the second inter-sub-layer insulating layer 242 corresponding to the second portion of the inter-layer insulating layer 24.

In this example, the second interlayer sub-layer insulating layer 242 may be disposed in a manner that refers to the description of the interlayer insulating layer 24 in some of the above examples, and is not described herein again.

The relationship between the third sub-portion of the first inter-sub-layer insulating layer 241 corresponding to the first portion of the interlayer insulating layer 24 and the fourth sub-portion of the first inter-sub-layer insulating layer 241 corresponding to the second portion of the interlayer insulating layer 24 is not limited, and may be selected according to actual needs.

For example, as shown in fig. 5, the thickness of the third sub-section of the first inter-sub-layer insulating layer 241, which corresponds to the first portion of the interlayer insulating layer 24, is equal to the thickness of the fourth sub-section of the first inter-sub-layer insulating layer 241, which corresponds to the second portion of the interlayer insulating layer 24.

At this time, the thickness of the first sub-section of the second interlayer sub-layer 242 corresponding to the first portion of the interlayer insulating layer 24 may be greater than 0, or equal to 0.

For another example, a thickness of a third sub-section of the first inter-sub-layer insulating layer 241 corresponding to the first portion of the inter-layer insulating layer 24 is smaller than a thickness of a fourth sub-section of the first inter-sub-layer insulating layer 241 corresponding to the second portion of the inter-layer insulating layer 24.

At this time, a portion of the second interlayer sub-layer 242 corresponding to the first portion of the interlayer insulating layer 24 has a thickness of 0, and a third sub-portion of the first interlayer sub-layer 241 corresponding to the first portion of the interlayer insulating layer 24 is exposed.

By providing the interlayer insulating layer 24 in a multilayer laminated structure, the thickness adjustment range of the portion of the interlayer insulating layer 24 located in the thinning-out region C1 can be increased by the multilayer interlayer insulating layer in the interlayer insulating layer 24.

In some embodiments, as shown in fig. 2 to 7, the orthographic projection of the source electrode 251 and the drain electrode 252 on the substrate 1 does not overlap with the orthographic projection of the first portion of the interlayer insulating layer 24 on the substrate 1.

Therefore, the source electrode 251 and the drain electrode 252 can be prevented from covering the first portion of the interlayer insulating layer 24, which causes the first portion of the interlayer insulating layer 24 to form a protrusion on the surface of the side away from the substrate 1, and further avoids the increase of the extrusion stress borne by the first portion of the interlayer insulating layer 24 and the increase of the risk of the display failure phenomenon of the display substrate 100 when the display substrate 100 is longitudinally extruded.

The structure of the transistor 2 includes a plurality of kinds, and when the display substrate 100 includes a plurality of transistors 2, the plurality of transistors 2 may have the same structure or different structures.

Illustratively, the transistor 2 may be a single-gate transistor or a double-gate transistor.

In some embodiments, as shown in fig. 6, in case the transistor 2 is a double gate transistor, the transistor 2 further comprises a second gate electrode 27 disposed between the active layer 21 and the first gate insulating layer 22. An orthogonal projection of the second gate electrode 27 on the substrate 1 is located within an orthogonal projection range of the first portion of the interlayer insulating layer 24 on the substrate 1.

Illustratively, an orthographic projection of the second gate electrode 27 on the substrate 1 overlaps with an orthographic projection of the first portion of the interlayer insulating layer 24 on the substrate 1. Alternatively, as shown in fig. 6, an area of an orthographic projection of the second gate electrode 27 on the substrate 1 is smaller than an area of an orthographic projection of the first portion of the interlayer insulating layer 24 on the substrate 1.

Note that in the case where the transistor 2 further includes the second gate electrode 27, the transistor 2 further includes a second gate insulating layer 28 between the active layer 21 and the second gate electrode 27. The material of the second gate insulating layer 28 is an inorganic material. For example, the inorganic material may be at least one of silicon nitride and silicon oxide. The thickness of the second gate insulating layer 28 is uniform.

If the thickness of the first portion of the interlayer insulating layer 24 is equal to the thickness of the second portion of the interlayer insulating layer 24, the difference between the distance between the surface of the first portion of the interlayer insulating layer 24 remote from the substrate 1 and the distance between the surface of the second portion of the interlayer insulating layer 24 remote from the substrate 1 and the substrate 1 is larger in the case where the second gate electrode 27 is provided than in the case where only the first gate electrode 23 is provided. Accordingly, when the display substrate 100 is pressed in the longitudinal direction, the first gate electrode 23, the second gate electrode 27 and the channel portion of the active layer 21 are pressed more.

According to the embodiment of the invention, the distance between the surface of one side, away from the substrate 1, of the first part of the interlayer insulating layer 24 and the substrate 1 is smaller than the distance between the surface of one side, away from the substrate 1, of the second part of the interlayer insulating layer 24 and the substrate 1, so that when the display substrate 100 is subjected to longitudinal extrusion force, the pressure on the channel parts of the first gate 23, the second gate 27 and the active layer 21 can be effectively reduced, the stability of the transistor 2 is ensured, the extrusion resistance of the display substrate 100 is improved, the problem of poor display of the display substrate 100 is avoided, and the product yield is improved.

It should be noted that, in the embodiment of the present invention, the relationship between the orthographic projection of the first gate 23 on the substrate 1 and the orthographic projection of the second gate 27 on the substrate 1 is not limited as long as the orthographic projections of the first gate 23 and the second gate 27 on the substrate 1 are both located within the range of the orthographic projection of the first portion of the interlayer insulating layer 24 on the substrate 1. For example, the orthographic projection of the first gate 23 on the substrate 1 is within the orthographic projection range of the second gate 27 on the substrate 1, or the orthographic projection of the second gate 27 on the substrate 1 is within the orthographic projection range of the first gate 23 on the substrate 1.

In some embodiments, the display substrate 100 may further include a light emitting device disposed on a side of the pixel defining layer away from the substrate 1.

The types of the light emitting devices include various types, and the arrangement can be selected according to actual needs.

For example, the Light Emitting device may be an OLED, a QLED (Quantum Dot Light Emitting diode), an LED (Light Emitting diode), or the like.

The present example is schematically illustrated by taking the above-described light emitting device as an OLED.

In some examples, as shown in fig. 7, the display substrate 100 further includes: a pixel defining layer 3 and a plurality of spacers 4 disposed on the side of the planarization layer 26 away from the substrate 1 and stacked in this order. The orthographic projection of the plurality of spacers 4 on the substrate 1 does not overlap the orthographic projection of the first portion of the interlayer insulating layer 24 on the substrate 1.

In some examples, the pixel defining layer 3 has an opening. The light emitting device may include at least an anode, a light emitting layer, and a cathode stacked in this order. The anode may be disposed between the pixel defining layer 3 and the planarization layer 26, and at least a portion of the light emitting layer may be located within the opening of the pixel defining layer 3.

For example, the light emitting layer may be formed by an evaporation process according to an embodiment of the present invention. Based on this, the spacer 4 can be used to support a FMM (Fine Metal Mask) used in an evaporation process.

When the display substrate 100 is longitudinally pressed, the spacers 4 are subjected to a large pressure. By making the orthographic projection of the spacer 4 on the substrate 1 not overlap with the orthographic projection of the first part of the interlayer insulating layer 24 on the substrate 1, a larger distance can be kept between the first part of the interlayer insulating layer 24 and the spacer 4 in the direction parallel to the substrate 1, which is beneficial to reducing the pressure transmitted to the first part of the interlayer insulating layer 24, the gate electrode and the channel part of the active layer 21, and reducing the risk of display failure phenomenon of the display substrate 100.

In some embodiments, the display substrate 100 further includes: a plurality of pixel driving circuits P provided on one side of the substrate 1.

The structure of the pixel driving circuit P may include various structures, and may be selectively arranged according to actual needs. For example, the structure of the pixel driving circuit P may include structures such as "2T 1C", "6T 1C", "7T 1C", "6T 2C" or "7T 2C". Here, "T" is represented as a thin film transistor, the number located in front of "T" is represented as the number of thin film transistors, "C" is represented as a storage capacitor, and the number located in front of "C" is represented as the number of storage capacitors.

It should be noted that the pixel driving circuit P may include a driving transistor T1. Of course, the pixel driving circuit P may further include a compensation transistor T2 and/or a reset transistor T3.

In some embodiments, the display substrate 100 includes a plurality of transistors 2. The plurality of transistors 2 includes at least one of a driving transistor T1, a compensation transistor T2, and a reset transistor T3.

Exemplarily, the plurality of transistors 2 may belong to at least one pixel driving circuit P. For example, in the case where the plurality of transistors 2 includes the driving transistor T1, the compensation transistor T2, and the reset transistor T3, the driving transistor T1, the compensation transistor T2, and the reset transistor T3 may belong to the same pixel driving circuit P or may belong to different pixel driving circuits P.

As shown in fig. 8, the following description will be made taking as an example a configuration in which the pixel drive circuit P is 7T 1C. Among them, the transistor 2 may include a driving transistor T1, a compensating transistor T2, and a reset transistor T3.

By adopting the above arrangement of the interlayer insulating layer 24 in the driving transistor T1, it is possible to avoid affecting the transmission of the driving current and thus the light emitting state of the light emitting device. By adopting the above arrangement for the interlayer insulating layer 24 in the compensation transistor T2, it is possible to avoid affecting the transmission of the data signal during the writing of the data signal to the gate of the driving transistor T1 through the compensation transistor T2, and thus avoid affecting the compensation of the threshold voltage of the driving transistor T1. By adopting the above arrangement manner for the interlayer insulating layer 24 in the reset transistor T3, it is possible to avoid affecting the transmission of the reset signal, and further, it is possible to ensure the reset effect on the gate of the driving transistor T1, and avoid the signal residue of the previous frame display.

In another aspect, embodiments of the present invention provide a method for manufacturing a display substrate. Wherein the display substrate 100 comprises at least one transistor 2. Based on this, as shown in fig. 9, the method for manufacturing a display substrate includes: s100 to S400.

S100, providing a substrate 1.

Optionally, the structure of the substrate 1 may refer to the description in some embodiments above, and is not described here again.

S200, as shown in fig. 12a, an active layer 21, a first gate insulating film 22a, a first gate electrode 23, and an interlayer insulating film 24a are sequentially formed on the substrate 1.

For example, in the process of forming the active layer 21, an active film may be formed by a deposition process, and then patterned by a photolithography process, thereby forming the active layer 21.

For example, in the process of forming the first gate insulating film 22a, a PECVD (Plasma Enhanced Chemical Vapor Deposition) process, a CVD (Chemical Vapor Deposition) process, or the like may be used.

For example, in the process of forming the first gate electrode 23, a gate conductive film may be formed by a deposition process, and then patterned by a photolithography process to form the first gate electrode 23.

Illustratively, in the process of forming the interlayer insulating film 24a, for example, a PECVD process, a CVD process, or the like may be used.

S300, as shown in fig. 12b and 12c, in the primary patterning process, the interlayer insulating film 24a and the first gate insulating film 22a are patterned to obtain the first gate insulating layer 22 and the interlayer insulating layer 24. The interlayer insulating layer 24 includes a first portion and a second portion. An orthogonal projection of the first portion of the interlayer insulating layer 24 on the substrate 1 and an orthogonal projection of the first gate electrode 23 on the substrate 1 at least partially overlap. With respect to the substrate 1, a surface of a side of the interlayer insulating layer 24 away from the substrate 1 is lower in a first portion than a surface of a side of the interlayer insulating layer 24 away from the substrate 1.

In some embodiments, as shown in fig. 10, in the above S300, the interlayer insulating film 24a is patterned in a single patterning process to obtain the interlayer insulating layer 24, including S310a to S330 a.

S310a, a photoresist layer is formed on the surface of the interlayer insulating film 24a on the side away from the substrate 1.

Illustratively, the photoresist layer may be formed using a coating process.

The material of the photoresist layer comprises a plurality of materials, and the materials can be selected according to actual needs. For example, the material of the photoresist layer may be a positive photoresist, or the material of the photoresist layer may be a negative photoresist. The embodiment of the invention takes the material of the photoresist layer as an example of a positive photoresist, and is schematically illustrated.

And S320a, exposing and developing the photoresist layer through the gray-scale mask plate to form a patterned photoresist layer.

The gray scale mask plate has various types and can be selectively arranged according to actual needs. For example, the gray-scale mask can be a halftone mask or a gray-scale mask. The embodiment of the invention takes a halftone mask as an example for schematic explanation.

The patterned photoresist layer may be formed by exposing and developing the photoresist layer through a half-tone mask. The patterned photoresist layer has a completely reserved region and a partially reserved region.

The completely reserved area of the patterned photoresist layer means that the photoresist in the area is not removed and still covers the surface of the area of the interlayer insulating film 24a corresponding to the completely reserved area. The partial remaining region in the patterned photoresist layer means that the photoresist in the region is partially removed in the thickness direction, that is, the planar area of the photoresist in the region is unchanged, the thickness is reduced, and the photoresist layer in the region still covers the surface of the region corresponding to the partial remaining region of the interlayer insulating film 24 a.

Different areas of the patterned photoresist layer correspond to different areas in the interlayer insulating film 24a, that is, a completely reserved area of the patterned photoresist layer corresponds to a second portion to be formed in the interlayer insulating film 24a, and a partially reserved area of the patterned photoresist layer corresponds to a first portion to be formed in the interlayer insulating film 24 a.

Note that the source 251 and the drain 252 in the transistor 2 are electrically connected to the active layer 21 through the first via G1 and the second via G2, respectively. The first and second vias G1 and G2 each penetrate the first gate insulating layer 22 and the interlayer insulating layer 24.

Based on this, the patterned photoresist layer also includes a completely removed region. The completely removed region means that the photoresist in the region is completely removed to expose a part of the side surface of the interlayer insulating film 24a facing away from the substrate 1.

The completely removed region corresponds to a first via and a second via to be formed.

S330a, as shown in fig. 12b and 12c, the interlayer insulating film 24a is etched by using the patterned photoresist layer as a mask, so as to reduce the thickness of a first portion to be formed in the interlayer insulating film 24a, thereby obtaining the interlayer insulating layer 24 including the first portion and the second portion.

Illustratively, the etching of the interlayer insulating film 24a with the patterned photoresist layer as a mask includes, for example: and etching the interlayer insulating film 24a for the first time by using the patterned photoresist layer as a mask, so that the regions of the interlayer insulating film 24a corresponding to the first via hole and the second via hole to be formed penetrate through the interlayer insulating film 24a and the first gate insulating film 22a, thereby forming a first via hole G2 and a second via hole G2.

The completely remaining region and the partially remaining region of the patterned photoresist layer protect a first portion to be formed and a second portion to be formed in the interlayer insulating film 24a, so that when the interlayer insulating film 24a is etched for the first time, only the completely removed region of the interlayer insulating film 24a may be etched to form the first via hole G1 and the second via hole G2. In the specific etching, a dry etching process or a wet etching process may be used to etch the interlayer insulating film 24a and the first gate insulating film 22 a.

And then, removing the part of the patterned photoresist layer, which is positioned in the partial reserved area, so as to perform second etching on the interlayer insulating film 24a subjected to the first etching, namely, etching the first part to be formed in the interlayer insulating film 24a, and reducing the thickness of the first part to be formed in the interlayer insulating film 24 a.

After that, the interlayer insulating layer 24 and the first gate insulating layer 22 can be obtained.

S400, as shown in fig. 12d and 12e, the source/drain electrode layer 25 and the planarization layer 26 are sequentially formed on the interlayer insulating layer 24 on the side away from the substrate 1.

For example, in the process of forming the source/drain electrode layer 25, a deposition process may be used to form a source/drain electrode film, and then a photolithography process may be used to pattern the source/drain electrode film to form the source/drain electrode layer 25. Wherein the source drain electrode layer 25 includes a source electrode 251 and a drain electrode 252.

Illustratively, the above-described planarization layer 26 may be formed using a coating process.

The beneficial technical effects of the preparation method of the display substrate provided by the embodiment of the invention are the same as those of the display substrate 100 provided in some embodiments, and are not described herein again.

In some embodiments, as shown in fig. 12a, in the above S200, forming the interlayer insulating film 24a includes: a first interlayer insulating film 241a and a second interlayer insulating film 242a are sequentially formed on the side of the first gate 23 away from the substrate 1, resulting in an interlayer insulating film 24 a.

Wherein the thickness of the interlayer insulating film 24a is in the range of 500nm to 1500 nm.

Illustratively, the thickness of the interlayer insulating film 24a may be 500nm, 1000nm, or 1500 nm.

In addition, as shown in fig. 11, in S300, the interlayer insulating film 24a is patterned in the primary patterning process to obtain the interlayer insulating layer 24, which may include S310b to S320 b.

S310b, a photoresist layer is formed on the surface of the second inter-sublayer insulating film 242a on the side away from the substrate 1.

In this example, the process of forming the photoresist layer on the surface of the second interlayer insulating film 242a on the side away from the substrate 1 is the same as the process of S310a described above, and will not be described again here.

And S320b, exposing and developing the photoresist layer through the gray-scale mask plate to form a patterned photoresist layer. The patterned photoresist layer has a fully preserved region and a partially preserved region. The completely reserved area of the patterned photoresist layer corresponds to a second sub-portion to be formed in the second inter-sub-layer insulating film 242a, and the partially reserved area of the patterned photoresist layer corresponds to a first sub-portion to be formed in the second inter-sub-layer insulating film 242 a.

In this example, the description of the processes of exposing and developing the photoresist layer and the structure of the patterned photoresist layer can refer to the description in S320a, and will not be repeated here.

S330b, as shown in fig. 12b and 12c, the patterned photoresist layer is used as a mask to etch the second inter-sub-layer insulating film 242a, so as to reduce the thickness of the first sub-portion to be formed in the second inter-sub-layer insulating film 242a, thereby obtaining the second inter-sub-layer insulating film 242 including the first sub-portion and the second sub-portion. A first sub-portion of the second inter-sub-layer insulating layer 242 corresponds to a first portion of the inter-layer insulating layer 24, and a second sub-portion of the second inter-sub-layer insulating layer 242 corresponds to a second portion of the inter-layer insulating layer 24. With respect to the substrate 1, a first sub-portion of the second interlayer sub-layer insulating layer 242 is lower than a surface of the second interlayer sub-layer insulating layer 242 in order of being away from the substrate 1.

Illustratively, the thickness of the third sub-section of the first inter-sub-layer insulating layer 241 is equal to the thickness of the fourth sub-section of the first inter-sub-layer insulating layer 241. Alternatively, the thickness of the third sub-section of the first inter-sub-layer insulating layer 241 is smaller than the thickness of the fourth sub-section of the first inter-sub-layer insulating layer 241.

In this example, in the case that the thickness of the third sub-portion in the first inter-sub-layer insulating layer 241 is equal to the thickness of the fourth sub-portion in the first inter-sub-layer insulating layer 241, the process of etching the second inter-sub-layer insulating film 242a may refer to the description in S330a, and will not be described herein again.

In the case where the thickness of the third sub-section in the first interlayer insulating layer 241 is smaller than the thickness of the fourth sub-section in the first interlayer insulating layer 241, the thickness of the third sub-section to be formed in the first interlayer insulating film 241a may be reduced at the same time in the above-described S330 b.

An embodiment of the present invention provides a display device 1000, as shown in fig. 13, where the display device 1000 includes any one of the display substrates 100 described above.

The beneficial effects that can be achieved by the display device 1000 according to some embodiments of the present invention are the same as those that can be achieved by the display substrate 100 according to some embodiments described above, and are not described herein again.

In some embodiments, curved display device 1000 may be any device that displays text or images, whether in motion (e.g., video) or stationary (e.g., still images). More particularly, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, Personal Digital Assistants (PDAs), hand-held or portable computers, Global Positioning System (GPS) receivers/navigators, cameras, motion Picture Experts Group (MP 4) video players, video cameras, game consoles, wrist watches, clocks, calculators, television monitors, computer monitors, automobile displays (e.g., odometer display, etc.), navigators, cockpit controls and/or displays, displays of camera views (e.g., displays of rear view cameras in vehicles), electronic photographs, electronic billboards or signs, video game consoles, and the like, Projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images for a piece of jewelry), and the like.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can appreciate that changes or substitutions within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A display substrate, comprising:

a substrate; and the number of the first and second groups,

at least one transistor disposed on one side of the substrate; the transistor includes: the active layer, the first gate insulating layer, the first gate electrode, the interlayer insulating layer, the source drain electrode layer and the flat layer are sequentially stacked; the source drain electrode layer comprises a source electrode and a drain electrode;

wherein the interlayer insulating layer includes a first portion and a second portion; an orthographic projection of a first part of the interlayer insulating layer on the substrate and an orthographic projection of the first grid electrode on the substrate are at least partially overlapped;

relative to the substrate, the surface of the side, away from the substrate, of the first part of the interlayer insulating layer is lower than the surface of the side, away from the substrate, of the second part of the interlayer insulating layer.

2. The display substrate according to claim 1, wherein a distance between a surface of a first portion of the interlayer insulating layer on a side away from the substrate and a surface of a second portion of the interlayer insulating layer on a side away from the substrate is greater than 0nm and less than or equal to 200 nm.

3. The display substrate according to claim 1, wherein an orthographic projection of the first gate electrode on the substrate is within an orthographic projection range of the first portion of the interlayer insulating layer on the substrate.

4. The display substrate according to claim 1, wherein an orthographic projection of the source electrode and the drain electrode on the substrate does not overlap with an orthographic projection of the first portion of the interlayer insulating layer on the substrate.

5. The display substrate according to claim 1, wherein the transistor further comprises a second gate electrode disposed between the active layer and the first gate insulating layer;

the orthographic projection of the second grid electrode on the substrate is located in the orthographic projection range of the first part of the interlayer insulating layer on the substrate.

6. The display substrate of claim 1, further comprising: the pixel defining layer and the plurality of spacers are arranged on one side of the flat layer, which is far away from the substrate, and are sequentially stacked;

orthographic projections of the plurality of spacers on the substrate do not overlap orthographic projections of the first portions of the interlayer insulating layers on the substrate.

7. The display substrate according to claim 1, wherein the second portion of the interlayer insulating layer has a thickness in a range of 500nm to 1500 nm.

8. The display substrate according to claim 1, wherein the interlayer insulating layer comprises: the first interlayer sub-layer insulating layer and the second interlayer sub-layer insulating layer are sequentially stacked;

wherein, relative to the substrate, a surface of a side, away from the substrate, of a first sub-portion of the second inter-sub-layer insulating layer corresponding to the first portion of the inter-layer insulating layer is lower than a surface of a side, away from the substrate, of a second sub-portion of the second inter-sub-layer insulating layer corresponding to the second portion of the inter-layer insulating layer.

9. The display substrate according to claim 1, wherein a material of the interlayer insulating layer comprises an inorganic insulating material;

the material of the planarization layer includes an organic insulating material.

10. The display substrate according to any one of claims 1 to 9, wherein the number of the transistors is plural, and the plural transistors include at least one of a driving transistor, a compensating transistor, and a reset transistor.

11. A method for preparing a display substrate, wherein the display substrate comprises at least one transistor, the method comprising:

providing a substrate;

sequentially forming an active layer, a gate insulating film, a first gate electrode and an interlayer insulating film on the substrate;

in a primary composition process, patterning the interlayer insulating film and the gate insulating film to obtain a first gate insulating layer and an interlayer insulating layer; wherein the interlayer insulating layer includes a first portion and a second portion; an orthographic projection of a first part of the interlayer insulating layer on the substrate and an orthographic projection of the first grid electrode on the substrate are at least partially overlapped; relative to the substrate, the surface of the side, away from the substrate, of the first part of the interlayer insulating layer is lower than the surface of the side, away from the substrate, of the second part of the interlayer insulating layer;

sequentially forming a source drain electrode layer and a flat layer on one side of the interlayer insulating layer far away from the substrate; the source drain electrode layer comprises a source electrode and a drain electrode;

in the one-step composition process, the patterning process is performed on the interlayer insulating film to obtain an interlayer insulating layer, and the method comprises the following steps:

forming a photoresist layer on the surface of one side, away from the substrate, of the interlayer insulating film;

exposing and developing the photoresist layer through a gray scale mask plate to form a patterned photoresist layer; the patterned photoresist layer is provided with a complete reserved area and a partial reserved area; the completely reserved area of the patterned photoresist layer corresponds to a second part to be formed in the interlayer insulating film, and the partially reserved area of the patterned photoresist layer corresponds to a first part to be formed in the interlayer insulating film;

and etching the interlayer insulating film by taking the patterned photoresist layer as a mask to reduce the thickness of a first part to be formed in the interlayer insulating film, so as to obtain the interlayer insulating layer comprising the first part and a second part.

12. The method of manufacturing a display substrate according to claim 11, wherein forming an interlayer insulating film comprises:

sequentially forming a first inter-sub-layer insulating film and a second inter-sub-layer insulating film on one side of the first grid electrode, which is far away from the substrate, so as to obtain the inter-layer insulating film;

in a one-step composition process, the patterning process is performed on the interlayer insulating film to obtain an interlayer insulating layer, and the method comprises the following steps:

forming a photoresist layer on the surface of one side, far away from the substrate, of the second interlayer insulating film;

exposing and developing the photoresist layer through a gray scale mask plate to form a patterned photoresist layer; the patterned photoresist layer is provided with a complete reserved area and a partial reserved area; the completely reserved area of the patterned photoresist layer corresponds to a second sub-portion to be formed in the second interlayer insulating film, and the partially reserved area of the patterned photoresist layer corresponds to a first sub-portion to be formed in the second interlayer insulating film;

etching the second inter-sub-layer insulating film by taking the patterned photoresist layer as a mask to reduce the thickness of a first sub-part to be formed in the second inter-sub-layer insulating film, so as to obtain a second inter-sub-layer insulating layer comprising the first sub-part and the second sub-part; wherein a first sub-section of the second inter-sub layer insulation layer corresponds to a first portion of the inter-layer insulation layer and a second sub-section of the second inter-sub layer insulation layer corresponds to a second portion of the inter-layer insulation layer; with respect to the substrate, a surface of a side of the first sub-portion of the second interlayer insulating layer, which is away from the substrate, is lower than a surface of a side of the second sub-portion of the second interlayer insulating layer, which is away from the substrate.

13. A display device comprising the display substrate according to any one of claims 1 to 10.