CN113097233B

CN113097233B - Display substrate, preparation method thereof and display device

Info

Publication number: CN113097233B
Application number: CN202110356602.0A
Authority: CN
Inventors: 李栋; 张慧娟
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2021-04-01
Filing date: 2021-04-01
Publication date: 2024-05-14
Anticipated expiration: 2041-04-01
Also published as: CN113097233A

Abstract

The embodiment of the invention discloses a display substrate, a preparation method thereof and a display device, relates to the technical field of display, and is used for improving extrusion resistance of the display substrate. The display substrate includes: a substrate and at least one transistor disposed on one side of the substrate. The transistor includes: the active layer, the first gate insulating layer, the first gate electrode, the interlayer insulating layer, the source/drain electrode layer and the planarization layer are sequentially stacked. The source-drain electrode layer includes a source electrode and a drain electrode. Wherein the interlayer insulating layer includes a first portion and a second portion. The orthographic projection of the first portion of the interlayer insulating layer on the substrate and the orthographic projection of the first gate on the substrate are at least partially overlapped. The first portion of the interlayer insulating layer is located away from the surface of the substrate side and is lower than the second portion of the interlayer insulating layer is located away from the surface of the substrate side. The display substrate, the preparation method thereof and the display device are used for displaying images.

Description

Display substrate, preparation method thereof and display device

Technical Field

The invention relates to the technical field of display, in particular to a display substrate, a preparation method thereof and a display device.

Background

Organic LIGHT EMITTING Diode (OLED) has been widely used in the display field because of its advantages of self-luminescence, low driving voltage, high luminous efficiency, fast response speed, flexible display, and the like.

With the development of display technology, LTPS (Low Temperature Poly-silicon) back plate technology has been receiving increasing attention because of its high mobility, high aperture ratio, capability of implementing GOA (GATE DRIVE on Array, gate integration driving), and other reasons, so that a display panel based on the LTPS (Low Temperature Poly-silicon) back plate technology has a better display effect than a display panel based on a-Si (amorphous silicon) technology.

In the prior art, display devices manufactured by the LTPS backboard technology have the problem that due to the self structure of the LTPS backboard, display defects such as bright and dark spots and the like caused by unstable transistors are easy to occur when the display devices are longitudinally extruded.

Disclosure of Invention

The embodiment of the invention aims to provide a display substrate, a preparation method thereof and a display device, which are used for improving extrusion resistance of the display substrate.

In order to achieve the above purpose, the embodiment of the invention provides the following technical scheme:

In one aspect, an embodiment of the present invention provides a display substrate, including a substrate and at least one transistor disposed on one side of the substrate. The transistor includes: the active layer, the first gate insulating layer, the first gate electrode, the interlayer insulating layer, the source/drain electrode layer and the planarization layer are sequentially stacked. The source-drain electrode layer includes a source electrode and a drain electrode. Wherein the interlayer insulating layer includes a first portion and a second portion. The orthographic projection of the first portion of the interlayer insulating layer on the substrate and the orthographic projection of the first gate on the substrate are at least partially overlapped. The first portion of the interlayer insulating layer is located away from the surface of the substrate side and is lower than the second portion of the interlayer insulating layer is located away from the surface of the substrate side.

According to the display substrate provided by some embodiments of the present disclosure, the first portion of the interlayer insulating layer corresponding to the first gate and the second portion of the interlayer insulating layer are disposed, so that the first portion of the interlayer insulating layer is far away from the surface of the substrate, and is lower than the surface of the second portion of the interlayer insulating layer far away from the substrate, with respect to the substrate, the first portion of the interlayer insulating layer is in a concave state with respect to the second portion of the interlayer insulating layer, and further, the thickness of the portion of the flat layer corresponding to the first portion of the interlayer insulating layer is greater than the thickness of the portion of the flat layer corresponding to the second portion of the interlayer insulating layer.

When the display substrate receives longitudinal extrusion stress, the extrusion stress transmitted to the interlayer insulating layer is larger at the position with smaller thickness of the flat layer, and after the longitudinal extrusion stress is transmitted to the interlayer insulating layer through the flat layer, the received pressure of the first part of the interlayer insulating layer is smaller than the received pressure of the second part of the interlayer insulating layer, so that the received pressure of the first grid electrode and the channel part of the active layer can be reduced, the whole received pressure of the transistor can be relieved, the stability of the transistor is ensured, the extrusion resistance of the display substrate is improved, the display defect problem such as bright and dark points of the display substrate can be avoided, and the product yield is improved.

In some embodiments, a distance between a surface of the first portion of the interlayer insulating layer remote from the substrate side and a surface of the second portion of the interlayer insulating layer remote from the substrate side is greater than 0nm and less than or equal to 200nm.

In some embodiments, an orthographic projection of the first gate on the substrate is within an orthographic projection of the first portion of the interlayer insulating layer on the substrate.

In some embodiments, the orthographic projections of the source and drain electrodes on the substrate do not overlap with orthographic projections of the first portion of the interlayer insulating layer on the substrate.

In some embodiments, the transistor further includes a second gate electrode disposed between the active layer and the first gate insulating layer. The orthographic projection of the second grid electrode on the substrate is positioned in the orthographic projection range of the first part of the interlayer insulating layer on the substrate.

In some embodiments, the display substrate further comprises: and the pixel defining layer and the plurality of spacers are arranged on one side of the flat layer away from the substrate and are sequentially laminated. The orthographic projection of the plurality of spacers on the substrate is not overlapped with the orthographic projection of the first part of the interlayer insulating layer on the substrate.

In some embodiments, the second portion of the interlayer insulating layer has a thickness in the range of 500nm to 1500nm.

In some embodiments, the interlayer insulating layer includes: the first sub interlayer insulating layer and the second sub interlayer insulating layer are laminated in this order. Wherein, relative to the substrate, a first sub-part corresponding to a first part of the interlayer insulating layer in the second sub-interlayer insulating layer is far away from the surface of one side of the substrate and is lower than a second sub-part corresponding to a second part of the interlayer insulating layer in the second sub-interlayer insulating layer is far away from the surface of one side of the substrate.

In some embodiments, the material of the interlayer insulating layer includes an inorganic insulating material. The material of the planarization layer includes an organic insulating material.

In some embodiments, the number of the transistors is a plurality, and the plurality of the transistors includes at least one of a driving transistor, a compensation transistor, and a reset transistor.

On the other hand, the embodiment of the invention provides a preparation method of the display substrate. The display substrate comprises at least one transistor, and the preparation method comprises the following steps: providing a substrate; an active layer, a gate insulating film, a first gate electrode, and an interlayer insulating film are sequentially formed on the substrate. And in the one-time patterning process, patterning the interlayer insulating film and the gate insulating film to obtain a first gate insulating layer and an interlayer insulating layer. Wherein the interlayer insulating layer includes a first portion and a second portion. The orthographic projection of the first part of the interlayer insulating layer on the substrate and the orthographic projection of the first grid electrode on the substrate are at least partially overlapped; the first portion of the interlayer insulating layer is located away from the surface of the substrate side and is lower than the second portion of the interlayer insulating layer is located away from the surface of the substrate side. And sequentially forming a source-drain electrode layer and a flat layer on one side of the interlayer insulating layer, which is far away from the substrate. The source-drain electrode layer includes a source electrode and a drain electrode. In the one-time patterning process, patterning the interlayer insulating film to obtain an interlayer insulating layer, including: forming a photoresist layer on a surface of the interlayer insulating film on a side remote from the substrate; exposing and developing the photoresist layer through a gray-scale mask plate to form a patterned photoresist layer; the patterned photoresist layer is provided with a full reserved area and a partial reserved area; the completely reserved area of the patterned photoresist layer corresponds to a second part to be formed in the interlayer insulating film, and the partially reserved area of the patterned photoresist layer corresponds to a first part to be formed in the interlayer insulating film; and etching the interlayer insulating film by taking the patterned photoresist layer as a mask, so that the thickness of a first part to be formed in the interlayer insulating film is reduced, and the interlayer insulating layer comprising the first part and the second part is obtained.

The beneficial effects of the preparation method of the display substrate provided by the embodiment of the invention are the same as those of the display substrate in some embodiments, and are not described herein again.

In some embodiments, forming an interlayer insulating film includes: and sequentially forming a first sub-interlayer insulating layer and a second sub-interlayer insulating film on one side of the first grid electrode far away from the substrate to obtain the interlayer insulating film. In a one-time patterning process, performing patterning treatment on the interlayer insulating film to obtain an interlayer insulating layer, including: forming a photoresist layer on a surface of the second interlayer insulating film on a side remote from the substrate; exposing and developing the photoresist layer through a gray-scale mask plate to form a patterned photoresist layer; the patterned photoresist layer is provided with a full reserved area and a partial reserved area; the full reserved area of the patterned photoresist layer corresponds to a second sub-part to be formed in the second sub-interlayer insulating film, and the partial reserved area of the patterned photoresist layer corresponds to a first sub-part to be formed in the second sub-interlayer insulating film; etching the second sub-interlayer insulating film by taking the patterned photoresist layer as a mask, so that the thickness of a first sub-part to be formed in the second sub-interlayer insulating film is reduced, and a second sub-interlayer insulating layer comprising the first sub-part and the second sub-part is obtained; wherein a first sub-portion of the second sub-interlayer insulating layer corresponds to a first portion of the interlayer insulating layer, and a second sub-portion of the second sub-interlayer insulating layer corresponds to a second portion of the interlayer insulating layer; the first sub-portion of the second sub-interlayer insulating layer is lower than the surface of the second sub-interlayer insulating layer on the side away from the substrate with respect to the substrate.

In still another aspect, an embodiment of the present invention provides a display device, including the display substrate described in any one of the foregoing embodiments.

The display substrate included in the display device has the same structure and beneficial technical effects as those of the display substrate provided in some embodiments described above, and will not be described in detail herein.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings that need to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic illustrations, and are not limiting of the actual size of the products, the actual flow of the methods, etc. according to the embodiments of the present disclosure.

Fig. 1 is a structural view of a display substrate according to the related art;

FIG. 2 is a block diagram of a display substrate according to some embodiments of the invention;

FIG. 3 is a force analysis diagram of a display substrate according to some embodiments of the invention;

FIG. 4 is a block diagram of another display substrate according to some embodiments of the invention;

FIG. 5 is a block diagram of a further display substrate according to some embodiments of the invention;

FIG. 6 is a block diagram of a display substrate according to yet another embodiment of the invention;

FIG. 7 is a block diagram of a display substrate according to yet another embodiment of the invention;

FIG. 8 is a block diagram of a pixel drive circuit according to some embodiments of the invention;

FIG. 9 is a flow chart of a method of fabricating a display substrate according to some embodiments of the invention;

FIG. 10 is a flowchart of one of S300 in the flowchart of FIG. 9;

FIG. 11 is a flowchart of another S300 of the flowchart shown in FIG. 9;

FIGS. 12 a-12 e are flow charts illustrating the fabrication of a display substrate according to some embodiments of the invention;

fig. 13 is a block diagram of a display device according to some embodiments of the invention.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "examples," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

At least one of "A, B and C" has the same meaning as at least one of "A, B or C" and includes the following combinations of A, B and C: a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

As shown in fig. 1, the display substrate in the related art generally includes: a substrate 1' and a transistor 2' provided on one side of the substrate 1 '. The transistor 2' includes an active layer 21', a gate insulating layer 22', a gate electrode 23', an interlayer insulating layer 24', a source electrode, and a drain electrode, which are stacked in this order.

In the display substrate, the thickness of the interlayer insulating layer 24' is relatively uniform. Due to the presence of the gate electrode 23', the portion of the interlayer insulating layer 24' opposite to the gate electrode 23' is protruded.

Thus, when the display substrate is longitudinally pressed, the pressure f1 'applied to the convex portion of the interlayer insulating layer 24' is greater than the pressure f2 'applied to the other portion of the interlayer insulating layer 24'. Since the raised portion of the interlayer insulating layer 24' is opposite to the gate electrode 23' and the channel portion of the active layer 21', the gate electrode 23' and the channel portion of the active layer 21' are subjected to a large pressure, and thus the performance of the transistor is unstable, and display defects such as bright and dark spots are easily caused in the display substrate.

Based on this, an embodiment of the present invention provides a display substrate 100.

In some examples, as shown in fig. 2-8, the display substrate 100 includes a substrate 1.

The structure of the substrate 1 includes various types, and can be selected and set according to actual needs. For example, the substrate 1 is a blank substrate board. As another example, the substrate 1 includes a blank substrate base plate and a functional thin film (for example, may include a buffer layer) provided on the blank substrate base plate.

The types of the blank substrate include various types, and the blank substrate can be specifically selected and set according to actual needs.

For example, the blank substrate may be a rigid substrate. The rigid substrate may be, for example, a glass substrate or a PMMA (Polymethyl methacrylate ) substrate. In this case, the display substrate 100 may be a rigid display substrate.

As another example, the blank substrate may be a flexible substrate. The flexible substrate may be, for example, a PET (Polyethylene terephthalate ) substrate, a PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) substrate, or a PI (Polyimide) substrate. In this case, the display substrate 100 may be a flexible display substrate.

In some examples, as shown in fig. 2-7, the display substrate 100 further includes at least one transistor 2 disposed on one side of the substrate 1. Each transistor 2 may include an active layer 21, a first gate insulating layer 22, a first gate electrode 23, an interlayer insulating layer 24, a source-drain electrode layer 25, and a planarization layer 26, which are stacked in this order. The source/drain electrode layer 25 includes a source electrode 251 and a drain electrode 252.

Illustratively, the material of the active layer 21 may be LTPS or metal oxide, etc. The metal oxide may be IGZO (Indium Gallium Zinc Oxide ).

Illustratively, the material of the first gate insulating layer 22 is an inorganic material. For example, the inorganic material may be at least one of silicon nitride and silicon oxide. Wherein the thickness of the first gate insulating layer 22 is relatively uniform.

Illustratively, the material of the interlayer insulating layer 24 is an inorganic material. For example, the inorganic material may be at least one of silicon nitride and silicon oxide.

In some examples, as shown in fig. 2, the interlayer insulating layer 24 includes a first portion and a second portion. Wherein a first portion of the interlayer insulating layer 24 may be located at the thinned region C1 and a second portion of the interlayer insulating layer 24 may be located at the non-thinned region C2.

As illustrated in fig. 2 and 4, in the cross-sectional view of the transistor 2, the boundary between the thinned region C1 and the non-thinned region C2 is located at a position where the thickness of the interlayer insulating layer 24 just changes in a direction parallel to the substrate 1 and directed toward the first gate electrode 23 by the source electrode 251 or toward the first gate electrode 23 by the drain electrode 252. Here, in the cross-sectional view of the transistor, the non-thinned region C2 may be regarded as including two portions, one of which is located between the source 251 and the thinned region C1 and the other of which is located between the drain 252 and the thinned region C1.

Illustratively, as shown in fig. 3, with respect to the substrate 1, a first portion of the interlayer insulating layer 24 is lower than a surface of the interlayer insulating layer 24 on a side away from the substrate 1. That is, the distance H1 between the surface of the first portion of the interlayer insulating layer 24 on the side away from the substrate 1 and the substrate 1 is smaller than the distance H2 between the surface of the second portion of the interlayer insulating layer 24 on the side away from the substrate 1 and the substrate 1. "pitch" refers to the distance between two surfaces in a direction perpendicular to the substrate 1.

This makes it possible to reduce the pitch between the side surface of the first portion of the interlayer insulating layer 24 remote from the substrate 1 and to make the first portion of the interlayer insulating layer 24 in a recessed state compared to the second portion of the interlayer insulating layer 24.

Note that, in consideration of a process for preparing the interlayer insulating layer 24, a surface of the first portion of the interlayer insulating layer 24 on the side away from the substrate 1 may include two-part surfaces. Wherein a part of the surface may be parallel to the substrate 1 and another part of the surface may be at an angle to the substrate 1 and used for connecting the part of the surface parallel to the substrate 1 and the surface of the second part of the interlayer insulating layer 24 on the side away from the substrate 1.

The "surface of the first portion of the interlayer insulating layer 24 on the side away from the substrate 1" referred to herein means a portion of the surface parallel to the substrate 1. Wherein the "parallel" is not strictly parallel, and the partial surface and the substrate 1 may have a deviation of, for example, ±5° (or other degrees) due to a process error, which may also be considered parallel.

Illustratively, the orthographic projection of the first portion of the interlayer insulating layer 24 onto the substrate 1 and the orthographic projection of the first gate electrode 23 onto the substrate 1 at least partially overlap. That is, the position of the first portion of the interlayer insulating layer 24 corresponds to the position of the first gate electrode 23.

For example, the orthographic projection of the first portion of the interlayer insulating layer 24 on the substrate 1 and the orthographic projection of the first gate electrode 23 on the substrate 1 partially overlap.

As another example, as shown in fig. 4, the orthographic projection of the first portion of the interlayer insulating layer 24 on the substrate 1 and the orthographic projection of the first gate electrode 23 on the substrate 1 overlap. At this time, the orthographic projection area of the first portion of the interlayer insulating layer 24 on the substrate 1 and the orthographic projection area of the first gate electrode 23 on the substrate 1 are equal, and the orthographic projection shape of the first portion of the interlayer insulating layer 24 on the substrate 1 and the orthographic projection shape of the first gate electrode 23 on the substrate 1 are the same.

As another example, as shown in fig. 2 and 6, the orthographic projection of the first gate electrode 23 on the substrate 1 is located within the orthographic projection range of the first portion of the interlayer insulating layer 24 on the substrate 1. At this time, the orthographic projection area of the first gate electrode 23 on the substrate 1 is smaller than the orthographic projection area of the first portion of the interlayer insulating layer 24 on the substrate 1.

The material of the planarization layer 26 is an organic material, and may be any one of an organic resin and polyimide, for example.

For example, as shown in fig. 3, the side surface of the planarization layer 26 remote from the substrate 1 is a relatively flat surface.

Since the distance H1 between the surface of the first portion of the interlayer insulating layer 24 on the side away from the substrate 1 and the substrate 1 is smaller than the distance H2 between the surface of the second portion of the interlayer insulating layer on the side away from the substrate 1 and the substrate 1, after the flat layer 26 is formed on the side of the interlayer insulating layer 24 on the side away from the substrate 1, the thickness H3 of the portion of the flat layer 26 corresponding to the first portion of the interlayer insulating layer 24 can be made larger than the thickness H4 of the portion of the flat layer 26 corresponding to the second portion of the interlayer insulating layer 24.

The young's modulus E1 of the inorganic material is much larger than the young's modulus E2 of the organic material.

When the display substrate 100 in the present embodiment is subjected to longitudinal extrusion (at least having a force in a direction perpendicular to the substrate 1), since the material of the interlayer insulating layer 24 is an inorganic material and the material of the flat layer 26 is an organic material, the interlayer insulating layer 24 is hardly deformed or deformed little, and the thickness variation at different positions of the flat layer 26 is negligible, for example, relatively uniform.

Illustratively, the display substrate 100 is subjected to a longitudinal pressing force F, which is transmitted to the interlayer insulating layer 24 through the flat layer 26, and the distribution and magnitude of the pressing force transmitted to the interlayer insulating layer 24 through the different thickness positions of the flat layer 26 are different. From force transmission and distribution rules and formulas(Where f is the pressure transmitted to the interlayer insulating layer 24, E is the young's modulus of the flat layer 26, Δh is the thickness variation of the flat layer 26 after being pressed, and H is the thickness of the flat layer 26), it is known that since E and Δh are constant values, the pressure transmitted to the interlayer insulating layer 24 is greater at a position where the thickness of the flat layer 26 is smaller.

Since the thickness H3 of the portion of the planarization layer 26 corresponding to the first portion of the interlayer insulating layer 24 is increased, and the thickness H3 of the portion of the planarization layer 26 corresponding to the first portion of the interlayer insulating layer 24 is greater than the thickness H4 of the portion of the planarization layer 26 corresponding to the second portion of the interlayer insulating layer 24, the pressure transmitted to the first portion of the interlayer insulating layer 24 through the planarization layer 26 is smaller than the pressure transmitted to the second portion of the interlayer insulating layer 24 through the planarization layer 26, that is, the longitudinal compressive stress F is mainly borne by the second portion of the interlayer insulating layer 24, thus reducing the pressure applied to the channel portions of the first gate electrode 23 and the active layer 21.

Thus, in the display substrate 100 provided in some embodiments of the present disclosure, by disposing the first portion of the interlayer insulating layer 24 corresponding to the first gate electrode 23 and the second portion of the interlayer insulating layer 24 such that the first portion of the interlayer insulating layer 24 is far away from the surface on the substrate 1 side, the first portion of the interlayer insulating layer 24 is recessed with respect to the second portion of the interlayer insulating layer 24 with respect to the surface on the substrate 1 side where the second portion of the interlayer insulating layer 24 is lower than the substrate 1 side, and thus the thickness H3 of the portion of the flat layer 26 corresponding to the first portion of the interlayer insulating layer 24 is greater than the thickness H4 of the portion of the flat layer 26 corresponding to the second portion of the interlayer insulating layer 24.

In this way, when the display substrate 100 receives the longitudinal compressive stress F, the compressive stress transmitted to the interlayer insulating layer 24 is greater at the position where the thickness of the flat layer 26 is smaller, and after the longitudinal compressive stress F is transmitted to the interlayer insulating layer 24 through the flat layer 26, the pressure received by the first portion of the interlayer insulating layer 24 is smaller than the pressure received by the second portion of the interlayer insulating layer 24, so that the pressure received by the first gate 23 and the channel portion of the active layer 21 can be reduced, the pressure received by the whole transistor 2 can be relieved, the stability of the transistor 2 can be ensured, the compressive resistance of the display substrate 100 can be improved, the display defect problem such as bright and dark spots of the display substrate 100 can be avoided, and the product yield can be improved.

In some embodiments, as shown in fig. 3, a distance Δh between a surface of the first portion of the interlayer insulating layer 24 on a side away from the substrate 1 and a surface of the second portion of the interlayer insulating layer 24 on a side away from the substrate 1 is greater than 0nm and less than or equal to 200nm.

Illustratively, Δh may be 1nm, 50nm, 100nm, 150nm, 200nm, or the like.

By setting Δh to the above range, it is possible to ensure that the first portion of the interlayer insulating layer 24 still has a good insulating property or crosstalk preventing capability while ensuring that the display substrate 100 in the present embodiment has the beneficial effects in the above embodiments, and to prevent the wiring on the side of the interlayer insulating layer 24 away from the substrate 1 from interfering with the first gate electrode 23, which affects the operation performance of the transistor 2.

In some embodiments, as shown in fig. 3, the thickness H5 of the second portion of the interlayer insulating layer 24 ranges from 500nm to 1500nm.

By way of example, H5 may be 500nm, 1000nm or 1500nm, etc.

By making the second portion of the interlayer insulating layer 24 have a larger thickness, the first portion of the interlayer insulating layer 24 can be made to have a larger thickness at the same time as the thickness of the first portion of the interlayer insulating layer 24 is smaller than the thickness of the second portion of the interlayer insulating layer 24. This is advantageous in ensuring that the first portion of the interlayer insulating layer 24 has good crosstalk prevention capability.

The interlayer insulating layer 24 may have a single-layer structure or a multilayer structure, and may be provided as desired.

In the case where the interlayer insulating layer 24 has a single-layer structure, the manner in which the interlayer insulating layer 24 is disposed may be referred to the description in some of the above examples, and will not be described here again.

In the case where the interlayer insulating layer 24 is a multilayer structure, a structure in which the interlayer insulating layer 24 is a two-layer structure will be described as an example.

In some embodiments, as shown in fig. 5, the interlayer insulating layer 24 includes: the first sub interlayer insulating layer 241 and the second sub interlayer insulating layer 242 are sequentially stacked. Wherein, with respect to the substrate 1, a surface of the second sub-interlayer insulating layer 242 on a side away from the substrate 1, which corresponds to the first portion of the interlayer insulating layer 24, is lower than a surface of the second sub-interlayer insulating layer 242 on a side away from the substrate 1, which corresponds to the second portion of the interlayer insulating layer 24.

In this example, the second interlayer insulating layer 242 may be disposed in a manner that is described above with reference to the interlayer insulating layer 24 in some examples, and will not be described here again.

The relationship between the third sub-portion of the first sub-interlayer insulating layer 241 corresponding to the first portion of the interlayer insulating layer 24 and the fourth sub-portion of the first sub-interlayer insulating layer 241 corresponding to the second portion of the interlayer insulating layer 24 is not limited, and may be selected according to actual needs.

For example, as shown in fig. 5, the thickness of the third sub-portion of the first sub-interlayer insulating layer 241 corresponding to the first portion of the interlayer insulating layer 24 is equal to the thickness of the fourth sub-portion of the first sub-interlayer insulating layer 241 corresponding to the second portion of the interlayer insulating layer 24.

At this time, the thickness of the first sub-portion of the second sub-interlayer insulating layer 242 corresponding to the first portion of the interlayer insulating layer 24 may be greater than 0, or equal to 0.

As another example, the thickness of the third sub-portion of the first sub-interlayer insulating layer 241 corresponding to the first portion of the interlayer insulating layer 24 is smaller than the thickness of the fourth sub-portion of the first sub-interlayer insulating layer 241 corresponding to the second portion of the interlayer insulating layer 24.

At this time, the thickness of the portion of the second sub-interlayer insulating layer 242 corresponding to the first portion of the interlayer insulating layer 24 is 0, and the third sub-portion of the first sub-interlayer insulating layer 241 corresponding to the first portion of the interlayer insulating layer 24 is exposed.

By providing the interlayer insulating layer 24 in a multi-layered stacked structure, the thickness adjustment range of the portion of the interlayer insulating layer 24 located in the thinned region C1 can be increased by using a plurality of sub-interlayer insulating layers in the interlayer insulating layer 24.

In some embodiments, as shown in fig. 2-7, the orthographic projections of the source 251 and drain 252 on the substrate 1 do not overlap with the orthographic projections of the first portion of the interlayer insulating layer 24 on the substrate 1.

This can avoid the source electrode 251 and the drain electrode 252 covering the first portion of the interlayer insulating layer 24, resulting in a protrusion formed on a surface of the first portion of the interlayer insulating layer 24 away from the substrate 1, thereby avoiding an increase in compressive stress borne by the first portion of the interlayer insulating layer 24 when the display substrate 100 is longitudinally compressed, and increasing the risk of display defects of the display substrate 100.

The structure of the transistor 2 includes a plurality of types, and in the case where the display substrate 100 includes a plurality of transistors 2, the plurality of transistors 2 may have the same structure or may have different structures.

The transistor 2 may be a single gate transistor or a double gate transistor, for example.

In some embodiments, as shown in fig. 6, in the case where the transistor 2 is a double gate transistor, the transistor 2 further includes a second gate 27 disposed between the active layer 21 and the first gate insulating layer 22. The orthographic projection of the second gate electrode 27 on the substrate 1 is located within the orthographic projection range of the first portion of the interlayer insulating layer 24 on the substrate 1.

Illustratively, the orthographic projection of the second gate 27 on the substrate 1 overlaps with the orthographic projection of the first portion of the interlayer insulating layer 24 on the substrate 1. Or as shown in fig. 6, the orthographic projection area of the second gate electrode 27 on the substrate 1 is smaller than the orthographic projection area of the first portion of the interlayer insulating layer 24 on the substrate 1.

In the case where the transistor 2 further includes the second gate electrode 27, the transistor 2 further includes the second gate insulating layer 28 between the active layer 21 and the second gate electrode 27. The material of the second gate insulating layer 28 is an inorganic material. For example, the inorganic material may be at least one of silicon nitride and silicon oxide. Wherein the thickness of the second gate insulating layer 28 is relatively uniform.

If the thickness of the first portion of the interlayer insulating layer 24 is equal to the thickness of the second portion of the interlayer insulating layer 24, the difference between the spacing between the substrate 1 and the side surface of the interlayer insulating layer 24 remote from the substrate 1 and the spacing between the substrate 1 and the side surface of the second portion of the interlayer insulating layer 24 remote from the substrate 1 is larger in the case where the second gate electrode 27 is provided than in the case where only the first gate electrode 23 is provided. Accordingly, when the display substrate 100 receives a longitudinal pressing force, the first gate electrode 23, the second gate electrode 27, and the channel portion of the active layer 21 receive a greater pressing force.

According to the embodiment of the invention, the distance between the first part of the interlayer insulating layer 24, which is far away from the side surface of the substrate 1, and the substrate 1 is smaller than the distance between the second part of the interlayer insulating layer 24, which is far away from the side surface of the substrate 1, and the substrate 1, so that when the display substrate 100 is subjected to longitudinal extrusion force, the pressure applied to the first grid electrode 23, the second grid electrode 27 and the channel part of the active layer 21 can be effectively reduced, the stability of the transistor 2 is ensured, the extrusion resistance of the display substrate 100 is improved, the display defect problem of the display substrate 100 is avoided, and the product yield is improved.

It should be noted that, in the embodiment of the present invention, the relationship between the orthographic projection of the first gate electrode 23 on the substrate 1 and the orthographic projection of the second gate electrode 27 on the substrate 1 is not limited as long as the orthographic projections of the first gate electrode 23 and the second gate electrode 27 on the substrate 1 are both within the range of the orthographic projection of the first portion of the interlayer insulating layer 24 on the substrate 1. For example, the front projection of the first gate 23 on the substrate 1 is within the front projection range of the second gate 27 on the substrate 1, or the front projection of the second gate 27 on the substrate 1 is within the front projection range of the first gate 23 on the substrate 1.

In some embodiments, the display substrate 100 may further include a light emitting device disposed on a side of the pixel defining layer remote from the substrate 1.

The types of the above-mentioned light emitting devices include various ones, and can be selected and set according to actual needs.

For example, the light emitting device may be an OLED, a QLED (Quantum Dot LIGHT EMITTING Diodes), an LED (LIGHT EMITTING Diodes), or the like.

The present example is schematically illustrated with the above-described light emitting device being an OLED as an example.

In some examples, as shown in fig. 7, the display substrate 100 further includes: a pixel defining layer 3 and a plurality of spacers 4 which are provided on a side of the planarization layer 26 away from the substrate 1 and are stacked in this order. The orthographic projection of the plurality of spacers 4 on the substrate 1 does not overlap with the orthographic projection of the first portion of the interlayer insulating layer 24 on the substrate 1.

In some examples, the above-described pixel defining layer 3 has an opening. The light emitting device may include at least an anode, a light emitting layer, and a cathode, which are sequentially stacked. The anode may be disposed between the pixel defining layer 3 and the planarization layer 26, and at least a portion of the light emitting layer may be located within an opening of the pixel defining layer 3.

For example, the embodiment of the invention can form the light-emitting layer by adopting an evaporation process. Based on this, the spacer 4 can be used to support the FMM (FINE METAL MASK ) used in the vapor deposition process.

When the display substrate 100 is longitudinally pressed, the spacers 4 are subjected to a large pressure. By making the orthographic projection of the spacer 4 on the substrate 1 and the orthographic projection of the first portion of the interlayer insulating layer 24 on the substrate 1 non-overlap, a larger distance between the first portion of the interlayer insulating layer 24 and the spacer 4 in a direction parallel to the substrate 1 can be provided, which is beneficial to reducing the pressure transferred to the first portion of the interlayer insulating layer 24, the gate electrode and the channel portion of the active layer 21, and reducing the risk of occurrence of display failure of the display substrate 100.

In some embodiments, the display substrate 100 further includes: a plurality of pixel driving circuits P provided on the substrate 1 side.

The structure of the pixel driving circuit P may include various types, and may be selected according to actual needs. For example, the structure of the pixel driving circuit P may include a structure of "2T1C", "6T1C", "7T1C", "6T2C", or "7T2C", or the like. Here, "T" denotes a thin film transistor, a number located before "T" denotes the number of thin film transistors, "C" denotes a storage capacitor, and a number located before "C" denotes the number of storage capacitors.

Note that the pixel driving circuit P may include a driving transistor T1. Of course, the pixel driving circuit P may further include a compensation transistor T2 and/or a reset transistor T3.

In some embodiments, the display substrate 100 includes a plurality of transistors 2. The plurality of transistors 2 includes at least one of a driving transistor T1, a compensation transistor T2, and a reset transistor T3.

The plurality of transistors 2 may belong to at least one pixel driving circuit P, for example. For example, in the case where the plurality of transistors 2 includes the driving transistor T1, the compensation transistor T2, and the reset transistor T3, the driving transistor T1, the compensation transistor T2, and the reset transistor T3 may belong to the same pixel driving circuit P or may belong to different pixel driving circuits P.

As shown in fig. 8, the following description will take an example in which the configuration of the pixel driving circuit P is 7T 1C. The transistor 2 may include a driving transistor T1, a compensation transistor T2, and a reset transistor T3.

By adopting the above arrangement of the interlayer insulating layer 24 in the driving transistor T1, it is possible to avoid affecting the transmission of the driving current and thus the light emitting state of the light emitting device. By adopting the above arrangement of the interlayer insulating layer 24 in the compensation transistor T2, it is possible to avoid influencing the transmission of the data signal during the process of writing the data signal into the gate of the driving transistor T1 through the compensation transistor T2, and further avoid influencing the compensation of the threshold voltage of the driving transistor T1. By adopting the above arrangement mode for the interlayer insulating layer 24 in the reset transistor T3, the influence on the transmission of the reset signal can be avoided, and the reset effect on the gate of the drive transistor T1 can be ensured, and the signal residue displayed in the previous frame can be avoided.

In another aspect, an embodiment of the present invention provides a method for manufacturing a display substrate. Wherein the display substrate 100 comprises at least one transistor 2. Based on this, as shown in fig. 9, the manufacturing method of the display substrate includes: s100 to S400.

S100, providing a substrate 1.

Alternatively, the structure of the substrate 1 may refer to the descriptions in some embodiments, and will not be repeated here.

S200, as shown in fig. 12a, an active layer 21, a first gate insulating film 22a, a first gate electrode 23, and an interlayer insulating film 24a are sequentially formed on a substrate 1.

For example, in forming the active layer 21, the active film may be formed using a deposition process, and then patterned using a photolithography process, for example, to form the active layer 21.

For example, in forming the first gate insulating film 22a, it may be formed by, for example, a PECVD (PLASMA ENHANCED CHEMICAL Vapor Deposition) process or a CVD (Chemical Vapor Deposition) process.

For example, in the process of forming the first gate electrode 23, a deposition process may be used to form a gate conductive film, and then a photolithography process may be used to pattern the gate conductive film to form the first gate electrode 23.

For example, in forming the interlayer insulating film 24a, it may be formed by, for example, a PECVD process, a CVD process, or the like.

S300, as shown in fig. 12b and 12c, in the one patterning process, the interlayer insulating film 24a and the first gate insulating film 22a are subjected to patterning processing, to obtain the first gate insulating layer 22 and the interlayer insulating layer 24. Wherein the interlayer insulating layer 24 includes a first portion and a second portion. The orthographic projection of the first portion of the interlayer insulating layer 24 on the substrate 1 and the orthographic projection of the first gate electrode 23 on the substrate 1 overlap at least partially. The first portion of the interlayer insulating layer 24 is located away from the surface of the substrate 1 side with respect to the substrate 1, and is lower than the second portion of the interlayer insulating layer 24 is located away from the surface of the substrate 1 side.

In some embodiments, as shown in fig. 10, in the above-described S300, the interlayer insulating film 24a is subjected to patterning processing in one patterning process, resulting in the interlayer insulating layer 24, including S310a to S330a.

S310a, a photoresist layer is formed on a side surface of the interlayer insulating film 24a remote from the substrate 1.

The photoresist layer described above may be formed, for example, using a coating process.

The photoresist layer comprises a plurality of materials, and can be selected and arranged according to actual needs. For example, the material of the photoresist layer may be a positive photoresist, or the material of the photoresist layer may be a negative photoresist. In the embodiment of the invention, the positive photoresist is taken as an example of the photoresist layer material, and schematic description is made.

And S320a, exposing and developing the photoresist layer through a gray-scale mask plate to form a patterned photoresist layer.

The gray-scale mask plate comprises a plurality of types, and can be selected and set according to actual needs. For example, the gray tone mask may be a halftone mask or a gray tone mask. The embodiment of the invention takes a half-tone mask plate as an example for schematic description.

The photoresist layer is exposed and developed through the halftone mask plate, and the patterned photoresist layer can be formed. The patterned photoresist layer has a fully reserved region and a partially reserved region.

Wherein, the fully reserved area of the patterned photoresist layer means that the photoresist in the area is not removed and still covers the surface of the interlayer insulating film 24a corresponding to the fully reserved area. The partially remaining region in the patterned photoresist layer means that the photoresist in the region is partially removed in the thickness direction, i.e., the planar area of the photoresist in the region is unchanged, the thickness is reduced, and the photoresist layer in the region is still covered on the region surface of the interlayer insulating film 24a corresponding to the partially remaining region.

Different regions of the patterned photoresist layer correspond to different regions in the interlayer insulating film 24a, that is, a fully reserved region of the patterned photoresist layer corresponds to a second portion to be formed in the interlayer insulating film 24a, and a partially reserved region of the patterned photoresist layer corresponds to a first portion to be formed in the interlayer insulating film 24 a.

The source 251 and the drain 252 in the transistor 2 are electrically connected to the active layer 21 through the first via G1 and the second via G2, respectively. The first and second vias G1 and G2 each penetrate through the first gate insulating layer 22 and the interlayer insulating layer 24.

Based on this, the patterned photoresist layer also includes a complete removal region. The complete removal region means that the photoresist in the region is completely removed, exposing a portion of the side surface of the interlayer insulating film 24a facing away from the substrate 1.

And completely removing the region corresponding to the first via hole and the second via hole to be formed.

As shown in fig. 12b and 12c, the interlayer insulating film 24a is etched with the patterned photoresist layer as a mask, so that the thickness of the first portion to be formed in the interlayer insulating film 24a is reduced, and the interlayer insulating layer 24 including the first portion and the second portion is obtained.

Illustratively, etching the interlayer insulating film 24a with the patterned photoresist layer as a mask includes, for example: the interlayer insulating film 24a is etched for the first time using the patterned photoresist layer as a mask, so that regions of the interlayer insulating film 24a corresponding to the first and second vias to be formed penetrate the interlayer insulating film 24a and the first gate insulating film 22a, thereby forming first and second vias G2 and G2.

The fully reserved area and the partially reserved area of the patterned photoresist layer protect the first portion to be formed and the second portion to be formed in the interlayer insulating film 24a, so that only the fully removed area of the interlayer insulating film 24a can be etched to form the first via hole G1 and the second via hole G2 when the interlayer insulating film 24a is etched for the first time. The interlayer insulating film 24a and the first gate insulating film 22a may be etched using a dry etching process or a wet etching process.

Then, the portion of the patterned photoresist layer located in the partially remaining region is removed to perform a second etching of the interlayer insulating film 24a subjected to the first etching, i.e., to etch the first portion to be formed in the interlayer insulating film 24a, so that the thickness of the first portion to be formed in the interlayer insulating film 24a is reduced.

Thereafter, the interlayer insulating layer 24 and the first gate insulating layer 22 can be obtained.

S400, as shown in fig. 12d and 12e, a source/drain electrode layer 25 and a planarization layer 26 are sequentially formed on the interlayer insulating layer 24 on the side away from the substrate 1.

For example, in the process of forming the source/drain electrode layer 25, a deposition process may be used to form a source/drain electrode film, and then a photolithography process may be used to pattern the source/drain electrode film to form the source/drain electrode layer 25. Wherein the source drain electrode layer 25 includes a source electrode 251 and a drain electrode 252.

By way of example, the planar layer 26 described above may be formed using a coating process.

The beneficial technical effects of the method for manufacturing a display substrate provided in the embodiments of the present invention are the same as those that can be achieved by the display substrate 100 provided in some embodiments, and are not described herein.

In some embodiments, as shown in fig. 12a, in S200 described above, forming the interlayer insulating film 24a includes: a first sub interlayer insulating film 241a and a second sub interlayer insulating film 242a are sequentially formed on the side of the first gate electrode 23 away from the substrate 1, to obtain an interlayer insulating film 24a.

The thickness of the interlayer insulating film 24a is 500nm to 1500nm.

The thickness of the interlayer insulating film 24a may be 500nm, 1000nm, or 1500nm, for example.

On the basis of this, as shown in fig. 11, in the above-described S300, the interlayer insulating film 24a is subjected to patterning processing in one patterning process to obtain the interlayer insulating layer 24, and S310b to S320b may be included.

S310b, a photoresist layer is formed on a side surface of the second sub interlayer insulating film 242a remote from the substrate 1.

In this example, the process of forming the photoresist layer on the side surface of the second sub-interlayer insulating film 242a facing away from the substrate 1 is the same as the process of S310a described above, and will not be repeated here.

And S320b, exposing and developing the photoresist layer through the gray-scale mask plate to form a patterned photoresist layer. The patterned photoresist layer has a fully reserved area and a partially reserved area. The full-reserved area of the patterned photoresist layer corresponds to the second sub-portion to be formed in the second sub-interlayer insulating film 242a, and the partial-reserved area of the patterned photoresist layer corresponds to the first sub-portion to be formed in the second sub-interlayer insulating film 242 a.

In this example, the process of exposing and developing the photoresist layer and the structure of the patterned photoresist layer may be described with reference to the above description in S320a, which is not repeated here.

S330b, as shown in fig. 12b and 12c, the second interlayer insulating film 242a is etched with the patterned photoresist layer as a mask, so that the thickness of the first sub-portion to be formed in the second interlayer insulating film 242a is reduced, and the second interlayer insulating layer 242 including the first sub-portion and the second sub-portion is obtained. Wherein a first sub-portion of the second sub-interlayer insulating layer 242 corresponds to a first portion of the interlayer insulating layer 24, and a second sub-portion of the second sub-interlayer insulating layer 242 corresponds to a second portion of the interlayer insulating layer 24. With respect to the substrate 1, the first sub-portion of the second sub-interlayer insulating layer 242 is lower than the surface of the second sub-interlayer insulating layer 242 which is distant from the substrate 1 in order.

Illustratively, the thickness of the third sub-portion in the first sub-interlayer insulating layer 241 is equal to the thickness of the fourth sub-portion in the first sub-interlayer insulating layer 241. Or the thickness of the third sub-portion in the first sub-interlayer insulating layer 241 is smaller than the thickness of the fourth sub-portion in the first sub-interlayer insulating layer 241.

In this example, in the case where the thickness of the third sub-portion in the first sub-interlayer insulating layer 241 is equal to the thickness of the fourth sub-portion in the first sub-interlayer insulating layer 241, the process of etching the second sub-interlayer insulating film 242a may refer to the description in S330a described above, and will not be repeated here.

In the case where the thickness of the third sub-portion in the first sub-interlayer insulating layer 241 is smaller than the thickness of the fourth sub-portion in the first sub-interlayer insulating layer 241, the thickness of the third sub-portion to be formed in the first sub-interlayer insulating film 241a may be simultaneously thinned in S330b described above.

An embodiment of the present invention provides a display device 1000, as shown in fig. 13, where the display device 1000 includes any one of the display substrates 100 described above.

The advantages achieved by the display device 1000 according to some embodiments of the present invention are the same as those achieved by the display substrate 100 according to some embodiments, and are not described herein.

In some embodiments, curved display device 1000 may be any device that displays both motion (e.g., video) and stationary (e.g., still image) and whether text or image. More particularly, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal data assistants (Personal DIGITAL ASSISTANT, PDA for short), hand-held or portable computers, global positioning system (Global Positioning System) receivers/navigators, cameras, moving picture experts group (Moving Picture Experts Group 4, MP 4) video players, video cameras, game consoles, wrist watches, clocks, calculators, television monitors, computer monitors, automotive displays (e.g., odometer display, etc.), navigators, cockpit controls and/or displays, displays of camera views (e.g., display of a rear view camera in a vehicle), electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry), and the like.

The foregoing is merely illustrative of the embodiments of the present invention, and the present invention is not limited thereto, and any person skilled in the art will recognize that changes and substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A display substrate, comprising:

a substrate; and

At least one transistor disposed on one side of the substrate; the transistor includes: an active layer, a first gate insulating layer, a first gate electrode, an interlayer insulating layer, a source drain electrode layer, and a planarization layer which are sequentially stacked; the source-drain electrode layer comprises a source electrode and a drain electrode;

Wherein the interlayer insulating layer includes a first portion and a second portion; the orthographic projection of the first part of the interlayer insulating layer on the substrate and the orthographic projection of the first grid electrode on the substrate are at least partially overlapped;

a first portion of the interlayer insulating layer is lower than a surface of the interlayer insulating layer on a side away from the substrate with respect to the substrate;

Orthographic projections of the source electrode and the drain electrode on the substrate are not overlapped with orthographic projections of the first part of the interlayer insulating layer on the substrate; the orthographic projection of the first grid electrode on the substrate is positioned in the orthographic projection range of the first part of the interlayer insulating layer on the substrate;

the material of the interlayer insulating layer comprises an inorganic insulating material; the material of the flat layer comprises an organic insulating material;

the thickness of the part of the flat layer corresponding to the first part of the interlayer insulating layer is greater than the thickness of the part of the flat layer corresponding to the second part of the interlayer insulating layer;

A distance between a first part of the interlayer insulating layer, which is far away from the surface of one side of the substrate, and a second part of the interlayer insulating layer, which is far away from the surface of one side of the substrate, is greater than 0nm and less than or equal to 200nm; the thickness of the second part of the interlayer insulating layer ranges from 1000nm to 1500nm;

The interlayer insulating layer includes: a first sub interlayer insulating layer and a second sub interlayer insulating layer which are laminated in this order; wherein, with respect to the substrate, a first sub-portion of the second sub-interlayer insulating layer corresponding to a first portion of the interlayer insulating layer is away from a surface of the substrate side, and is lower than a second sub-portion of the second sub-interlayer insulating layer corresponding to a second portion of the interlayer insulating layer is away from a surface of the substrate side; the thickness of the third sub-portion of the first sub-interlayer insulating layer corresponding to the first portion of the interlayer insulating layer is smaller than the thickness of the fourth sub-portion of the first sub-interlayer insulating layer corresponding to the second portion of the interlayer insulating layer.

2. The display substrate according to claim 1, wherein the transistor further comprises a second gate electrode provided between the active layer and the first gate insulating layer;

The orthographic projection of the second grid electrode on the substrate is positioned in the orthographic projection range of the first part of the interlayer insulating layer on the substrate.

3. The display substrate of claim 1, wherein the display substrate further comprises: a pixel defining layer and a plurality of spacers, which are arranged on one side of the flat layer away from the substrate and are sequentially laminated;

The orthographic projection of the plurality of spacers on the substrate is not overlapped with the orthographic projection of the first part of the interlayer insulating layer on the substrate.

4. A display substrate according to any one of claims 1-3, wherein the number of transistors is plural, the plural transistors including at least one of a driving transistor, a compensating transistor, and a reset transistor.

5. A method of manufacturing a display substrate, the display substrate comprising at least one transistor, the method comprising:

providing a substrate;

Sequentially forming an active layer, a gate insulating film, a first gate electrode, and an interlayer insulating film on the substrate;

In a one-time patterning process, patterning the interlayer insulating film and the gate insulating film to obtain a first gate insulating layer and an interlayer insulating layer; wherein the orthographic projection of the first grid electrode on the substrate is positioned in the orthographic projection range of the first part of the interlayer insulating layer on the substrate; the interlayer insulating layer includes a first portion and a second portion; the orthographic projection of the first part of the interlayer insulating layer on the substrate and the orthographic projection of the first grid electrode on the substrate are at least partially overlapped; a first portion of the interlayer insulating layer is lower than a surface of the interlayer insulating layer on a side away from the substrate with respect to the substrate;

Sequentially forming a source-drain electrode layer and a flat layer on one side of the interlayer insulating layer, which is far away from the substrate; the source-drain electrode layer comprises a source electrode and a drain electrode; orthographic projections of the source electrode and the drain electrode on the substrate are not overlapped with orthographic projections of the first part of the interlayer insulating layer on the substrate;

The interlayer insulating layer includes: a first sub interlayer insulating layer and a second sub interlayer insulating layer which are laminated in this order; wherein, with respect to the substrate, a first sub-portion of the second sub-interlayer insulating layer corresponding to a first portion of the interlayer insulating layer is away from a surface of the substrate side, and is lower than a second sub-portion of the second sub-interlayer insulating layer corresponding to a second portion of the interlayer insulating layer is away from a surface of the substrate side; the thickness of a third sub-part corresponding to a first part of the interlayer insulating layer in the first sub-interlayer insulating layer is smaller than the thickness of a fourth sub-part corresponding to a second part of the interlayer insulating layer in the first sub-interlayer insulating layer;

in the one-time patterning process, patterning the interlayer insulating film to obtain an interlayer insulating layer, including:

forming a photoresist layer on a surface of the interlayer insulating film on a side remote from the substrate;

exposing and developing the photoresist layer through a gray-scale mask plate to form a patterned photoresist layer; the patterned photoresist layer is provided with a full reserved area and a partial reserved area; the completely reserved area of the patterned photoresist layer corresponds to a second part to be formed in the interlayer insulating film, and the partially reserved area of the patterned photoresist layer corresponds to a first part to be formed in the interlayer insulating film;

And etching the interlayer insulating film by taking the patterned photoresist layer as a mask, so that the thickness of a first part to be formed in the interlayer insulating film is reduced, and the interlayer insulating layer comprising the first part and the second part is obtained.

6. The method of manufacturing a display substrate according to claim 5, wherein forming an interlayer insulating film comprises:

Sequentially forming a first sub-interlayer insulating film and a second sub-interlayer insulating film on one side of the first grid electrode far away from the substrate to obtain the interlayer insulating film;

In a one-time patterning process, performing patterning treatment on the interlayer insulating film to obtain an interlayer insulating layer, including:

Forming a photoresist layer on a surface of the second interlayer insulating film on a side remote from the substrate;

Exposing and developing the photoresist layer through a gray-scale mask plate to form a patterned photoresist layer; the patterned photoresist layer is provided with a full reserved area and a partial reserved area; the full reserved area of the patterned photoresist layer corresponds to a second sub-part to be formed in the second sub-interlayer insulating film, and the partial reserved area of the patterned photoresist layer corresponds to a first sub-part to be formed in the second sub-interlayer insulating film;

Etching the second sub-interlayer insulating film by taking the patterned photoresist layer as a mask, so that the thickness of a first sub-part to be formed in the second sub-interlayer insulating film is reduced, and a second sub-interlayer insulating layer comprising the first sub-part and the second sub-part is obtained; wherein a first sub-portion of the second sub-interlayer insulating layer corresponds to a first portion of the interlayer insulating layer, and a second sub-portion of the second sub-interlayer insulating layer corresponds to a second portion of the interlayer insulating layer; the first sub-portion of the second sub-interlayer insulating layer is lower than the surface of the second sub-interlayer insulating layer on the side away from the substrate with respect to the substrate.

7.A display device comprising the display substrate according to any one of claims 1 to 4.