CN111261588B - Thin film transistor array panel and manufacturing method thereof - Google Patents
Thin film transistor array panel and manufacturing method thereof Download PDFInfo
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- CN111261588B CN111261588B CN202010079688.2A CN202010079688A CN111261588B CN 111261588 B CN111261588 B CN 111261588B CN 202010079688 A CN202010079688 A CN 202010079688A CN 111261588 B CN111261588 B CN 111261588B
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- 239000010409 thin film Substances 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 112
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 39
- 238000005530 etching Methods 0.000 claims description 23
- 238000002834 transmittance Methods 0.000 claims description 12
- 230000005540 biological transmission Effects 0.000 claims description 11
- 238000010329 laser etching Methods 0.000 claims description 10
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 239000000463 material Substances 0.000 description 10
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 238000004380 ashing Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229920001621 AMOLED Polymers 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- -1 silicon oxide compound Chemical class 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010668 complexation reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a thin film transistor array panel and a manufacturing method thereof, comprising the following steps: forming a device board, wherein the device board is sequentially laminated with a substrate, a grid electrode insulating layer, an active layer and a metal layer; forming a photoresist layer on the metal layer, wherein the photoresist layer comprises a first part of the photoresist layer and a second part of the photoresist layer; processing the first portion of the photoresist layer with a combination of a mask plate and a laser beam to remove the first portion of the photoresist layer; processing the metal layer to form a source electrode pattern, a drain electrode pattern and a channel region; and stripping the second part of the photoresist layer. The thin film transistor array panel and the manufacturing method thereof can improve the stability of the thin film transistor in the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor array panel and a manufacturing method thereof.
Background
Display panels are divided into two main categories, liquid crystal displays (Liquid Crystal Display, LCD) and active matrix light emitting diodes (Active Matrix Organic Light Emitting Diode, AMOLED).
Thin film transistors (Thin Film Transistor, TFT) in organic light emitting diodes and liquid crystal displays (Liquid Crystal Display, LCD) are classified into bottom gate thin film transistors and top gate thin film transistors according to the manufacturing process of the gate electrodes; the bottom gate type thin film transistor is divided into a back channel etching type thin film transistor and a channel protection film type thin film transistor. At present, a four-Mask (Mask) is commonly used to form a fabrication process of a back Channel type thin film transistor, in which an etching process is used to process photoresist in a Channel region so as to facilitate formation of a subsequent Channel (Channel), however, when the etching process is used to process the photoresist in the Channel region, the thickness of the photoresist outside the Channel region is often reduced, and the photoresist cannot effectively block etching liquid during subsequent etching, so that stability of the thin film transistor in a display panel is affected.
Therefore, a new solution is needed to solve the above-mentioned problems.
Disclosure of Invention
The embodiment of the invention provides a thin film transistor array panel and a manufacturing method thereof, which are used for improving the stability of a thin film transistor in a display panel.
The embodiment of the invention provides a manufacturing method of a thin film transistor array panel, which comprises the following steps:
step A: forming a device board, wherein the device board is sequentially laminated with a substrate, a grid electrode insulating layer, an active layer and a metal layer;
and (B) step (B): forming a photoresist layer on the metal layer, wherein the photoresist layer comprises a first part of the photoresist layer and a second part of the photoresist layer;
step C: processing the first portion of the photoresist layer with a combination of a mask plate and a laser beam to remove the first portion of the photoresist layer;
step D: processing the metal layer to form a source electrode pattern, a drain electrode pattern and a channel region;
step E: and stripping the second part of the photoresist layer.
In the method for manufacturing a thin film transistor array panel according to the embodiment of the present invention, the step C includes:
step c1: the mask plate is arranged on the photoresist layer in a frame mode;
step c2: and irradiating laser to the mask plate, so that the laser penetrating through the mask plate performs laser etching on the first part of the photoresist layer to remove the first part of the photoresist layer.
In the method for manufacturing a thin film transistor array panel according to the embodiment of the present invention, the step c2 includes:
the mask plate is translated to a predetermined distance in a horizontal direction of the device plate such that a first portion of the photoresist layer is etched.
In the method for manufacturing a thin film transistor array panel according to the embodiment of the present invention, the step D includes:
step d1: and carrying out laser etching on the position, corresponding to the first part of the photoresist layer, of the metal layer by utilizing the combination of the mask plate and the laser beam so as to form the source electrode pattern, the drain electrode pattern and the channel region.
In the method for manufacturing a thin film transistor array panel according to the embodiment of the present invention, the step d1 includes:
step d11: the mask plate is arranged on the photoresist layer in a frame mode;
step d12: and irradiating the mask plate with the laser, so that the laser penetrating through the mask plate performs laser etching on the position, corresponding to the first part of the photoresist layer, of the metal layer to form the source electrode pattern, the drain electrode pattern and the channel region.
In the method for manufacturing the thin film transistor array panel, the mask plate comprises a light transmission area and a light shielding area, wherein the light transmission area of the mask plate is arranged at a position corresponding to the first part of the photoresist layer, and the light shielding area of the mask plate is arranged at a position corresponding to the second part of the photoresist layer.
In the method for manufacturing the thin film transistor array panel, the light-transmitting region of the mask plate comprises a first light-transmitting portion and a second light-transmitting portion, the second light-transmitting portion is located on two sides of the first light-transmitting portion, and the light transmittance of the first light-transmitting portion is smaller than that of the second light-transmitting portion.
In the method for manufacturing a thin film transistor array panel according to the embodiment of the present invention, the step D further includes:
step d2: and etching the position, corresponding to the first part of the photoresist layer, of the metal layer by adopting an etching process so as to form the source electrode pattern, the drain electrode pattern and the channel region.
The manufacturing method of the thin film transistor array panel comprises the following steps:
and forming the channel region protection layer.
The embodiment of the invention also comprises a thin film transistor array panel, which is manufactured by the manufacturing method of the thin film transistor array panel.
Compared with the prior art, in the thin film transistor and the manufacturing method thereof in the embodiment of the invention, the photoresist in the channel region is etched by utilizing the combination of the mask plate and the laser beam, so that the thickness of the photoresist outside the channel region is prevented from being thinned, etching liquid can be effectively blocked by the photoresist during subsequent etching, and the metal layer is prevented from being etched, thereby improving the stability of the thin film transistor in the display panel.
In addition, the combination of the mask plate and the laser beam is utilized to etch the photoresist, so that the production time can be greatly shortened, and the productivity can be improved.
Meanwhile, due to the fact that the light transmittance of different areas of the mask plate is different, the exposed photoresist and the flatness of a channel area formed subsequently can be effectively improved, and therefore the charging characteristic of a thin film transistor channel is improved.
In order to make the above-mentioned objects of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a thin film transistor array panel according to an embodiment of the present invention;
fig. 2 to fig. 6 are schematic diagrams illustrating a method for manufacturing a thin film transistor array panel according to an embodiment of the invention;
fig. 7 is a schematic diagram of a tft array panel according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a mask plate in a method for manufacturing a thin film transistor array panel according to an embodiment of the present invention.
Detailed Description
For a better understanding of the present invention, its objects, technical solutions and advantages, reference should be made to the following detailed description of the invention with reference to the drawings wherein like reference numerals refer to like elements throughout the several views, and the following description is based on the illustrated embodiments of the invention, which should not be construed as limiting other embodiments of the invention not described herein. The word "embodiment" is used in this specification to mean an example, instance, or illustration. Furthermore, the articles "a" and "an" as used in this specification and the appended claims may generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form.
In the embodiment of the invention, the method for manufacturing the thin film transistor array panel includes a method for manufacturing the thin film transistor array panel in the active matrix organic light emitting diode and a method for manufacturing the thin film transistor array panel in the liquid crystal display, wherein the thin film transistor array panel includes the thin film transistor array panel in the active matrix organic light emitting diode and the thin film transistor array panel in the liquid crystal display.
As shown in fig. 1, an embodiment of the present invention provides a method for manufacturing a thin film transistor array panel, including:
step S1: forming a device board in which a substrate 100, a gate electrode 110, a gate insulating layer 120, an active layer 130, and a metal layer 140 are sequentially stacked;
specifically, as shown in fig. 2, first, after the substrate 100 is cleaned, a metal film layer is deposited on the surface of the substrate 100 by using a sputtering film coating method, a gate 110 is formed by using a photolithography technique, and the material of the gate 110 includes one or two or more of tantalum (Ta), molybdenum (Mo), tungsten (W), and aluminum (Al), wherein the substrate 100 includes a glass substrate and a flexible substrate; then, a gate insulating layer 120 and an active layer 130 are sequentially formed on the gate electrode 110 using a chemical vapor deposition (Chemical Vapor Deposition, CVD) technique, and a material of the gate insulating layer 120 includes a silicon oxide compound (SiO x ) And silicon nitride compound (SiN) x ) Alumina (Al) 2 O 3 ) Tantalum pentoxide (Ta) 2 O 5 ) And the like, the material of the active layer 130 includes IGZO (Indium Gallium Zinc Oxide ) and a polysilicon material, for example, when the active layer 130 is a polysilicon material, a semiconductor active layer is first formed on the gate insulating layer 120 using a chemical vapor deposition technique, and in order to reduce contact resistance between a metal electrode and amorphous silicon, the amorphous silicon material is converted into the polysilicon material using an excimer laser annealing (Excimer Laser Anneal, ELA) process to form the polysilicon active layer 130; next, a metal layer 140 is formed on the active layer 130 using a chemical vapor deposition technique, a physical vapor deposition technique, or a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) technique, the metal layer material including a metal simple substance of aluminum, copper, molybdenum, titanium, or an alloy material having a metal simple substance of aluminum, copper, molybdenum, titanium, or the like as a main body,the thickness of the metal layer 140 is 100 nm to 3000 nm.
Step S2: forming a photoresist layer 150 on the metal layer 140, the photoresist layer 150 including a first portion 1501 of the photoresist layer and a second portion 1502 of the photoresist layer;
specifically, as shown in fig. 3, a photoresist material is coated on the surface of the metal layer 140, and the photoresist layer 150 is formed by irradiation or radiation of a light source such as ultraviolet light, excimer laser, electron beam, ion beam, X-ray, etc., the photoresist layer 150 includes a first portion 1501 of the photoresist layer and a second portion 1502 of the photoresist layer, the photoresist material includes a photoresist compound, etc., the thickness of the photoresist layer 150 is 0.5 to 5 micrometers, and the width of the first portion 1501 of the photoresist layer is 5 to 500 nanometers.
Step S3: processing the first portion 1501 of the photoresist layer with a combination of a mask plate 20 and a laser beam to remove photoresist from the first portion 1501 of the photoresist layer;
further, as shown in fig. 4, step S3 includes:
step S31: erecting the mask plate 20 on the photoresist layer 150;
step S32: the mask plate 20 is irradiated with a laser such that the first portion 1501 of the photoresist layer is laser etched through the laser of the mask plate 20 to remove the photoresist 1501 of the first portion of the photoresist layer.
Specifically, a mask plate 20 is erected on the photoresist layer 150, the distance between the mask plate 20 and the photoresist layer 150 is greater than zero, a laser beam is erected on the mask plate 20 in parallel, and a light spot of the laser beam is aligned to the first portion 1501 of the photoresist layer to remove the photoresist on the first portion 1501 of the photoresist layer, wherein the etching precision of the laser beam is 0.5 micrometers to 5 micrometers, the etching width is 5 nanometers to 500 nanometers, the etching speed is 0 to 3000mm/s, the etching time is 1 second to 30 seconds, and the wavelength of the laser beam comprises the laser wavelength of a fiber laser, the laser wavelength of a green laser, the laser wavelength of an ultraviolet laser, and the like.
Further, the step S32 further includes: translating the mask plate 20 to a predetermined distance in a horizontal direction of the device plate such that a first portion 1501 of the photoresist layer is etched; specifically, the mask plate 20 is moved at a predetermined speed, for example, at a speed of 1nm/s (nanometer/second), so that the photoresist at the angle of the horizontal direction and the vertical direction of the device plate is completely etched to secure the flatness of the exposed photoresist. It should be noted that, the mask plate 20 may move back and forth, that is, the number of movements is greater than or equal to 1, the predetermined moving speed is 0.1nm/s to 10nm/s, and the predetermined distance is 1nm to 1000 nm.
Further, the mask 20 includes a light-transmitting region 201 and a light-shielding region 202, where the light-transmitting region 201 of the mask 20 is erected at a position corresponding to the first portion 1501 of the photoresist layer, and the light-shielding region 202 of the mask 20 is erected at a position corresponding to the second portion 1052 of the photoresist layer, where the width of the light-transmitting region 201 is 5 nm to 500 nm.
Alternatively, as shown in fig. 8, the light-transmitting region 201 of the mask plate 20 includes a first light-transmitting portion 2011 and a second light-transmitting portion 2012, the second light-transmitting portion 2012 is located at two sides of the first light-transmitting portion 2011, and the light transmittance of the first light-transmitting portion 2011 is smaller than the light transmittance of the second light-transmitting portion 2012. Specifically, the light transmittance of the first light-transmitting portion 2011 of the light-transmitting region 201 of the mask 20 includes 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100%, and the light transmittance of the second light-transmitting portion 2012 of the light-transmitting region 201 of the mask 20 includes 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100%, and when the first portion 1501 of the photoresist layer is processed by using the combination of the mask 20 and the laser beam, since the light transmittance of the second light-transmitting portion 2012 of the light-transmitting region 201 is greater than the light transmittance of the first light-transmitting portion 2011, the photoresist exposure of the portion can be uniform, and the flatness of the exposed photoresist can be improved.
In the embodiment of the invention, the first portion 201 of the photoresist layer is etched by using the combination of the mask plate 20 and the laser beam, so that the second portion 202 of the photoresist layer is protected from being etched, the occurrence of broken lines is avoided, the yield of products is improved, and the time for processing the photoresist layer by adopting the laser etching process is only 20% of the time spent on the oxygen ashing treatment, so that the productivity is greatly improved.
Step S4: processing the metal layer 140 to form a source pattern 160, a drain pattern 170, and a channel region;
further, an etching process is used to etch the metal layer 140 at a position corresponding to the first portion 1501 of the photoresist layer, so as to form the source pattern 160, the drain pattern 170 and the channel region. In the embodiment of the present invention, for example, the second portion 1502 of the photoresist layer is used as a mask, and one or two or more of hydrofluoric acid (HF), nitric acid, acetic acid, hydrochloric acid, and phosphoric acid with a specific concentration and a combination of two or more are used to react the position of the metal layer 140 corresponding to the first portion 1501 of the photoresist layer.
Optionally, as shown in fig. 5, in an embodiment of the present invention, step S4 further includes:
the metal layer 140 is laser etched at a position corresponding to the first portion 1501 of the photoresist layer using a combination of the mask plate 20 and the laser beam to form the source pattern 160, the drain pattern 170, and the channel region. Specifically, the laser is irradiated to the mask plate 20, so that the laser transmitted through the mask plate 20 performs laser etching on the metal layer 140 at a position corresponding to the first portion 1501 of the photoresist layer, to form the source pattern 160, the drain pattern 170, and the channel region.
Specifically, the mask plate 20 is erected on the photoresist layer 150, the distance between the mask plate 20 and the photoresist layer 150 is greater than zero, a laser beam is erected on the mask plate 20 in parallel, a light spot of the laser beam is aligned to the first portion 1501 of the photoresist layer, and laser etching is performed on the position, corresponding to the first portion 1501 of the photoresist layer, of the metal layer 140 to form the source pattern 160, the drain pattern 170 and the channel region, wherein the etching precision of the laser beam is 0.5 micrometers to 5 micrometers, the etching width is 5 nanometers to 500 nanometers, the etching speed is 0 to 3000mm/s, the etching time is 1 second to 30 seconds, and the wavelength of the laser beam includes the laser wavelength of the fiber laser, the laser wavelength of the green laser, the laser wavelength of the ultraviolet laser, and the like.
Further, the step S4 further includes: translating the mask plate 20 to a predetermined distance in a horizontal direction of the device plate such that a portion of the metal layer 140 corresponding to the first portion 1501 of the photoresist layer is etched; specifically, the mask plate 20 is moved at a predetermined speed, for example, at a speed of 1nm/s (nanometer/second), so that the metal layer 140 at an angle between the horizontal direction and the vertical direction of the device plate is completely etched to secure the flatness of the exposed metal layer 140, improving the charging characteristics of the thin film transistor channel. It should be noted that, the mask plate 20 may move back and forth, that is, the number of movements is greater than or equal to 1, the predetermined moving speed is 0.1nm/s to 10nm/s, and the predetermined distance is 1nm to 1000 nm.
Further, the mask 20 includes a light-transmitting region 201 and a light-shielding region 202, where the light-transmitting region 201 of the mask 20 is erected at a position corresponding to the first portion 1501 of the photoresist layer, and the light-shielding region 202 of the mask 20 is erected at a position corresponding to the second portion 105 of the photoresist layer, where the width of the light-transmitting region 201 is 5 nm to 500 nm.
Optionally, referring to fig. 8, the light-transmitting region 201 of the mask plate 20 includes a first light-transmitting portion 2011 and a second light-transmitting portion 2012, the second light-transmitting portion 2012 is located at two sides of the first light-transmitting portion 2011, and the light transmittance of the first light-transmitting portion 2011 is smaller than the light transmittance of the second light-transmitting portion 2012. When the mask plate 20 and the laser beam are used for processing the metal layer 140 and the first portion 1501 of the photoresist layer, the metal layer 140 of the portion can be uniformly exposed, the flatness of the exposed metal layer 140 is improved, and the charging characteristic of the thin film transistor channel is improved.
In the step of using the combination of the mask plate 20 and the laser beam to form the source pattern 160, the drain pattern 170, and the channel region, the etching precision of the laser may be adjusted, and after the first portion 1501 of the photoresist layer is removed using the mask plate 20 and the laser beam, the laser etching may be continued to form the source pattern 160, the drain pattern 170, and the channel region.
Step S5: the photoresist of the second portion 1502 of the photoresist layer is stripped.
Wherein, as shown in fig. 6, the stripping method comprises wet stripping and dry ashing, specifically, when wet stripping is used, the organic solvent or alkaline aqueous solution is used to carry out complexation reaction with the photoresist polymer so as to dissolve and remove the photoresist of the second part 1502 of the photoresist layer; when dry ashing is used, plasma ashing or ozone ashing is used to oxidize and decompose the photoresist in the second portion 1502 of the photoresist layer.
Further, as shown in fig. 7, in an embodiment of the present invention, the method for manufacturing a thin film transistor array panel includes:
forming a channel protection layer 180; wherein the channel protection layer 180 is formed by chemical vapor deposition technique, physical vapor deposition technique, plasma enhanced chemical vapor deposition technique or atomic layer deposition, and the material of the channel protection layer 180 comprises silicon oxide compound (SiO) x ) And silicon nitride compound (SiN) x ) Alumina (Al) 2 O 3 ) Tantalum pentoxide (Ta) 2 O 5 ) Etc.
The embodiment of the invention also comprises a thin film transistor array panel which is manufactured by the manufacturing method of the thin film transistor array panel, and concretely, as shown in the figure, the thin film transistor array panel comprises:
a substrate 100;
a gate electrode 110, the gate electrode 110 being disposed on the substrate 100;
a gate insulating layer 120, wherein the gate insulating layer 120 is disposed on the gate electrode 110 and covers the gate electrode 120 and the substrate 100;
an active layer 130, wherein the active layer 130 includes an active layer channel region and a portion electrically connected to the source electrode 160 and the drain electrode 170, and the active layer 130 covers the gate insulating layer 120;
the source electrode 160, wherein the source electrode 160 covers at least a portion of the active layer 130 and is electrically connected to the active layer 130;
the drain electrode 170, wherein the drain electrode 170 covers at least a portion of the active layer 130 and is electrically connected to the active layer 130;
a channel protection layer 180, wherein the channel protection layer 180 covers the source electrode 160, the drain electrode 170, and the channel region of the active layer 130.
Compared with the prior art, in the thin film transistor and the manufacturing method thereof in the embodiment of the invention, the photoresist in the channel region is etched by utilizing the combination of the mask plate and the laser beam, so that the thickness of the photoresist outside the channel region is prevented from being thinned, etching liquid can be effectively blocked by the photoresist during subsequent etching, and the metal layer is prevented from being etched, thereby improving the stability of the thin film transistor in the display panel.
In addition, the combination of the mask plate and the laser beam is utilized to etch the photoresist, so that the production time can be greatly shortened, and the productivity can be improved.
Meanwhile, due to the fact that the light transmittance of different areas of the mask plate is different, the exposed photoresist and the flatness of a channel area formed subsequently can be effectively improved, and therefore the charging characteristic of a thin film transistor channel is improved.
In summary, although the present invention has been described in terms of the preferred embodiments, the preferred embodiments are not limited to the above embodiments, and various modifications and changes can be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention is defined by the appended claims.
Claims (8)
1. A method for fabricating a thin film transistor array panel, comprising:
step A: forming a device board, wherein the device board is sequentially laminated with a substrate, a grid electrode insulating layer, an active layer and a metal layer;
and (B) step (B): forming a photoresist layer on the metal layer, wherein the photoresist layer comprises a first part of the photoresist layer and a second part of the photoresist layer;
step C: processing the first portion of the photoresist layer with a combination of a mask plate and a laser beam to remove the first portion of the photoresist layer; the mask plate comprises a light transmission area and a light shielding area, wherein the light transmission area corresponds to the first part, the light shielding area corresponds to the second part, the light transmission area comprises a first light transmission part and a second light transmission part, the second light transmission part is positioned at two sides of the first light transmission part, and the light transmittance of the first light transmission part is smaller than that of the second light transmission part;
the step C comprises the following steps:
moving the mask plate back and forth along the horizontal direction of the device plate;
step D: processing the metal layer to form a source electrode pattern, a drain electrode pattern and a channel region;
the step D comprises the following steps:
step d1: performing laser etching on the position, corresponding to the first part of the photoresist layer, of the metal layer by utilizing the combination of the mask plate and the laser beam so as to form a source electrode pattern, a drain electrode pattern and a channel region, wherein the source electrode pattern and the drain electrode pattern correspond to the shading region;
step E: and stripping the second part of the photoresist layer.
2. The method of manufacturing a thin film transistor array panel according to claim 1, wherein the step C comprises:
step c1: the mask plate is arranged on the photoresist layer in a frame mode;
step c2: and irradiating laser to the mask plate, so that the laser penetrating through the mask plate performs laser etching on the first part of the photoresist layer to remove the first part of the photoresist layer.
3. The method for manufacturing a thin film transistor array panel according to claim 2, wherein the step c2 comprises:
the mask plate is translated to a predetermined distance in a horizontal direction of the device plate such that a first portion of the photoresist layer is etched.
4. The method of manufacturing a thin film transistor array panel according to claim 1, wherein the step d1 comprises:
step d11: the mask plate is arranged on the photoresist layer in a frame mode;
step d12: and irradiating the mask plate with the laser, so that the laser penetrating through the mask plate performs laser etching on the position, corresponding to the first part of the photoresist layer, of the metal layer to form the source electrode pattern, the drain electrode pattern and the channel region.
5. The method according to any one of claims 1 to 4, wherein the mask plate includes a light-transmitting region and a light-shielding region, wherein the light-transmitting region of the mask plate is disposed at a position corresponding to the first portion of the photoresist layer, and the light-shielding region of the mask plate is disposed at a position corresponding to the second portion of the photoresist layer.
6. The method of manufacturing a thin film transistor array panel according to claim 1, wherein the step D further comprises:
step d2: and etching the position, corresponding to the first part of the photoresist layer, of the metal layer by adopting an etching process so as to form the source electrode pattern, the drain electrode pattern and the channel region.
7. The method of manufacturing a thin film transistor array panel according to any one of claims 1 to 4, comprising:
and forming the channel region protection layer.
8. A thin film transistor array panel, characterized in that the thin film transistor is manufactured by the manufacturing method of the thin film transistor array panel according to any one of claims 1 to 7.
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| CN202010079688.2A CN111261588B (en) | 2020-02-04 | 2020-02-04 | Thin film transistor array panel and manufacturing method thereof |
| PCT/CN2020/079567 WO2021155625A1 (en) | 2020-02-04 | 2020-03-17 | Thin film transistor array panel and manufacturing method therefor |
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| CN104022078A (en) * | 2014-05-29 | 2014-09-03 | 京东方科技集团股份有限公司 | Preparation method of array substrate |
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| CN104409361A (en) * | 2014-12-16 | 2015-03-11 | 京东方科技集团股份有限公司 | Thin-film transistor, preparation method of thin-film transistor, array substrate and display device |
| CN105977210A (en) * | 2016-05-20 | 2016-09-28 | 深圳市华星光电技术有限公司 | Array substrate and preparation method thereof |
| CN110061015B (en) * | 2019-05-10 | 2021-03-02 | 业成科技（成都）有限公司 | TFT array substrate and manufacturing method thereof |
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| CN103066017A (en) * | 2012-12-28 | 2013-04-24 | 北京京东方光电科技有限公司 | Preparing method of array substrate |
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| WO2021155625A1 (en) | 2021-08-12 |
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