CN107346960B - Low-offset operational amplifier based on active load adjustment - Google Patents

Low-offset operational amplifier based on active load adjustment Download PDF

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CN107346960B
CN107346960B CN201710453918.5A CN201710453918A CN107346960B CN 107346960 B CN107346960 B CN 107346960B CN 201710453918 A CN201710453918 A CN 201710453918A CN 107346960 B CN107346960 B CN 107346960B
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nmos transistor
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transistor
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CN107346960A (en
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王红义
朱奥麟
徐延超
周罡
曹灿
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Huatech Semiconductor Inc
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Huatech Semiconductor Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
    • H03F1/342—Negative-feedback-circuit arrangements with or without positive feedback in field-effect transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0088—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/471—Indexing scheme relating to amplifiers the voltage being sensed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45031—Indexing scheme relating to differential amplifiers the differential amplifier amplifying transistors are compositions of multiple transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45044—One or more switches are opened or closed to balance the dif amp to reduce the offset of the dif amp

Abstract

A low-offset operational amplifier based on active load adjustment comprises an operational amplifier module, a comparator module, a logic control unit and a four-bit successive approximation register; the in-phase input end of the comparator module is connected with the detection voltage Vdec of the operational amplifier module, and the reverse-phase input end of the comparator module is connected with VDD/2; the input end of the logic control unit is connected with the output end of the comparator module; the four-bit successive approximation comparison register is connected with the output end of the logic control unit, and the output ports of the four-bit successive approximation comparison register are four ports a0, a1, a2 and a3, and are used for adjusting the number of transistors connected in series on one side of an active load. The design of the operational amplifier increases the detection level, and avoids the uncertain jump of the output end level when the misadjustment is corrected, which influences the use of users.

Description

Low-offset operational amplifier based on active load adjustment
Technical Field
The invention belongs to the field of CMOS (complementary metal oxide semiconductor) process integrated circuits, and particularly relates to a low-offset operational amplifier based on active load regulation.
Background
The prepared operational amplifier inevitably has the problem of offset voltage because of the uncertainty of each procedure in the integrated circuit manufacturing process. The operational amplifier designed by adopting the bipolar transistor process has the advantages that the offset voltage can achieve a relatively ideal effect, but the bipolar transistor device has large power consumption and high cost, so the operational amplifier is rarely adopted. The mainstream production process at present is a CMOS process, and has the characteristics of low cost, low power consumption and high integration degree. However, the classical value of the operational amplifier offset of the operational amplifier designed based on the CMOS process is about 10mV, which cannot be tolerated in many applications. The offset voltage of the operational amplifier has two components: one is systematic misalignment due to misalignment of devices in the circuit due to improper device sizing or bias conditions; the other is a random offset voltage, which is an offset caused by random errors inevitable in the manufacturing process. To obtain better matching to reduce the random offset of the amplifier, the low offset operational amplifier usually uses a large input tube and a large active load, but introduces extra capacitance and consumes a very large area.
The invention provides a novel offset correction technology of a CMOS operational amplifier, which improves the symmetry of an active load in a mode of adjusting the length of a channel of the active load and effectively solves the offset problem of the operational amplifier.
Disclosure of Invention
The invention aims to provide a low-offset operational amplifier based on an active load adjustment, which solves the problem of offset of the operational amplifier.
In order to achieve the purpose, the invention adopts the following technical scheme:
a low-offset operational amplifier based on active load adjustment comprises an operational amplifier module, a comparator module, a logic control unit and a four-bit successive approximation register; the in-phase input end of the comparator module is connected with the detection voltage Vdec of the operational amplifier module, and the reverse-phase input end of the comparator module is connected with VDD/2; the input end of the logic control unit is connected with the output end of the comparator module; the four-bit successive approximation comparison register is connected with the output end of the logic control unit, and the output ports of the four-bit successive approximation comparison register are four ports a0, a1, a2 and a3, and are used for adjusting the number of transistors connected in series on one side of an active load.
Further, the operational amplifier module is divided into three parts: a gain stage, a detection stage and an output stage;
the gain stage comprises a PMOS transistor MP101, a PMOS transistor MP102, an NMOS transistor MN101, an NMOS transistor MN102, an NMOS transistor MN105, an NMOS transistor MN106, an NMOS transistor MN107, an NMOS transistor MN108, a current source Ib101, a switch k102, a switch k104, a switch a101, a switch a102, a switch a103 and a switch a 104; the non-inverting input end is connected with the grid electrode of the PMOS transistor MP102 through a switch k104, the inverting input end is connected with the grid electrode of the PMOS transistor MP101 through a switch k101, one end of the switch k102 is connected with the non-inverting input end, and the other end of the switch k102 is connected with the grid electrode of the PMOS transistor MP 101; the PMOS transistors MP101 and MP102 are input tubes of operational amplifiers, the sources thereof are connected with one end of a bias current source Ib101, and the other end of the current source Ib101 is connected with a power supply VDD; the NMOS transistor MN101 and the NMOS transistor MN102 form a current mirror load; the NMOS transistor MN101 is the source of the current mirror, the drain of the NMOS transistor MN is connected with the drain of the PMOS transistor MP101, and the source is grounded; the drain of the NMOS transistor MN102 is connected to the drain of the PMOS transistor MP102, and the drain of the NMOS transistor MN102 is also the output terminal of the gain stage; the gate of the NMOS transistor MN102 is connected with the drain of the NMOS transistor MN 101; the gates of the NMOS transistor MN105, the NMOS transistor MN106, the NMOS transistor MN107 and the NMOS transistor MN108 are connected, connected with the gate of the NMOS transistor MN101 and connected in series in a mode that the source and the drain are connected; the drain of the NMOS transistor MN105 is connected with the source of the NMOS transistor MN102, and the source of the NMOS transistor MN108 is grounded; the switch a101 is connected in parallel at the source-drain two ends of the NMOS transistor MN105, the switch a102 is connected in parallel at the source-drain two ends of the NMOS transistor MN106, the switch a103 is connected in parallel at the source-drain two ends of the NMOS transistor MN106, and the switch a104 is connected in parallel at the source-drain two ends of the NMOS transistor MN 107;
the detection stage comprises an NMOS transistor MN103 and a current source Ib 102; the output end of the gain stage is connected with the gate of the NMOS transistor MN103, namely the drain of the NMOS transistor MN102 is connected with the gate of the NMOS transistor MN 103; the NMOS transistor MN103 is biased by the current source Ib102, and has a drain connected to one end of the current source Ib102 and a source grounded; the other end of the current source Ib102 is connected with a power supply VDD; the drain of NMOS transistor MN103 outputs voltage signal Vdec;
the output stage comprises an NMOS transistor MN104, a current source Ib103, a switch k105 and a capacitor C101; the grid of the NMOS transistor MN104 is connected with the output end of the gain stage amplifier through a switch k105, namely the drain of the NMOS transistor MN102 is connected with one end of the switch k105, and the other end of the switch k105 is connected with the grid of the NMOS transistor MN 104; the drain electrode of the NMOS transistor MN104 is an output end VOUT, and the source electrode of the NMOS transistor MN is grounded; the current source Ib103 is used for biasing the NMOS transistor MN104, one end of the current source is connected with the drain electrode of the NMOS transistor MN104, and the other end of the current source is connected with a power supply VDD; the capacitor C101 is a Miller compensation capacitor, one end of the capacitor is connected with the drain electrode of the NMOS transistor MN104, and the other end of the capacitor is connected with the grid electrode of the NMOS transistor MN 104; the switch k103 has one end connected to the gate of the NMOS transistor MN104 and the other end connected to ground.
Further, the gain stage can further include a PMOS transistor MP201, a PMOS transistor MP202, a PMOS transistor MP203, a PMOS transistor MP204, a PMOS transistor MP205, a PMOS transistor MP206, an NMOS transistor MN201, an NMOS transistor MN202, an NMOS transistor MN203, an NMOS transistor MN204, an NMOS transistor MN207, an NMOS transistor MN208, an NMOS transistor MN209, an NMOS transistor MN210, a current source Ib201, a switch k202, a switch k204, a switch a201, a switch a202, a switch a203, and a switch a 204; the non-inverting input end is connected with the grid electrode of the PMOS transistor MP202 through a k204, and the inverting input end is connected with the grid electrode of the PMOS transistor MP201 through a k 201; one end of the switch k202 is connected with the non-inverting input end, and the other end is connected with the grid electrode of the PMOS transistor MP 201; the PMOS transistor MP201 and the PMOS transistor MP202 are input tubes of operational amplifiers, the sources thereof are connected with one end of a bias current source Ib201, and the other end of the bias current source Ib201 is connected with a power supply VDD; the drain of the PMOS transistor MP201 is connected with the drain of the NMOS transistor MN201, and the drain of the PMOS transistor MP202 is connected with the drain of the NMOS transistor MN 202; the drain of the NMOS transistor MN201 is connected to the source of the NMOS transistor MN203, and the source thereof is connected to ground; the drain of the NMOS transistor MN202 is connected with the source of the NMOS transistor MN 204; the NMOS transistor MN201 is connected to the gate of the NMOS transistor MN202, and biased by an external voltage Vb 1; the NMOS transistor MN203 is connected to the gate of the NMOS transistor MN204, and biased by an external voltage Vb 2; the PMOS transistors MP203, MP204, MP205 and MP206 form a cascode current mirror load; the drain of the PMOS transistor MP205 is connected to the drain of the NMOS transistor MN203, the drain of the PMOS transistor MP206 is connected to the drain of the NMOS transistor MN204, and the drain of the PMOS transistor MP206 is the output terminal of the gain stage amplifier; the source electrode of the PMOS transistor MP205 is connected with the drain electrode of the PMOS transistor MP203, the source electrode of the PMOS transistor MP206 is connected with the drain electrode of the PMOS transistor MP204, the PMOS transistor MP203 is connected with the source electrode of the PMOS transistor MP204 and the power supply VDD, the grid electrode of the PMOS transistor MP203 is connected with the drain electrode of the PMOS transistor MP 203; the PMOS transistor MP205 is connected with the grid electrode of the PMOS transistor MP206 and is connected with the drain electrode of the PMOS transistor MP 205; the NMOS transistors MN207, MN208, MN209, and MN210 are used to adjust the equivalent length of the NMOS transistor MN202, and the gates of these transistors are connected to the gate of the NMOS transistor MN201, and are connected in series in a manner that the sources and drains are connected to each other; the drain of the NMOS transistor MN207 is connected with the source of the NMOS transistor MN202, and the source of the NMOS transistor MN210 is grounded; the switch a201 is connected in parallel to the source and drain ends of the NMOS transistor MN207, the switch a202 is connected in parallel to the source and drain ends of the NMOS transistor MN208, the switch a203 is connected in parallel to the source and drain ends of the NMOS transistor MN209, and the switch a204 is connected in parallel to the source and drain ends of the NMOS transistor MN 210.
Further, the NMOS transistor MN105, the NMOS transistor MN106, the NMOS transistor MN107, and the NMOS transistor MN108 are used to adjust the equivalent length of the NMOS transistor MN 102.
Further, the logic control unit outputs k1, k2, k3 and k4 control the internal switch states of the operational amplifier for switching the operational mode of the amplifier.
Compared with the prior art, the invention has the following technical effects:
the method adjusts the length of one side of the active load to correct the offset voltage of the operational amplifier in a Successive Approximation (SAR) mode, and can save 2^ n-n clock cycles compared with a scanning mode when the precision required to be corrected is n bits, thereby effectively improving the correction speed and reducing the starting time of a circuit.
The design of the operational amplifier increases the detection level, and avoids the uncertain jump of the output end level when the misadjustment is corrected, which influences the use of users.
Drawings
FIG. 1 is a block diagram of the present invention;
fig. 2 is a schematic circuit diagram in embodiment 1 of the present invention;
fig. 3 is a schematic circuit diagram in embodiment 2 of the present invention;
Detailed Description
The invention is further illustrated with reference to the following figures and examples:
a low-offset operational amplifier based on active load adjustment comprises an operational amplifier module, a comparator module, a logic control unit and a four-bit successive approximation register; the in-phase input end of the comparator module is connected with the detection voltage Vdec of the operational amplifier module, and the reverse-phase input end of the comparator module is connected with VDD/2; the input end of the logic control unit is connected with the output end of the comparator module; the four-bit successive approximation comparison register is connected with the output end of the logic control unit, the output ports of the four-bit successive approximation comparison register are four ports a0, a1, a2 and a3 and used for adjusting the number of transistors connected in series on one side of an active load, the four-bit successive approximation comparison register is provided with a clock signal clk, and the clock signal is the clock of an internal synchronous circuit of the four-bit successive approximation comparison register.
Example 1:
referring to fig. 2, the operational amplifier is divided into three parts: gain stage, detection stage, output stage.
The gain stage includes: the PMOS transistor MP101, the PMOS transistor MP102, the NMOS transistor MN101, the NMOS transistor MN102, the NMOS transistor MN105, the NMOS transistor MN106, the NMOS transistor MN107, the NMOS transistor MN108, the current source Ib101, the switch k102, the switch k104, the switch a101, the switch a102, the switch a103, and the switch a 104. The non-inverting input terminal is connected with the gate of the PMOS transistor MP102 through the k104, the inverting input terminal is connected with the gate of the PMOS transistor MP101 through the k101, one end of the switch k102 is connected with the non-inverting input terminal, and the other end is connected with the gate of the PMOS transistor MP 101. The PMOS transistor MP101 and the PMOS transistor MP102 are input transistors of the operational amplifier, and the sources thereof are connected to one end of the bias current source Ib101, and the other end of the current source Ib101 is connected to the power supply VDD. The NMOS transistor MN101 and the NMOS transistor MN102 constitute a current mirror load. The NMOS transistor MN101 is a source of the current mirror, and has a drain connected to the drain of the PMOS transistor MP101 and a source connected to ground. The drain of the NMOS transistor MN102 is connected to the drain of the PMOS transistor MP102, and the drain of the NMOS transistor MN102 is also the output terminal of the gain stage. The gate of the NMOS transistor MN102 is connected to the drain of the NMOS transistor MN 101. The NMOS transistors MN105, MN106, MN107, MN108 are used to adjust the equivalent length of the NMOS transistor MN102, and their gates are connected in series, connected to the gate of the NMOS transistor MN101, and connected in series in a source-drain connection manner. The drain of the NMOS transistor MN105 is connected to the source of the NMOS transistor MN102, and the source of the NMOS transistor MN108 is connected to ground. The switch a101 is connected in parallel at the source-drain both ends of the NMOS transistor MN105, the switch a102 is connected in parallel at the source-drain both ends of the NMOS transistor MN106, the switch a103 is connected in parallel at the source-drain both ends of the NMOS transistor MN106, and the switch a104 is connected in parallel at the source-drain both ends of the NMOS transistor MN 107.
The detection stage is composed of an NMOS transistor MN103 and a current source Ib 102. The output end of the gain stage is connected with the gate of the NMOS transistor MN103, namely the drain of the NMOS transistor MN102 is connected with the gate of the NMOS transistor MN 103. The NMOS transistor MN103 is biased by the current source Ib102, and has a drain connected to one end of the current source Ib102 and a source connected to ground. The other end of the current source Ib102 is connected to the power supply VDD. The drain of the NMOS transistor MN103 outputs a voltage signal Vdec, which is connected to the non-inverting input of U2 of the comparator of fig. 1.
The output stage includes: NMOS transistor MN104, current source Ib103, switch k105, and capacitor C101. The gate of the NMOS transistor MN104 is connected to the output terminal of the gain stage amplifier via a switch k105, i.e., the drain of the NMOS transistor MN102 is connected to one terminal of the switch k105, and the other terminal of the switch k105 is connected to the gate of the NMOS transistor MN 104. The drain of the NMOS transistor MN104 is the output terminal VOUT, and the source thereof is grounded. The current source Ib103 is used to bias the NMOS transistor MN104, and has one end connected to the drain of the NMOS transistor MN104 and the other end connected to the power supply VDD. The capacitor C101 is a miller compensation capacitor, and has one end connected to the drain of the NMOS transistor MN104 and the other end connected to the gate of the NMOS transistor MN 104. One end of the switch k103 is connected to the gate of the NMOS transistor MN104, and the other end is grounded, and when the switch k is closed, the gate of the NMOS transistor MN104 is pulled low.
When the operational amplifier starts to correct the detuning, a switch k101 of the gain stage is opened, a switch k102 is closed, the non-inverting end of the operational amplifier is externally connected with a common mode voltage, and a direct current working point of the amplifier is determined. The switch k104 is a normally closed switch for balancing the input load. At this time, the switch k105 of the output stage is opened, and the switch k103 is closed, so that VOUT outputs a constant high level.
In design, the size of the operational amplifier NMOS transistor MN102 is slightly larger than the size of the NMOS transistor MN101, so that the output Vdec of the detection stage is at a high level. In the correction, the offset of the operational amplifier is corrected by changing the equivalent width-to-length ratio by changing the number of transistors connected in series to the NMOS transistor MN 102. The gate widths of the NMOS transistor MN105, the NMOS transistor MN106, the NMOS transistor MN107, and the NMOS transistor MN104 are the same, and the ratio of the gate lengths is 1: 2: 4: 8.
the switches inside the operational amplifier are determined by the output of the 4-bit successive approximation register. a1 controls the state of switch a101, a2 controls the state of switch a102, a3 controls the state of switch a103, and a4 controls the state of switch a 104. When the output port of the register outputs a high level, the switch controlled correspondingly is closed, otherwise, the switch controlled correspondingly is opened.
The output of the 4-bit successive approximation register is initially 1111, that is, all the transistors connected in series to the transistor MN102 are short-circuited. As shown in Table I, the calibration process is divided into four steps, first, the highest bit a3 of the register is cleared, and the others are set to one. If Vdec jumps to low level at this time, indicating overcorrection, a3 is set to hold. If the level of Vdec is still high, it indicates that the correction is insufficient, and a3 is cleared and retained. Second, the register value clears a2, and a1 and a0 are set to one. If Vdec jumps to low level at this time, indicating overcorrection, a2 is set to hold. If Vdec is still low, the correction is insufficient, and a2 remains. Third, the register value clears a1 and a0 sets one. If Vdec is jumped to low level at this time, indicating that the correction is excessive, a1 is left after it is set. If the level of Vdec is still low, a1 is left if insufficient correction is indicated. Fourthly, when a0 is cleared to zero and the level of Vdec is changed to low level, the level is cleared and reserved. Otherwise a0 places a reservation.
TABLE 1
Figure BDA0001323230880000071
After the calibration is completed, the switch k101 is closed, the switch k102 is opened, the switch k103 is opened, the switch k105 is closed, and the operational amplifier operates normally.
Example 2:
the operational amplifier of this embodiment has the same structure as that of embodiment 1, and the gain stage in the operational amplifier main body module is replaced by a folded cascode amplifier.
Referring to fig. 2, the gain stage includes: the PMOS transistor MP201, the PMOS transistor MP202, the PMOS transistor MP203, the PMOS transistor MP204, the PMOS transistor MP205, the PMOS transistor MP206, the NMOS transistor MN201, the NMOS transistor MN202, the NMOS transistor MN203, the NMOS transistor MN204, the NMOS transistor MN207, the NMOS transistor MN208, the NMOS transistor MN209, the NMOS transistor MN210, the current source Ib201, the switch k202, the switch k204, the switch a201, the switch a202, the switch a203, and the switch a 204. The non-inverting input terminal is connected to the gate of the PMOS transistor MP202 via k204, and the inverting input terminal is connected to the gate of the PMOS transistor MP201 via k 201. One end of the switch k202 is connected to the non-inverting input terminal, and the other end is connected to the gate of the PMOS transistor MP 201. The PMOS transistor MP201 and the PMOS transistor MP202 are input transistors of the operational amplifier, and the sources thereof are connected to one end of the bias current source Ib201, and the other end of the bias current source Ib201 is connected to the power supply VDD. The drain of the PMOS transistor MP201 is connected to the drain of the NMOS transistor MN201, and the drain of the PMOS transistor MP202 is connected to the drain of the NMOS transistor MN 202. The drain of the NMOS transistor MN201 is connected to the source of the NMOS transistor MN203, and the source thereof is connected to ground. The drain of the NMOS transistor MN202 is connected to the source of the NMOS transistor MN 204. The NMOS transistor MN201 is connected to the gate of the NMOS transistor MN202, and is biased by an external voltage Vb 1. The NMOS transistor MN203 is connected to the gate of the NMOS transistor MN204, and is biased by an external voltage Vb 2. The PMOS transistors MP203, MP204, MP205, MP206 constitute a cascode current mirror load. The drain of the PMOS transistor MP205 is connected to the drain of the NMOS transistor MN203, the drain of the PMOS transistor MP206 is connected to the drain of the NMOS transistor MN204, and the drain of the PMOS transistor MP206 is the output terminal of the gain stage amplifier. The source of the PMOS transistor MP205 is connected to the drain of the PMOS transistor MP203, the source of the PMOS transistor MP206 is connected to the drain of the PMOS transistor MP204, the PMOS transistor MP203 is connected to the source of the PMOS transistor MP204, to the power supply VDD, and the gate thereof is connected to the drain of the PMOS transistor MP 203. The gates of the PMOS transistors MP205 and MP206 are connected to the drain of the PMOS transistor MP 205. The NMOS transistors MN207, MN208, MN209, and MN210 are used to adjust the equivalent length of the NMOS transistor MN202, and their gates are connected in series, connected to the gate of the NMOS transistor MN201, and connected in series in a source-drain connection manner. The drain of the NMOS transistor MN207 is connected to the source of the NMOS transistor MN202, and the source of the NMOS transistor MN210 is connected to ground. The switch a201 is connected in parallel to the source and drain ends of the NMOS transistor MN207, the switch a202 is connected in parallel to the source and drain ends of the NMOS transistor MN208, the switch a203 is connected in parallel to the source and drain ends of the NMOS transistor MN209, and the switch a204 is connected in parallel to the source and drain ends of the NMOS transistor MN 210.
When the operational amplifier starts to correct the detuning, a switch k201 of the gain stage is opened, a switch k202 of the gain stage is closed, the non-inverting end of the operational amplifier is externally connected with a common mode voltage, and a direct current working point of the amplifier is determined. The switch k204 is a normally closed switch for balancing the input load. At this time, the switch k205 of the output stage is opened, and the switch k203 is closed, so that VOUT outputs a constant high level.
In design, the size of the NMOS transistor MN202 of the operational amplifier is slightly larger than that of the NMOS transistor MN201, so that the output Vdec of the detection stage is at a high level. In the correction, the offset of the operational amplifier is corrected by changing the equivalent width-to-length ratio by changing the number of transistors connected in series to the NMOS transistor MN 202. The gate widths of the NMOS transistors MN207, MN208, MN209, and MN210 are the same, and the ratio of the gate lengths is 1: 2: 4: 8.
the switches inside the operational amplifier are determined by the output of the 4-bit successive approximation register. a1 controls the state of switch a201, a2 controls the state of switch a202, a3 controls the state of switch a203, and a4 controls the state of switch a 204. When the output port of the register outputs a high level, the switch controlled correspondingly is closed, otherwise, the switch controlled correspondingly is opened.
The output of the 4-bit successive approximation register is initially 1111, that is, all the transistors connected in series to the transistor MN202 are short-circuited. The correction process is divided into four steps, firstly, the highest bit a3 of the register is cleared, and the others are set to one. If Vdec jumps to low level at this time, indicating overcorrection, a3 is set to hold. If the level of Vdec is still high, it indicates that the correction is insufficient, and a3 is cleared and retained. Second, the register value clears a2, and a1 and a0 are set to one. If Vdec jumps to low level at this time, indicating overcorrection, a2 is set to hold. If Vdec is still low, the correction is insufficient, and a2 remains. Third, the register value clears a1 and a0 sets one. If Vdec is jumped to low level at this time, indicating that the correction is excessive, a1 is left after it is set. If the level of Vdec is still low, a1 is left if insufficient correction is indicated. Fourthly, when a0 is cleared to zero and the level of Vdec is changed to low level, the level is cleared and reserved. Otherwise a0 places a reservation.
After the calibration is finished, the switch k201 is closed, the switch k202 is opened, the switch k203 is opened, the switch k205 is closed, and the operational amplifier operates normally.
The above examples and illustrations do not limit the form and style of the present invention, and do not limit the present invention in any way, and it is obvious that various changes and modifications can be made to the circuit under the concept of the present invention, but they are within the protection of the present invention.

Claims (4)

1. A low-offset operational amplifier based on active load adjustment is characterized by comprising an operational amplifier module, a comparator module, a logic control unit and a four-bit successive approximation register; the in-phase input end of the comparator module is connected with the detection voltage Vdec of the operational amplifier module, and the reverse-phase input end of the comparator module is connected with VDD/2; the input end of the logic control unit is connected with the output end of the comparator module; the four-bit successive approximation comparison register is connected with the output end of the logic control unit, and the output ports of the four-bit successive approximation comparison register are four ports a0, a1, a2 and a3, and are used for adjusting the number of transistors connected in series on one side of an active load;
the operational amplifier module is divided into three parts: a gain stage, a detection stage and an output stage;
the gain stage comprises a PMOS transistor MP101, a PMOS transistor MP102, an NMOS transistor MN101, an NMOS transistor MN102, an NMOS transistor MN105, an NMOS transistor MN106, an NMOS transistor MN107, an NMOS transistor MN108, a current source Ib101, a switch k102, a switch k104, a switch a101, a switch a102, a switch a103 and a switch a 104; the non-inverting input end is connected with the grid electrode of the PMOS transistor MP102 through a switch k104, the inverting input end is connected with the grid electrode of the PMOS transistor MP101 through a switch k101, one end of the switch k102 is connected with the non-inverting input end, and the other end of the switch k102 is connected with the grid electrode of the PMOS transistor MP 101; the PMOS transistors MP101 and MP102 are input tubes of operational amplifiers, the sources thereof are connected with one end of a bias current source Ib101, and the other end of the current source Ib101 is connected with a power supply VDD; the NMOS transistor MN101 and the NMOS transistor MN102 form a current mirror load; the NMOS transistor MN101 is the source of the current mirror, the drain of the NMOS transistor MN is connected with the drain of the PMOS transistor MP101, and the source is grounded; the drain of the NMOS transistor MN102 is connected to the drain of the PMOS transistor MP102, and the drain of the NMOS transistor MN102 is also the output terminal of the gain stage; the gate of the NMOS transistor MN102 is connected with the drain of the NMOS transistor MN 101; the gates of the NMOS transistor MN105, the NMOS transistor MN106, the NMOS transistor MN107 and the NMOS transistor MN108 are connected, connected with the gate of the NMOS transistor MN101 and connected in series in a mode that the source and the drain are connected; the drain of the NMOS transistor MN105 is connected with the source of the NMOS transistor MN102, and the source of the NMOS transistor MN108 is grounded; the switch a101 is connected in parallel at the source-drain two ends of the NMOS transistor MN105, the switch a102 is connected in parallel at the source-drain two ends of the NMOS transistor MN106, the switch a103 is connected in parallel at the source-drain two ends of the NMOS transistor MN106, and the switch a104 is connected in parallel at the source-drain two ends of the NMOS transistor MN 107;
the detection stage comprises an NMOS transistor MN103 and a current source Ib 102; the output end of the gain stage is connected with the gate of the NMOS transistor MN103, namely the drain of the NMOS transistor MN102 is connected with the gate of the NMOS transistor MN 103; the NMOS transistor MN103 is biased by the current source Ib102, and has a drain connected to one end of the current source Ib102 and a source grounded; the other end of the current source Ib102 is connected with a power supply VDD; the drain of NMOS transistor MN103 outputs voltage signal Vdec;
the output stage comprises an NMOS transistor MN104, a current source Ib103, a switch k105 and a capacitor C101; the grid of the NMOS transistor MN104 is connected with the output end of the gain stage amplifier through a switch k105, namely the drain of the NMOS transistor MN102 is connected with one end of the switch k105, and the other end of the switch k105 is connected with the grid of the NMOS transistor MN 104; the drain electrode of the NMOS transistor MN104 is an output end VOUT, and the source electrode of the NMOS transistor MN is grounded; the current source Ib103 is used for biasing the NMOS transistor MN104, one end of the current source is connected with the drain electrode of the NMOS transistor MN104, and the other end of the current source is connected with a power supply VDD; the capacitor C101 is a Miller compensation capacitor, one end of the capacitor is connected with the drain electrode of the NMOS transistor MN104, and the other end of the capacitor is connected with the grid electrode of the NMOS transistor MN 104; the switch k103 has one end connected to the gate of the NMOS transistor MN104 and the other end connected to ground.
2. A low-offset operational amplifier based on active load adjustment is characterized by comprising an operational amplifier module, a comparator module, a logic control unit and a four-bit successive approximation register; the in-phase input end of the comparator module is connected with the detection voltage Vdec of the operational amplifier module, and the reverse-phase input end of the comparator module is connected with VDD/2; the input end of the logic control unit is connected with the output end of the comparator module; the four-bit successive approximation comparison register is connected with the output end of the logic control unit, and the output ports of the four-bit successive approximation comparison register are four ports a0, a1, a2 and a3, and are used for adjusting the number of transistors connected in series on one side of an active load;
the operational amplifier module is divided into three parts: a gain stage, a detection stage and an output stage;
the gain stage comprises a PMOS transistor MP201, a PMOS transistor MP202, a PMOS transistor MP203, a PMOS transistor MP204, a PMOS transistor MP205, a PMOS transistor MP206, an NMOS transistor MN201, an NMOS transistor MN202, an NMOS transistor MN203, an NMOS transistor MN204, an NMOS transistor MN207, an NMOS transistor MN208, an NMOS transistor MN209, an NMOS transistor MN210, a current source Ib201, a switch k202, a switch k204, a switch a201, a switch a202, a switch a203 and a switch a 204; the non-inverting input end is connected with the grid electrode of the PMOS transistor MP202 through a k204, and the inverting input end is connected with the grid electrode of the PMOS transistor MP201 through a k 201; one end of the switch k202 is connected with the non-inverting input end, and the other end is connected with the grid electrode of the PMOS transistor MP 201; the PMOS transistor MP201 and the PMOS transistor MP202 are input tubes of operational amplifiers, the sources thereof are connected with one end of a bias current source Ib201, and the other end of the bias current source Ib201 is connected with a power supply VDD; the drain of the PMOS transistor MP201 is connected with the drain of the NMOS transistor MN201, and the drain of the PMOS transistor MP202 is connected with the drain of the NMOS transistor MN 202; the drain of the NMOS transistor MN201 is connected to the source of the NMOS transistor MN203, and the source thereof is connected to ground; the drain of the NMOS transistor MN202 is connected with the source of the NMOS transistor MN 204; the NMOS transistor MN201 is connected to the gate of the NMOS transistor MN202, and biased by an external voltage Vb 1; the NMOS transistor MN203 is connected to the gate of the NMOS transistor MN204, and biased by an external voltage Vb 2; the PMOS transistors MP203, MP204, MP205 and MP206 form a cascode current mirror load; the drain of the PMOS transistor MP205 is connected to the drain of the NMOS transistor MN203, the drain of the PMOS transistor MP206 is connected to the drain of the NMOS transistor MN204, and the drain of the PMOS transistor MP206 is the output terminal of the gain stage amplifier; the source electrode of the PMOS transistor MP205 is connected with the drain electrode of the PMOS transistor MP203, the source electrode of the PMOS transistor MP206 is connected with the drain electrode of the PMOS transistor MP204, the PMOS transistor MP203 is connected with the source electrode of the PMOS transistor MP204 and the power supply VDD, the grid electrode of the PMOS transistor MP203 is connected with the drain electrode of the PMOS transistor MP 203; the PMOS transistor MP205 is connected with the grid electrode of the PMOS transistor MP206 and is connected with the drain electrode of the PMOS transistor MP 205; the NMOS transistors MN207, MN208, MN209, and MN210 are used to adjust the equivalent length of the NMOS transistor MN202, and the gates of these transistors are connected to the gate of the NMOS transistor MN201, and are connected in series in a manner that the sources and drains are connected to each other; the drain of the NMOS transistor MN207 is connected with the source of the NMOS transistor MN202, and the source of the NMOS transistor MN210 is grounded; the switch a201 is connected in parallel at the source-drain two ends of the NMOS transistor MN207, the switch a202 is connected in parallel at the source-drain two ends of the NMOS transistor MN208, the switch a203 is connected in parallel at the source-drain two ends of the NMOS transistor MN209, and the switch a204 is connected in parallel at the source-drain two ends of the NMOS transistor MN 210;
the detection stage comprises an NMOS transistor MN103 and a current source Ib 102; the output end of the gain stage is connected with the gate of the NMOS transistor MN103, namely the drain of the NMOS transistor MN102 is connected with the gate of the NMOS transistor MN 103; the NMOS transistor MN103 is biased by the current source Ib102, and has a drain connected to one end of the current source Ib102 and a source grounded; the other end of the current source Ib102 is connected with a power supply VDD; the drain of NMOS transistor MN103 outputs voltage signal Vdec;
the output stage comprises an NMOS transistor MN104, a current source Ib103, a switch k105 and a capacitor C101; the grid of the NMOS transistor MN104 is connected with the output end of the gain stage amplifier through a switch k105, namely the drain of the NMOS transistor MN102 is connected with one end of the switch k105, and the other end of the switch k105 is connected with the grid of the NMOS transistor MN 104; the drain electrode of the NMOS transistor MN104 is an output end VOUT, and the source electrode of the NMOS transistor MN is grounded; the current source Ib103 is used for biasing the NMOS transistor MN104, one end of the current source is connected with the drain electrode of the NMOS transistor MN104, and the other end of the current source is connected with a power supply VDD; the capacitor C101 is a Miller compensation capacitor, one end of the capacitor is connected with the drain electrode of the NMOS transistor MN104, and the other end of the capacitor is connected with the grid electrode of the NMOS transistor MN 104; the switch k103 has one end connected to the gate of the NMOS transistor MN104 and the other end connected to ground.
3. The operational amplifier of claim 1, wherein the NMOS transistors MN105, MN106, MN107 and MN108 are used to adjust the equivalent length of the NMOS transistor MN 102.
4. The operational amplifier of claim 1, wherein the logic control unit outputs k1, k2, k3 and k4 control the internal switch states of the operational amplifier for switching the operational mode of the operational amplifier.
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