CN107320893B - Device with fire control switch conversion monitoring and recording functions - Google Patents
Device with fire control switch conversion monitoring and recording functions Download PDFInfo
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- CN107320893B CN107320893B CN201710701177.8A CN201710701177A CN107320893B CN 107320893 B CN107320893 B CN 107320893B CN 201710701177 A CN201710701177 A CN 201710701177A CN 107320893 B CN107320893 B CN 107320893B
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- 238000013500 data storage Methods 0.000 claims abstract description 11
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Abstract
The device with the functions of switching, monitoring and recording the fire control switch comprises a processor circuit, a two-bus communication circuit connected with the processor circuit, a monitoring switch input circuit, an acousto-optic alarm circuit for field fault alarm, an internal power supply switching circuit for providing a required power supply for the device, a GPRS transmission circuit, a data storage circuit, a 485 communication circuit for reading data on site, a system clock circuit for providing accurate time record for a system and an IP address coding circuit. The invention provides a device with functions of monitoring and recording the switching of a fire control hand/automatic switch, which monitors the control mode of a fire facility in real time and automatically records the times and time of the manual/automatic switching of the fire facility.
Description
Technical Field
The invention relates to a fire control system, in particular to a device with functions of switching, monitoring and recording a fire control manual/automatic switch.
Background
According to the general technical standard of fire-fighting control room and the fire-fighting safety management system, in a quasi-working state, the power distribution cabinets of the water fire-extinguishing system, the smoke-preventing and exhausting system and the electric fire-preventing separation facility are strictly forbidden to be in a manual control state. However, for various reasons, operators of some units and control rooms put the switch boards in the manual control state for a long time, and only switch to the automatic control state when dealing with the inspection of related departments, so that the automatic effect of the automatic system cannot be achieved.
Disclosure of Invention
In view of the above problems, the present invention provides a device with fire control manual/automatic switch switching monitoring and recording functions.
In order to solve the problems, the invention adopts the technical scheme that: the device with the functions of switching, monitoring and recording the fire control switch comprises a processor circuit (U8), a two-bus communication circuit connected with the processor circuit (U8), a monitoring switch input circuit, an audible and visual alarm circuit for site fault alarm, an internal power supply switching circuit for alarming site faults through a light emitting diode and a buzzer and providing required power for the device, a GPRS transmission circuit (U4), a data storage circuit, a 485 communication circuit for reading data on site, a system clock circuit for providing accurate time recording for a system and an IP address coding circuit for providing site IP address arrangement for the device, wherein the two-bus communication circuit is in signal communication connection with an external fire control system and keeps data exchange, and the monitoring switch input circuit is in signal connection with a manual/automatic converter switching value input signal of the fire control system, the GPRS transmission circuit (U4) interacts with the fire-fighting headquarters information through satellite data transmission.
The processor circuit (U8) includes a power-on reset and program debug circuit
A pin and a PWM6 pin, AN XTAL pin and AN exteal pin connected to a clock circuit of a processor, a PWM4 pin, a PWM5 pin, AN IOC0 pin-IOC 5 pin, a PS2 pin and a PS3 pin connected to a GPRS transmission circuit (U4), AN IOC6 pin and AN IOC7 pin connected to a data storage circuit, a PM0 pin, a PM1 pin and a PWM3 pin connected to a 485 communication circuit, AN ECLK pin and a PS6 pin connected to a system clock circuit, AN0 pin-AN 3 pin, AN8 pin-AN 11 pin connected to AN acousto-optic alarm circuit, AN5 pin-AN 7 pin connected to AN input circuit of a monitor switch, a PS0 pin and a PS0 pin connected to a two bus communication circuit or a two bus signal isolation circuit, a VDDXRA pin and a pin connected to a power supply terminal VCC, a vsvss pin and ground pin, a sx 0 pin, a PWM0 pin, a bsd 0 pin, a PWM0 pin and a pin connected to a power supply terminal, The PS4 pin and the PS5 pin are suspended;
the power-on reset and programming debugging circuit comprises a BDM debugger (JP1), wherein a BDM debugger (JP1) BKGD pin is connected to a PWM6 pin of a processor circuit (U8) and passes through a second pinA twenty-four resistor (R24) is connected to a VCC power supply terminal, a VDD pin is connected to the VCC power supply terminal, a BDM debugger (JP1) RESET pin is connected to the VCC power supply terminal through a twenty-sixth resistor (R26), the RESET pin is connected to the ground through a twenty-fifth resistor (R25) and a seventeenth capacitor (C17) in series, and the common end of the twenty-fifth resistor (R25) and the seventeenth capacitor (C17) is connected to a processor circuit (U8)
The pin, the NC pin and the GND pin are grounded, and the VFP pin is suspended;
the processor clock circuit comprises a crystal oscillator (XT1), two ends of the crystal oscillator (XT1) are respectively connected to an XTAL pin and an EXTAL pin of the processor circuit (U8), and two ends of the crystal oscillator (XT1) are grounded through an eighteenth capacitor (C18) and a nineteenth capacitor (C19);
the power supply filter capacitor comprises a twentieth capacitor and a twentieth capacitor which are connected between a VCC power supply end and the power supply ground in parallel.
The two bus communication circuits are connected with the processor circuit (U8) through two bus signal isolation circuits;
the two bus communication circuits comprise a bus master station communication interface chip (U1) and a non-polar bidirectional circuit, wherein the non-polar bidirectional circuit comprises a second diode (D2) and a third diode (D3) which are connected in series, and a fourth diode (D4) and a fifth diode (D5) which are connected in series, the cathode of the second diode (D2) is connected with the cathode of the fourth diode (D4), the anode of the second diode (D2) is connected with the cathode of the third diode (D3), the anode of the fourth diode (D4) is connected with the cathode of the fifth diode (D5), and the anode of the third diode (D3) is connected with the anode of the fifth diode (D5);
the BUS master station communication interface chip (U1) SIN pin is connected to the common end of the cathode of the second diode (D2), the cathode of the fourth diode (D4) and the anode of the sixth diode (D6), the common end of the anode of the second diode (D2) and the cathode of the third diode (D3) is connected to the first BUS signal input end (BUS1), the common end of the anode of the fourth diode (D4) and the cathode of the fifth diode (D5) is connected to the second BUS signal input end (BUS2), the common end of the first BUS signal input end (BUS1) and the second BUS signal input end (BUS2) is connected in parallel with a first voltage stabilizing diode (D1), a first capacitor (C1) and a second capacitor (C2) in series, the common end of the first capacitor (C1) and the second capacitor (C2) is connected to the ground, the first voltage stabilizing protection diode is used for the BUS entrance, the first capacitor and the second capacitor are used for matching with the first voltage stabilizing diode for processing the BUS signal, the bus master station communication interface chip (U1) VCC pin is connected to the cathode of a sixth diode (D6) through a first resistor (R1), a third capacitor (C3) and a fourth capacitor (C4) are connected in parallel between the VCC pin and the GND pin of the bus master station communication interface chip (U1), the cathode of the third capacitor (C3) and the GND pin are grounded through signals, the VOUT pin and the SEL pin are connected to a 5V power supply and are grounded through a fifth capacitor (C5) through signals, the RXD pin is connected to the PS0 pin of the processor circuit (U8) through a second bus signal isolation circuit or a sixth resistor, if signal isolation is needed, the second bus signal isolation circuit is used, if signal isolation is not needed, the sixth resistor is used, the TXD pin is connected to the PS1 pin of the processor circuit (U8) through the second bus signal isolation circuit or the seventh resistor, suspending an NC pin;
the two-bus signal isolation circuit comprises a first optical coupler (U2) and a second optical coupler (U3), wherein a first optical coupler (U2) AN pin is connected to a 5V power supply, a second optical coupler (U3) VCC pin and AN EN pin, a first optical coupler (U2) CATH pin is connected to a bus master station communication interface chip (U1) RXD pin through a second resistor (R2), the first optical coupler (U2) VCC pin and the EN pin are connected to a VCC power supply end and a second optical coupler (U3) AN pin, a first optical coupler (U2) OUT pin is connected to a processor circuit (U8) PS0 pin and is connected to a first optical coupler (U2) VCC pin and AN EN pin through a fourth resistor (R4), a first optical coupler (U2) GND pin is grounded and is connected to a first optical coupler (U2) VCC pin and AN NC 1) pin through a seventh capacitor (C7), the two bus signals are input by an SIN pin, demodulated by a bus master station communication interface chip, output by an RXD pin to form a TTL signal, and transmitted to a processor circuit by a first optical coupler;
the OUT pin of a second optical coupler (U3) is connected to a TXD pin of a bus master station communication interface chip (U1) and is connected to a VCC pin and an EN pin of the second optical coupler (U3) through a third resistor (R3), a GND pin of the second optical coupler (U3) is grounded in signal and is connected to a 5V power supply through a sixth capacitor (C6), a CATH pin of the second optical coupler (U3) is connected to a PS1 pin of a processor circuit (U8) through a fifth resistor (R5), an NC pin and an NC1 pin are suspended, a TTL signal output by the processor circuit is input to the bus master station communication interface chip through the TXD pin after passing through the second optical coupler, and a modulation signal is generated on a bus.
The monitoring switch input circuit comprises a third optical coupler (U5), a first non-polar switch terminal (Z1) of a fire fighting control system manual/automatic converter is connected with a CATH pin of the third optical coupler (U5) through a twentieth resistor (R20), AN AN pin is connected with a VDD power supply terminal, the fire control system manual/automatic converter comprises a second nonpolar switch terminal (Z2) of the fire control system manual/automatic converter and a signal ground, a VCC pin and AN EN pin are connected to a VCC power supply end, AN OUT pin is connected to a processor circuit (U8) AN4 pin and is connected to a VCC pin and AN EN pin of a third optical coupler (U5) through a twenty-first resistor (R21), a GND pin is grounded and is connected to the VCC pin and the EN pin through a twelfth capacitor (C12), the NC pin and the NC1 pin are suspended, and Z1 and Z2 are used for inputting a nonpolar switch signal of the manual/automatic converter and transmitting the signal to the processor circuit after being isolated by a third optical coupler signal;
the third optical coupler plays a role in level conversion and signal isolation, if signal isolation is not needed, the monitoring switch input circuit can be connected between a VDD power supply end and a VCC power supply end through a twenty-second resistor, a twenty-third resistor is connected between a signal ground and a power ground, a switch signal isolation function is short-circuited, the monitoring switch input circuit only plays a role in level conversion, and the power VDD is obtained through the DC-DC power circuit module.
The acousto-optic alarm circuit comprises a buzzer alarm circuit and AN indicator lamp circuit, the buzzer alarm circuit comprises a buzzer (M1), the pin IN + of the buzzer (M1) is connected to the VCC power supply end, the pin IN1 is connected to the collector of a second triode (Q2), the power supply of the emitter of the second triode (Q2) is grounded, the base of the second triode (Q2) is connected to the pin AN5 of the processor circuit (U8) through a sixteenth resistor (R16), and a seventeenth resistor (R17) and a thirty-first capacitor (C31) are connected between the base of the second triode (Q2) and the power ground IN parallel;
the indicator light circuit comprises a first light emitting diode (D7) and a second light emitting diode (D8) which are respectively used as a working power indicator light and AN alarm indicator light, wherein the anode of the first light emitting diode (D7) and the anode of the second light emitting diode (D8) are connected to a VCC power supply end, the cathode of the first light emitting diode (D7) is connected to a pin AN7 of a processor circuit (U8) through AN eighteenth resistor (R18), and the cathode of the second light emitting diode (D8) is connected to a pin AN6 of the processor circuit (U8) through a nineteenth resistor (R19).
The internal power conversion circuit comprises a system power circuit and a signal isolation power circuit, wherein the system power circuit comprises an integrated voltage stabilizing circuit (U6), an IN pin of the integrated voltage stabilizing circuit (U6) is connected to a 12V power supply, the cathode of a ninth voltage stabilizing diode (D9), the anode of a thirteenth capacitor (C13) and one end of a fourteenth capacitor (C14) are connected to the IN pin, the anode of the ninth voltage stabilizing diode (D9), the cathode of a thirteenth capacitor (C13) and the other end of the fourteenth capacitor (C14) are grounded, an OUT pin is output to a VCC power end through a first inductor (L1), an FB pin is connected to the VCC power end, the GND pin and an ON/OFF pin are grounded, the cathode of a tenth voltage stabilizing diode (D10) is connected to the OUT pin, the anode of a fifteenth capacitor (C15) and one end of a sixteenth capacitor (C16) are connected to the VCC power end, the anode of the tenth voltage stabilizing diode (D10), the 12) is connected to the 12V power supply, and the anode of the fourteenth capacitor (C3552) is connected to the VCC power supply end, The negative electrode of the fifteenth capacitor (C15) and the power supply at the other end of the sixteenth capacitor (C16) are grounded, and the system power supply circuit converts a 12V power supply input by the power supply interface into a 5V power supply required by the system circuit;
the signal isolation power supply circuit comprises a DC-DC power supply circuit (U7), a VIN + pin of the DC-DC power supply circuit (U7) is connected to a VCC power supply end, a VOUT + pin is connected to a VDD power supply end, a VIN-pin is grounded, a VOUT-pin is grounded through a signal, and the DC-DC power supply circuit generates another set of 5V power supplies which are completely isolated electrically through a 5V power supply of a system and is used as an isolation power supply for nonpolar input.
The pin LINK1 and the pin LINK2 of the GPRS transmission circuit (U4) are respectively connected to the pin IOC0 and the pin IOC1 of the processor circuit (U8), the pin LINK4 and the pin LINK4 of the GPRS transmission circuit (U4) are respectively connected to the pin IOC4 and the pin IOC4 of the processor circuit (U4) through an eighth resistor (R4) and a ninth resistor (R4), the pin UTXD 4 and the pin URXD 4 of the GPRS transmission circuit (U4) are respectively connected to the pin PS4 and the pin PS4 of the processor circuit (U4), the pin WORD of the GPRS transmission circuit (U4) is connected to the pin PWM4 of the processor circuit (U4), the pin WKEY of the GPRS transmission circuit (U4) is connected to the pin PS4 of the first field effect transistor (Q4), the drain electrode of the first field effect transistor (Q4) is connected to the pin LOU 4 of the processor circuit (U4), the pin RERK 4) is connected to the pin of the RESET circuit (U4) and the RESET circuit (RE 4) is connected to the pin of the first field effect transistor (RE GND) of the RESET circuit (U4), a pin RE485_ EN of a GPRS transmission circuit (U4) is connected to a pin IOC5 of a processor circuit (U8) through an eleventh resistor (R11), a pin LINK of the GPRS transmission circuit (U4) is connected to a pin IOC4 of a processor circuit (U8), a pin VCAP of the GPRS transmission circuit (U4) is connected to the anode of an eighth capacitor (C8), pins DC5-18V are connected to a VCC power supply end and the anode of a ninth capacitor (C9), the cathode of the eighth capacitor (C8) and the cathode of the ninth capacitor (C9) are grounded, and a pin NC1, a pin NC2, a pin RCV _ N, a pin RCV _ P, a pin MIC _ N and a pin MIC _ P are suspended;
the RESET circuit comprises a first key (SW1), one end of the first key (SW1) is connected to a RESET pin of a GPRS transmission circuit (U4), is connected to a VCC power supply end through a twelfth resistor (R12) and is grounded through a tenth capacitor (C10), and the other end of the first key (SW1) is grounded through a thirteenth resistor (R13);
the data recovery circuit comprises a second key (SW2), one end of the second key (SW2) is connected to a RELOAD pin of a GPRS transmission circuit (U4), is connected to a VCC power supply end through a fourteenth resistor (R14) and is grounded through an eleventh capacitor (C11), and the other end of the second key (SW2) is grounded through a fifteenth resistor (R15).
The data storage circuit comprises a programmable read-only memory (U9), a pin A0-A2 of the programmable read-only memory (U9) is grounded through a twenty-seventh resistor (R27), a pin WP is grounded through a twenty-eighteen resistor (R28), a pin VCC is connected to a VCC power supply end and is grounded through a twenty-twelve capacitor (C22), a pin SCL is connected to a pin IOC6 of a processor circuit (U8) and is connected to the VCC power supply end through a twenty-ninth resistor (R29), a pin SDA is connected to a pin IOC7 of the processor circuit (U8) and is connected to the VCC power supply end through a thirtieth resistor (R30), and the pin GND is grounded. And meanwhile, recording and accumulating the data of the device, such as power failure time, power-on time, power failure times and the like, and storing the data for a long time for reading. The stored data can be read on site in a communication serial port mode, and can also be transmitted through a two-bus and GPRS.
The 485 communication circuit is used for reading various data on site and comprises a 485 communication chip (U11) and a D-type interface (J3), wherein a pin of RO of the 485 communication chip (U11) is connected to a pin of PM0 of a processor circuit (U8) and is connected to a cathode of a fourteenth light emitting diode (D14) through a thirty-fourth resistor (R34), an anode of the fourteenth light emitting diode (D14) is connected to a VCC power supply terminal, a DI pin is connected to a pin of PM1 of the processor circuit (U8) and is connected to a cathode of a thirteenth light emitting diode (D13) through a thirty-third resistor (R33), an anode of the thirteenth light emitting diode (D13) is connected to the VCC power supply terminal, a thirty-third resistor (R33) and a thirty-fourth resistor (R34) are current limiting resistors, the thirteen light indication of the thirteenth light emitting diode (D13) and the fourteenth light emitting diode (D14) is light indication when in communication, and represents the reading state of the data,
the pin and the DE pin are connected to a PWM3 pin of a processor circuit (U8), the pin A and the pin B are respectively connected to a TDA-/Y pin and an RDB +/B pin of a D-type interface (J3), the VCC pin is connected to a VCC power supply end and is grounded through a twenty-four capacitor (C24), the twenty-four capacitor (C24) is a filter capacitor, the GND pin is grounded, and other pins of the D-type interface (J3) are suspended.
The system clock circuit provides accurate time record for the system, is provided with a battery, has an automatic access function through a circuit, does not supply power to the battery in a normal power-on state, automatically accesses the battery in a power-off state, keeps the clock running normally in a power-off period, comprises a clock chip (U10), and can adjust the timeThe programming mode is adopted for writing and can also be modified through a serial port communication mode, a pin X1 and a pin X2 of a clock chip (U10) are respectively connected to two ends of a clock crystal oscillator (Y2), Y2 is a 32.768KHz clock crystal oscillator and provides accurate clock signals for the chip, a pin SCL is connected to a pin PS6 of a processor circuit (U8) and is connected to a VCC power supply end through a thirty-one resistor (R31), a pin SDA is connected to a pin ECLK of the processor circuit (U8) and is connected to VCC through a thirty-two resistor (R32), the VCC power supply end is respectively connected to an eleventh diode (D11) and a cathode of a twelfth diode (D12), an anode of the eleventh diode (D11) is connected to a positive polarity end of a battery (P1), a negative polarity end of the battery (P1) is grounded, P1 is a power supply circuit of the clock chip, the power supply is used for supplying power to the clock chip through the twelfth diode (D12) during normal power-on period, and the voltage VCC power supply (5V) is higher than the voltage (P1) of the battery (P1), the battery (P1) is not powered; when the device is powered off, the battery (P1) supplies power to the clock chip, the holding time is uninterrupted, the anode of the twelfth diode (D12) is connected to the VCC power supply end, the VCC pin is grounded through the second thirteen capacitor (C23), the twenty-third capacitor (C23) is a filter capacitor, the GND pin is grounded,
pin and
the pins are suspended.
The IP address coding circuit comprises a toggle switch (SW3), pins of the toggle switch (SW3) are respectively connected to AN AN0 pin-AN 3 pin and AN AN8 pin-AN 11 pin of the processor circuit (U8), a group of coded addresses are provided for the device, the coded addresses are 0-255, and IP address arrangement can be conveniently carried out on the device on site.
The first input end of the two bus signals, the second input end of the two bus signals, the first non-polarity switch end and the second non-polarity switch end of the fire control system manual/automatic converter are connected with the monitoring device through input interfaces, and the input interfaces are used as the input interfaces of the two bus signals of the consumption control system and the non-polarity switch signals of the manual/automatic converter; the external power supply provides electric energy for the monitoring device through a power interface, and the power interface is used as an input interface of a 12V direct-current power supply.
The invention provides a device with functions of monitoring and recording the switching of a fire control manual/automatic switch, which reads signals on the manual/automatic switch in a control cabinet, sends the signals of an automatic control state to a fire control room through a traditional switch signal and a two-bus means, and can remotely transmit the signals to a public security fire department or a fire control remote monitoring center for real-time monitoring through a GPRS remote transmission device, so as to monitor the control mode of fire-fighting facilities in real time and urge a unit to enable the automatic fire-fighting facilities to be in an automatic state, thereby ensuring that a fire control system plays the practical role. Meanwhile, the device can automatically record the times and time of manual/automatic switching of the fire-fighting facilities, read corresponding data in a serial port communication mode, transmit the corresponding data to the control cabinet and the fire-fighting headquarters main console in a two-bus and GPRS remote transmission mode, record and accumulate the power failure time, power-on time, power failure times and other data of the device, remotely transmit the data to the control cabinet and the fire-fighting headquarters main console as required, and read the data on site during patrol.
Drawings
FIG. 1 is a functional block diagram;
FIG. 2 is a processor circuit;
FIG. 3 is a power-on reset and program debug circuit;
FIG. 4 is a processor clock circuit;
FIG. 5 is a diagram of a two bus communication circuit;
FIG. 6 is a diagram of two bus signal isolation circuits;
FIG. 7 is a monitoring switch input circuit;
FIG. 8 is a buzzer warning circuit;
FIG. 9 is an indicator light circuit;
FIG. 10 is a system power supply circuit;
FIG. 11 is a signal isolation power supply circuit;
fig. 12 is a GPRS transmission circuit;
FIG. 13 is a data storage circuit;
FIG. 14 is a 485 communication circuit;
FIG. 15 is a system clock circuit;
FIG. 16 is an IP address encoding circuit;
FIG. 17 is an input interface;
fig. 18 is a power interface.
Detailed Description
As shown in figure 1, the device with the functions of switching, monitoring and recording the fire control switch comprises a processor circuit (U8), a two-bus communication circuit connected with the processor circuit (U8), a monitoring switch input circuit, an audible and visual alarm circuit for site fault alarm, an internal power conversion circuit for alarming site faults through a light emitting diode and a buzzer and providing required power for the device, a system power circuit and a signal isolation power circuit of the device are provided with two paths of required power, a GPRS transmission circuit (U4), a data storage circuit, a 485 communication circuit for reading data on site, a system clock circuit for providing accurate time recording for the system and an IP address coding circuit for providing site IP address arrangement for the device, the two-bus communication circuit is in signal communication connection with an external fire control system to keep data exchange, the monitoring switch input circuit is in signal connection with the switching value input signal of a manual/automatic converter of the fire control system, the GPRS transmission circuit (U4) interacts with the fire-fighting headquarters information through satellite data transmission.
As shown in FIG. 2, the processor circuit U8 adopts a FREESCALE series microprocessor S9S12G64CALL _48, a pin 48, a package LQFP48, 5V power supply, 3-path serial port communication interface, 24-path I/O input/output port, and the processor circuit U8 includes a power-on reset and programming debug circuit connected with the power-on reset and programming debug circuit
Pin and PWM6 pin, XTAL pin and extel pin connected to processor clock circuit, PWM4 pin, PWM5 pin, IOC0 pin-IOC 5 pin, PS2 pin and PS3 pin connected to GPRS transmission circuit (U4), IOC6 pin and IOC7 pin connected to data storage circuit, PM0 pin, PM1 pin and PWM3 pin connected to 485 communication circuit, ECLK pin and PS6 pin connected to system clock circuit, AN0 pin-AN 3 pin, AN8 pin-AN 11 pin connected to IP address coding circuitAN AN5 pin-AN 7 pin connected with the audible and visual alarm circuit, AN AN4 pin connected with the input circuit of the monitoring switch, a PS0 pin and a PS1 pin connected with the two bus communication circuits or the two bus signal isolation circuits, a VDDXRA pin and a VDDA pin are connected to a VCC power supply end, a VSSX pin, a VSS pin and a VSSA pin are grounded, a TEST pin, a PWM7 pin, a BKDD pin, a PWM 0-PWM 2 pin, a PS4 pin and a PS5 pin are suspended;
as shown in fig. 3, the power-on RESET and programming debugging circuit includes a BDM debugger (JP1), a BDM debugger (JP1) BKGD pin is connected to a PWM6 pin of the processor circuit (U8) and to a VCC power supply terminal through a twenty-fourth resistor (R24), a VDD pin is connected to the VCC power supply terminal, a RESET pin of the BDM debugger (JP1) is connected to the VCC power supply terminal through a twenty-sixth resistor (R26), the RESET pin is connected to ground through a twenty-fifth resistor (R25) and a seventeenth capacitor (C17) in series, and a common terminal of the twenty-fifth resistor (R25) and the seventeenth capacitor (C17) is connected to the processor circuit (U8)
The pin, the NC pin and the GND pin are grounded, and the VFP pin is suspended;
as shown in fig. 4, the processor clock circuit includes a crystal oscillator (XT1), two terminals of the crystal oscillator (XT1) are respectively connected to the XTAL pin and the extetal pin of the processor circuit (U8), and two terminals of the crystal oscillator (XT1) are grounded via an eighteenth capacitor (C18) and a nineteenth capacitor (C19);
the power supply filter capacitor comprises a twentieth capacitor and a twentieth capacitor which are connected between a VCC power supply end and the power supply ground in parallel.
The two bus communication circuits are connected with the processor circuit (U8) through two bus signal isolation circuits;
as shown in fig. 5, the two bus communication circuits include a bus master station communication interface chip (U1) and a non-polar bidirectional circuit, the non-polar bidirectional circuit includes a second diode (D2) and a third diode (D3) connected in series, a fourth diode (D4) and a fifth diode (D5) connected in series, and the cathode of the second diode (D2) is connected to the cathode of the fourth diode (D4), the anode of the second diode (D2) is connected to the cathode of the third diode (D3), the anode of the fourth diode (D4) is connected to the cathode of the fifth diode (D5), and the anode of the third diode (D3) is connected to the anode of the fifth diode (D5);
the BUS master station communication interface chip (U1) SIN pin is connected to the common end of the cathode of the second diode (D2), the cathode of the fourth diode (D4) and the anode of the sixth diode (D6), the common end of the anode of the second diode (D2) and the cathode of the third diode (D3) is connected to the first BUS signal input end (BUS1), the common end of the anode of the fourth diode (D4) and the cathode of the fifth diode (D5) is connected to the second BUS signal input end (BUS2), the common end of the first BUS signal input end (BUS1) and the second BUS signal input end (BUS2) is connected in parallel with a first voltage stabilizing diode (D1), a first capacitor (C1) and a second capacitor (C2) in series, the common end of the first capacitor (C1) and the second capacitor (C2) is connected to the ground, the first voltage stabilizing protection diode is used for the BUS entrance, the first capacitor and the second capacitor are used for matching with the first voltage stabilizing diode for processing the BUS signal, the bus master station communication interface chip (U1) VCC pin is connected to the cathode of a sixth diode (D6) through a first resistor (R1), a third capacitor (C3) and a fourth capacitor (C4) are connected in parallel between the VCC pin and the GND pin of the bus master station communication interface chip (U1), the cathode of the third capacitor (C3) and the GND pin are grounded through signals, the VOUT pin and the SEL pin are connected to a 5V power supply and are grounded through a fifth capacitor (C5) through signals, the RXD pin is connected to the PS0 pin of the processor circuit (U8) through a second bus signal isolation circuit or a sixth resistor, if signal isolation is needed, the second bus signal isolation circuit is used, if signal isolation is not needed, the sixth resistor is used, the TXD pin is connected to the PS1 pin of the processor circuit (U8) through the second bus signal isolation circuit or the seventh resistor, suspending an NC pin;
as shown in fig. 6, the two-bus signal isolating circuit includes a first optocoupler (U2) and a second optocoupler (U3), wherein a first optocoupler (U2) AN pin is connected to the 5V power supply and a second optocoupler (U3) VCC pin and AN EN pin, a first optocoupler (U2) CATH pin is connected to the bus master station communication interface chip (U1) RXD pin through a second resistor (R2), a first optocoupler (U2) VCC pin and AN EN pin are connected to the VCC power supply terminal and a second optocoupler (U3) AN pin, a first optocoupler (U2) OUT pin is connected to the processor circuit (U8) PS0 pin and to the first optocoupler (U2) VCC pin and AN EN pin through a fourth resistor (R4), a first optocoupler (U2) pin is connected to the power supply ground and to the first optocoupler (U2) VCC pin and the NC pin 1 through a seventh capacitor (C7), the two bus signals are input by an SIN pin, demodulated by a bus master station communication interface chip, output by an RXD pin to form a TTL signal, and transmitted to a processor circuit by a first optical coupler;
the OUT pin of a second optical coupler (U3) is connected to a TXD pin of a bus master station communication interface chip (U1) and is connected to a VCC pin and an EN pin of the second optical coupler (U3) through a third resistor (R3), a GND pin of the second optical coupler (U3) is grounded in signal and is connected to a 5V power supply through a sixth capacitor (C6), a CATH pin of the second optical coupler (U3) is connected to a PS1 pin of a processor circuit (U8) through a fifth resistor (R5), an NC pin and an NC1 pin are suspended, a TTL signal output by the processor circuit is input to the bus master station communication interface chip through the TXD pin after passing through the second optical coupler, and a modulation signal is generated on a bus.
As shown in fig. 7, the monitoring switch input circuit includes a third photo coupler (U5), a third photo coupler (U5) CATH pin is connected to a first non-polarity switch terminal (Z1) of the fire fighting control system manual/automatic converter through a twentieth resistor (R20), AN pin is connected to a VDD power supply terminal, the fire control system manual/automatic converter comprises a second nonpolar switch terminal (Z2) of the fire control system manual/automatic converter and a signal ground, a VCC pin and AN EN pin are connected to a VCC power supply end, AN OUT pin is connected to a processor circuit (U8) AN4 pin and is connected to a VCC pin and AN EN pin of a third optical coupler (U5) through a twenty-first resistor (R21), a GND pin is grounded and is connected to the VCC pin and the EN pin through a twelfth capacitor (C12), the NC pin and the NC1 pin are suspended, and Z1 and Z2 are used for inputting a nonpolar switch signal of the manual/automatic converter and transmitting the signal to the processor circuit after being isolated by a third optical coupler signal;
the third optical coupler plays a role in level conversion and signal isolation, if signal isolation is not needed, the monitoring switch input circuit can be connected between a VDD power supply end and a VCC power supply end through a twenty-second resistor, a twenty-third resistor is connected between a signal ground and a power ground, a switch signal isolation function is short-circuited, the monitoring switch input circuit only plays a role in level conversion, and the power VDD is obtained through the DC-DC power circuit module.
As shown IN fig. 8, the sound and light alarm circuit comprises a buzzer alarm circuit and AN indicator light circuit, the buzzer alarm circuit comprises a buzzer (M1), a pin IN + of the buzzer (M1) is connected to a VCC power supply end, a pin IN1 is connected to a collector of a second triode (Q2), a power supply of AN emitter of the second triode (Q2) is grounded, a base of the second triode (Q2) is connected to a pin AN5 of the processor circuit (U8) through a sixteenth resistor (R16), and a seventeenth resistor (R17) and a thirty-first capacitor (C31) are connected IN parallel between the base of the second triode (Q2) and the power ground;
as shown in fig. 9, the indicator light circuit includes a first light emitting diode (D7) and a second light emitting diode (D8) as AN operating power indicator light and AN alarm indicator light, respectively, AN anode of the first light emitting diode (D7) and AN anode of the second light emitting diode (D8) are connected to a VCC power terminal, a cathode of the first light emitting diode (D7) is connected to a pin AN7 of the processor circuit (U8) through AN eighteenth resistor (R18), and a cathode of the second light emitting diode (D8) is connected to a pin AN6 of the processor circuit (U8) through a nineteenth resistor (R19).
As shown IN fig. 10, the internal power conversion circuit includes a system power circuit and a signal isolation power circuit, wherein the system power circuit includes an integrated voltage regulator circuit (U6), an IN pin of the integrated voltage regulator circuit (U6) is connected to a 12V power supply, a cathode of a ninth zener diode (D9), an anode of a thirteenth capacitor (C13), and one end of a fourteenth capacitor (C14) are connected to the IN pin, an anode of the ninth zener diode (D9), a cathode of the thirteenth capacitor (C13), and the other end of the fourteenth capacitor (C14) are grounded, an OUT pin is output to a VCC power terminal through a first inductor (L1), the FB pin is connected to the VCC power terminal, the GND pin and an ON/OFF power supply are grounded, a cathode of a tenth zener diode (D10) is connected to the OUT pin, an anode of the fifteenth capacitor (C15) and one end of a sixteenth capacitor (C16) are connected to the VCC power terminal, an anode of the tenth zener diode (D10), an anode of the thirteenth capacitor (D10), a voltage regulator circuit is connected to the VCC power terminal, a voltage regulator circuit is connected to the 12V power supply terminal, and a voltage regulator circuit is connected to the second capacitor (b) is connected to the ground, and a voltage regulator circuit is connected to the second regulator circuit, The negative electrode of the fifteenth capacitor (C15) and the power supply at the other end of the sixteenth capacitor (C16) are grounded, and the system power supply circuit converts a 12V power supply input by the power supply interface into a 5V power supply required by the system circuit;
as shown in fig. 11, the signal isolation power circuit includes a DC-DC power circuit (U7), a VIN + pin of the DC-DC power circuit (U7) is connected to a VCC power terminal, a VOUT + pin is connected to a VDD power terminal, the VIN-pin is grounded, and the VOUT-pin is grounded, and the DC-DC power circuit generates another set of 5V power sources that are electrically and completely isolated by a 5V power source of the system, and is used as an isolated power source with a non-polar input.
As shown in fig. 12, the LINK1 pin and LINK2 pin of the GPRS transmission circuit (U4) are connected to the IOC0 pin and IOC1 pin of the processor circuit (U8), the LINK4 pin and LINK4 pin of the GPRS transmission circuit (U4) are connected to the IOC4 pin and IOC4 pin of the processor circuit (U4) through an eighth resistor (R4) and a ninth resistor (R4), the UTXD 4 pin and URXD 4 pin of the GPRS transmission circuit (U4) are connected to the PS4 pin and PS4 pin of the processor circuit (U4), the WORK pin of the GPRS transmission circuit (U4) is connected to the PWM4 pin of the processor circuit (U4), the POWKEY pin of the GPRS transmission circuit (U4) is connected to the drain of the first field effect transistor (Q4), the gate of the GPRS transmission circuit (U4) is connected to the load pin of the processor circuit (U4) and the RESET circuit (U4) is connected to the RESET power supply pin (RESET circuit (RESET) and the RESET circuit (RESET pin of the RESET circuit (U4) and RESET circuit (RESET circuit) is connected to the RESET pin of the RESET power supply circuit (RESET pin of the RESET circuit (U4), a pin RE485_ EN of a GPRS transmission circuit (U4) is connected to a pin IOC5 of a processor circuit (U8) through an eleventh resistor (R11), a pin LINK of the GPRS transmission circuit (U4) is connected to a pin IOC4 of a processor circuit (U8), a pin VCAP of the GPRS transmission circuit (U4) is connected to the anode of an eighth capacitor (C8), pins DC5-18V are connected to a VCC power supply end and the anode of a ninth capacitor (C9), the cathode of the eighth capacitor (C8) and the cathode of the ninth capacitor (C9) are grounded, and a pin NC1, a pin NC2, a pin RCV _ N, a pin RCV _ P, a pin MIC _ N and a pin MIC _ P are suspended;
the RESET circuit comprises a first key (SW1), one end of the first key (SW1) is connected to a RESET pin of a GPRS transmission circuit (U4), is connected to a VCC power supply end through a twelfth resistor (R12) and is grounded through a tenth capacitor (C10), and the other end of the first key (SW1) is grounded through a thirteenth resistor (R13);
the data recovery circuit comprises a second key (SW2), one end of the second key (SW2) is connected to a RELOAD pin of a GPRS transmission circuit (U4), is connected to a VCC power supply end through a fourteenth resistor (R14) and is grounded through an eleventh capacitor (C11), and the other end of the second key (SW2) is grounded through a fifteenth resistor (R15).
As shown in fig. 13, the data storage circuit includes a programmable read only memory (U9), a pin a 0-a 2 of the programmable read only memory (U9) is grounded through a twenty-seventh resistor (R27), a pin WP is grounded through a twenty-eighth resistor (R28), a VCC pin is connected to a VCC power terminal and is grounded through a twenty-twelfth capacitor (C22), an SCL pin is connected to an IOC6 pin of a processor circuit (U8) and is connected to a VCC power terminal through a twenty-ninth resistor (R29), a pin VCC SDA is connected to an IOC7 pin of the processor circuit (U8) and is connected to the VCC power terminal through a thirty-sixth resistor (R30), and a GND pin is grounded. And meanwhile, recording and accumulating the data of the device, such as power failure time, power-on time, power failure times and the like, and storing the data for a long time for reading. The stored data can be read on site in a communication serial port mode, and can also be transmitted through a two-bus and GPRS.
As shown in fig. 14, the 485 communication circuit is used for reading various data in situ, and includes a 485 communication chip (U11) and a D-type interface (J3), the 485 communication chip (U11) RO pin is connected to the PM0 pin of the processor circuit (U8) and connected to the cathode of the fourteenth light emitting diode (D14) through a thirty-fourth resistor (R34), the anode of the fourteenth light emitting diode (D14) is connected to the VCC power supply terminal, the DI pin is connected to the PM1 pin of the processor circuit (U8) and connected to the cathode of the thirteenth light emitting diode (D13) through a thirty-third resistor (R33), the anode of the thirteenth light emitting diode (D13) is connected to the VCC power supply terminal, the thirty-third resistor (R33) and the thirty-fourth resistor (R34) are current limiting resistors, and the light indications of the thirteenth light emitting diode (D13) and the fourteenth light emitting diode (D14) during communication indicate the reading status of the data,
the pin and the DE pin are connected to a PWM3 pin of a processor circuit (U8), the pin A and the pin B are respectively connected to a TDA-/Y pin and an RDB +/B pin of a D-type interface (J3), the VCC pin is connected to a VCC power supply end and is grounded through a twenty-four capacitor (C24), the twenty-four capacitor (C24) is a filter capacitor, the GND pin is grounded, and other pins of the D-type interface (J3) are suspended.
As shown in fig. 15, the system clock circuit provides accurate time record for the system, and is configured with a battery, the battery has an automatic access function through a circuit, the battery is not powered in a normal power-on state, the battery is automatically accessed in a power-off state, and the clock is kept to normally operate during the power-off period, the system clock circuit comprises a clock chip (U10), time adjustment can be written in a programming mode and can be modified in a serial communication mode, a pin X1 and a pin X2 of the clock chip (U10) are respectively connected to two ends of a clock crystal oscillator (Y2), a pin Y2 is a clock crystal oscillator of 32.768KHz to provide accurate clock signals for the chip, a pin SCL is connected to a pin PS6 of a processor circuit (U8) and is connected to a VCC power supply terminal through a thirty-one resistor (R31), a pin SDA is connected to a pin ECLK of the processor circuit (U8) and is connected to the VCC power supply terminal through a twelfth resistor (R32), and the VCC pin is respectively connected to a cathode of an eleventh diode (D11) and a cathode of a twelfth diode (D12), the anode of an eleventh diode (D11) is connected to the positive polarity end of the battery (P1), the negative polarity end of the battery (P1) is grounded, P1 is a power circuit of the clock chip, the power supply supplies power to the clock chip through a twelfth diode (D12) during normal power-on, and the battery (P1) does not supply power as the VCC voltage (5V) of the power supply is higher than the voltage (3V) of the battery (P1); when the device is powered off, the battery (P1) supplies power to the clock chip, the holding time is kept, the anode of the twelfth diode (D12) is connected to the VCC power supply end, the VCC pin is grounded through the second thirteen capacitor (C23), the twenty-third capacitor (C23) is a filter capacitor, the GND pin is grounded,
pin and
the pins are suspended.
As shown in fig. 16, the IP address coding circuit includes a toggle switch (SW3), and pins of the toggle switch (SW3) are respectively connected to pins AN 0-AN 3 and AN 8-AN 11 of the processor circuit (U8), so as to provide a set of coded addresses, which are 0-255, for the device, thereby facilitating the IP address arrangement on site.
As shown in fig. 17 and 18, the first BUS signal input port BUS1, the second BUS signal input port BUS2, the first non-polarity switch terminal Z1 and the second non-polarity switch terminal Z2 of the fire control system manual/automatic converter are connected to the monitoring device through the input interface J1, and the input interface J1 is used as the input interface of the two BUS signals of the consumption control system and the non-polarity switch signal of the manual/automatic converter; the external power supply provides electric energy for the monitoring device through a power interface J2, and the power interface J2 is used as an input interface of a 12V direct-current power supply.
When the switches arranged on fire separation facilities such as a normal automatic water-spraying fire extinguishing system, a fire-proof rolling curtain and the like controlled in a linkage mode are in an automatic state, nonpolar switch signals of a first nonpolar switch end Z1 and a second nonpolar switch end Z2 are subjected to photoelectric signal isolation and conversion through a third optical coupler U5 and then are input into a processor circuit U8 through an input interface J1, and after the level of the input signal is judged, the switch position at the moment is determined to be in a normal state in an automatic state, so that functions such as acousto-optic alarm, data remote transmission and the like are not started on site by the processor circuit U8.
When an operator sets fire separation facilities such as an automatic water spray fire extinguishing system, a fire-proof roller shutter under linkage control and the like in a manual control state or when a switching device at the moment breaks down, nonpolar switch signals of a first nonpolar switch end Z1 and a second nonpolar switch end Z2 of a manual/automatic converter are transmitted to a processor circuit U8 through a monitoring switch input circuit through an input interface J1, and under the condition that the processor circuit U8 judges that the switches are not in normal requirements, the state of the monitoring signals and data such as IP addresses of the device are simultaneously and remotely transmitted to a main control console of a fire-fighting headquarters through a GPRS transmission circuit U4, the control modes of all fire-fighting facilities are monitored in real time, and field faults are alarmed through an acousto-optic alarm circuit, so that the fire-fighting control system is ensured to play the actual role.
Besides signal transmission, it can record the number and time of hand/automatic state change, and the clock chip with battery can keep the time in power-off state, so it can accurately record the change-over time of hand/automatic switch and the keeping period of changed-over state. Besides being read in site by an external communication serial port mode, the recorded time data can be transmitted by two buses and a GPRS remote transmission mode, and the data can be remotely transmitted to a control cabinet and a main console of a fire-fighting headquarters.
The device is electrified again after power failure, and data such as power failure time, power-on time, power failure times and the like of the device can be recorded by reading the clock chip, and the data can be transmitted to a control center remotely and also can be read on site during patrol.
Claims (7)
1. Device with fire control switch conversion monitoring and record function, its characterized in that: the intelligent fire-fighting monitoring system comprises a processor circuit (U8), a two-bus communication circuit connected with the processor circuit (U8), a monitoring switch input circuit, a field fault alarm acousto-optic alarm circuit, an internal power supply conversion circuit for providing a required power supply for the device, a GPRS transmission circuit (U4), a data storage circuit, a 485 communication circuit for reading data on site, a system clock circuit for providing accurate time record for the system and an IP address coding circuit, wherein the two-bus communication circuit is in signal communication connection with an external fire-fighting control system, the monitoring switch input circuit is in signal connection with a switching value input signal of a manual/automatic converter of the fire-fighting control system, and the GPRS transmission circuit (U4) is in information interaction with a fire-fighting headquarters through satellite data transmission;
the processor circuit (U8) includes a power-on reset and program debug circuit
Pin and PWM6 pin, XTAL pin and EXTAL pin connected with processor clock circuit, PWM4 pin connected with GPRS transmission circuit (U4), PWM5 pin, IOC0 pin-IOC 5 pin, PS2 pin and PS3 pinThe device comprises pins, AN IOC6 pin and AN IOC7 pin which are connected with a data storage circuit, a PM0 pin, a PM1 pin and a PWM3 pin which are connected with a 485 communication circuit, AN ECLK pin and a PS6 pin which are connected with a system clock circuit, AN AN0 pin-AN 3 pin, AN AN8 pin-AN 11 pin which are connected with AN IP address coding circuit, AN AN5 pin-AN 7 pin which is connected with AN audible and visual alarm circuit, AN AN4 pin which is connected with a monitoring switch input circuit, a PS0 pin and a PS1 pin which are connected with a two-bus communication circuit or a two-bus signal isolation circuit, a VDDXRA pin and a VDDA pin are connected with a VCC power supply end, a VSSX pin, a VSS pin and a VSSA pin are grounded, a TEST pin, a PWM7 pin, a BKDD pin, a PWM0 pin-PWM 2 pin, a PS4 pin and a PS5 pin; the power-on RESET and programming debugging circuit comprises a BDM debugger (JP1), wherein a BDM debugger (JP1) BKGD pin is connected to a PWM6 pin of a processor circuit (U8) and is connected to a VCC power supply end through a twenty-fourth resistor (R24), a VDD pin is connected to the VCC power supply end, a BDM debugger (JP1) RESET pin is connected to the VCC power supply end through a twenty-sixth resistor (R26), the RESET pin is grounded through a twenty-fifth resistor (R25) and a seventeenth capacitor (C17) in series connection, and the common end of the twenty-fifth resistor (R25) and the seventeenth capacitor (C17) is connected to the processor circuit (U8)
The pin, the NC pin and the GND pin are grounded, and the VFP pin is suspended; the processor clock circuit comprises a crystal oscillator (XT1), two ends of the crystal oscillator (XT1) are respectively connected to an XTAL pin and an EXTAL pin of the processor circuit (U8), and two ends of the crystal oscillator (XT1) are grounded through an eighteenth capacitor (C18) and a nineteenth capacitor (C19);
the two bus communication circuits are connected with the processor circuit (U8) through two bus signal isolation circuits; the two bus communication circuits comprise a bus master station communication interface chip (U1) and a non-polar bidirectional circuit, wherein the non-polar bidirectional circuit comprises a second diode (D2) and a third diode (D3) which are connected in series, and a fourth diode (D4) and a fifth diode (D5) which are connected in series, the cathode of the second diode (D2) is connected with the cathode of the fourth diode (D4), the anode of the second diode (D2) is connected with the cathode of the third diode (D3), the anode of the fourth diode (D4) is connected with the cathode of the fifth diode (D5), and the anode of the third diode (D3) is connected with the anode of the fifth diode (D5); the pin SIN of the BUS master station communication interface chip (U1) is connected to the common end of the cathode of the second diode (D2), the cathode of the fourth diode (D4) and the anode of the sixth diode (D6), the common end of the anode of the second diode (D2) and the cathode of the third diode (D3) is connected to the first BUS signal input end (BUS1), the common end of the anode of the fourth diode (D4) and the cathode of the fifth diode (D5) is connected to the second BUS signal input end (BUS2), the common end of the first BUS signal input end (BUS1) and the second BUS signal input end (BUS2) is connected in parallel with a first voltage stabilizing diode (D1), a first capacitor (C1) and a second capacitor (C2) in series, the signal of the first capacitor (C1) and the second capacitor (C2) is grounded, the pin VCC of the BUS master station communication interface chip (U1) is connected to the sixth master station resistor (D1) 6), a third capacitor (C3) and a fourth capacitor (C4) are connected between a VCC pin and a GND pin of a bus master station communication interface chip (U1) in parallel, the negative electrode of the third capacitor (C3) and the GND pin are grounded in signal mode, a VOUT pin and a SEL pin are connected to a 5V power supply and are grounded in signal mode through a fifth capacitor (C5), an RXD pin is connected to a PS0 pin of a processor circuit (U8) through a second bus signal isolation circuit or a sixth resistor, a TXD pin is connected to a PS1 pin of the processor circuit (U8) through the second bus signal isolation circuit or the seventh resistor, and an NC pin is suspended; the two-bus signal isolation circuit comprises a first optical coupler (U2) and a second optical coupler (U3), the first optocoupler (U2) AN pin is connected to a 5V power supply and a second optocoupler (U3) VCC pin and AN EN pin, the first optocoupler (U2) CATH pin is connected to a bus master station communication interface chip (U1) RXD pin through a second resistor (R2), the first optocoupler (U2) VCC pin and the EN pin are connected to VCC and a second optocoupler (U3) AN pin, the first optocoupler (U2) OUT pin is connected to a processor circuit (U8) PS0 pin and a first optocoupler (U2) VCC pin and AN EN pin through a fourth resistor (R4), the first optocoupler (U2) GND pin is grounded and connected to the first optocoupler (U2) NC VCC pin and the EN pin through a seventh capacitor (C7), and the NC pin and the 1 pin are suspended; a second optical coupler (U3) OUT pin is connected to a TXD pin of a bus master station communication interface chip (U1) and is connected to a VCC pin and an EN pin of a second optical coupler (U3) through a third resistor (R3), a GND pin of the second optical coupler (U3) is grounded through a signal and is connected to a 5V power supply through a sixth capacitor (C6), a CATH pin of the second optical coupler (U3) is connected to a PS1 pin of a processor circuit (U8) through a fifth resistor (R5), and the NC pin and the NC1 pin are suspended;
the monitoring switch input circuit comprises a third optical coupler (U5), a CATH pin of the third optical coupler (U5) is connected to a first nonpolar switch end (Z1) of the fire control system manual/automatic converter through a twentieth resistor (R20), AN AN pin is connected to a VDD power supply end, a second nonpolar switch end (Z2) of the fire control system manual/automatic converter and signal ground, the VCC pin and AN EN pin are connected to the VCC power supply end, AN OUT pin is connected to AN AN4 pin of the processor circuit (U8) and is connected to a VCC pin and AN EN pin of the third optical coupler (U5) through a twenty-first resistor (R21), the GND pin is grounded and is connected to the VCC pin and the EN pin through a twelfth capacitor (C12), and the NC pin and the NC1 are suspended; the monitoring switch input circuit can be connected between a VDD power supply end and a VCC power supply end through a twenty-second resistor, and a twenty-third resistor is connected between signal ground and power ground to short-circuit a switch signal isolation function.
2. A device with fire control switch transition monitoring and logging functions as defined in claim 1, wherein: the acousto-optic alarm circuit comprises a buzzer alarm circuit and AN indicator lamp circuit, the buzzer alarm circuit comprises a buzzer (M1), the pin IN + of the buzzer (M1) is connected to the VCC power supply end, the pin IN1 is connected to the collector of a second triode (Q2), the power supply of the emitter of the second triode (Q2) is grounded, the base of the second triode (Q2) is connected to the pin AN5 of the processor circuit (U8) through a sixteenth resistor (R16), and a seventeenth resistor (R17) and a thirty-first capacitor (C31) are connected between the base of the second triode (Q2) and the power ground IN parallel;
the indicator light circuit comprises a first light-emitting diode (D7) and a second light-emitting diode (D8), wherein the anode of the first light-emitting diode (D7) and the anode of the second light-emitting diode (D8) are connected to a VCC power supply end, the cathode of the first light-emitting diode (D7) is connected to a pin AN7 of a processor circuit (U8) through AN eighteenth resistor (R18), and the cathode of the second light-emitting diode (D8) is connected to a pin AN6 of the processor circuit (U8) through a nineteenth resistor (R19).
3. A device with fire control switch transition monitoring and logging functions as defined in claim 1, wherein: the internal power conversion circuit comprises a system power circuit and a signal isolation power circuit, wherein the system power circuit comprises an integrated voltage stabilizing circuit (U6), an IN pin of the integrated voltage stabilizing circuit (U6) is connected to a 12V power supply, the cathode of a ninth voltage stabilizing diode (D9), the anode of a thirteenth capacitor (C13) and one end of a fourteenth capacitor (C14) are connected to the IN pin, the anode of the ninth voltage stabilizing diode (D9), the cathode of a thirteenth capacitor (C13) and the other end of the fourteenth capacitor (C14) are grounded, an OUT pin is output to a VCC power end through a first inductor (L1), an FB pin is connected to the VCC power end, the GND pin and an ON/OFF pin are grounded, the cathode of a tenth voltage stabilizing diode (D10) is connected to the OUT pin, the anode of a fifteenth capacitor (C15) and one end of a sixteenth capacitor (C16) are connected to the VCC power end, the anode of the tenth voltage stabilizing diode (D10), the 12) is connected to the 12V power supply, and the anode of the fourteenth capacitor (C3552) is connected to the VCC power supply end, The negative electrode of the fifteenth capacitor (C15) and the other end of the sixteenth capacitor (C16) are grounded;
the signal isolation power supply circuit comprises a DC-DC power supply circuit (U7), wherein a VIN + pin of the DC-DC power supply circuit (U7) is connected to a VCC power supply end, a VOUT + pin is connected to a VDD power supply end, a VIN-pin power supply is grounded, and a VOUT-pin signal is grounded.
4. A device with fire control switch transition monitoring and logging functions as defined in claim 1, wherein: the pin LINK1 and the pin LINK2 of the GPRS transmission circuit (U4) are respectively connected to the pin IOC0 and the pin IOC1 of the processor circuit (U8), the pin LINK4 and the pin LINK4 of the GPRS transmission circuit (U4) are respectively connected to the pin IOC4 and the pin IOC4 of the processor circuit (U4) through an eighth resistor (R4) and a ninth resistor (R4), the pin UTXD 4 and the pin URXD 4 of the GPRS transmission circuit (U4) are respectively connected to the pin PS4 and the pin PS4 of the processor circuit (U4), the pin WORD of the GPRS transmission circuit (U4) is connected to the pin PWM4 of the processor circuit (U4), the pin WKEY of the GPRS transmission circuit (U4) is connected to the pin PS4 of the first field effect transistor (Q4), the drain electrode of the first field effect transistor (Q4) is connected to the pin LOU 4 of the processor circuit (U4), the pin RERK 4) is connected to the pin of the RESET circuit (U4) and the RESET circuit (RE 4) is connected to the pin of the first field effect transistor (RE GND) of the RESET circuit (U4), a pin RE485_ EN of a GPRS transmission circuit (U4) is connected to a pin IOC5 of a processor circuit (U8) through an eleventh resistor (R11), a pin LINK of the GPRS transmission circuit (U4) is connected to a pin IOC4 of a processor circuit (U8), a pin VCAP of the GPRS transmission circuit (U4) is connected to the anode of an eighth capacitor (C8), pins DC5-18V are connected to a VCC power supply end and the anode of a ninth capacitor (C9), the cathode of the eighth capacitor (C8) and the cathode of the ninth capacitor (C9) are grounded, and a pin NC1, a pin NC2, a pin RCV _ N, a pin RCV _ P, a pin MIC _ N and a pin MIC _ P are suspended;
the RESET circuit comprises a first key (SW1), one end of the first key (SW1) is connected to a RESET pin of a GPRS transmission circuit (U4), is connected to a VCC power supply end through a twelfth resistor (R12) and is grounded through a tenth capacitor (C10), and the other end of the first key (SW1) is grounded through a thirteenth resistor (R13);
the data recovery circuit comprises a second key (SW2), one end of the second key (SW2) is connected to a RELOAD pin of a GPRS transmission circuit (U4), is connected to a VCC power supply end through a fourteenth resistor (R14) and is grounded through an eleventh capacitor (C11), and the other end of the second key (SW2) is grounded through a fifteenth resistor (R15).
5. A device with fire control switch transition monitoring and logging functions as defined in claim 1, wherein: the data storage circuit comprises a programmable read-only memory (U9), a pin A0-A2 of the programmable read-only memory (U9) is grounded through a twenty-seventh resistor (R27), a pin WP is grounded through a twenty-eighteenth resistor (R28), a pin VCC is connected to a VCC power supply end and is grounded through a twenty-twelve capacitor (C22), a pin SCL is connected to a pin IOC6 of the processor circuit (U8) and is connected to the VCC power supply end through a twenty-ninth resistor (R29), a pin SDA is connected to a pin IOC7 of the processor circuit (U8) and is connected to the VCC power supply end through a thirty-th resistor (R30), and the pin GND is grounded.
6. A device with fire control switch transition monitoring and logging functions as defined in claim 1, wherein: the 485 communication circuit comprises a 485 communication chip (U11) and a D-type interface (J3), wherein an RO pin of the 485 communication chip (U11) is connected to a PM0 pin of a processor circuit (U8) and is connected to a cathode of a fourteenth light-emitting diode (D14) through a thirty-fourth resistor (R34), an anode of the fourteenth light-emitting diode (D14) is connected to a VCC power supply end, a DI pin is connected to a PM1 pin of the processor circuit (U8) and is connected to a cathode of a thirteenth light-emitting diode (D13) through a thirty-third resistor (R33), an anode of the thirteenth light-emitting diode (D13) is connected to the VCC power supply end,
the pin and the DE pin are connected to a PWM3 pin of a processor circuit (U8), the pin A and the pin B are respectively connected to a TDA-/Y pin and a RDB +/B pin of a D-type interface (J3), the VCC pin is connected to a VCC power supply end and is grounded through a twenty-four capacitor (C24), the GND pin is grounded, and other pins of the D-type interface (J3) are suspended.
7. A device with fire control switch transition monitoring and logging functions as defined in claim 1, wherein: the system clock circuit comprises a clock chip (U10), wherein the X1 pin and the X2 pin of the clock chip (U10) are respectively connected to two ends of a clock crystal oscillator (Y2), the SCL pin is connected to the PS6 pin of a processor circuit (U8) and is connected to a VCC power supply end through a thirty-first resistor (R31), the SDA pin is connected to the ECLK pin of the processor circuit (U8) and is connected to the VCC power supply end through a thirty-second resistor (R32), the VCC pin is respectively connected to the cathode of an eleventh diode (D11) and a twelfth diode (D12), the anode of the eleventh diode (D11) is connected to the positive polarity end of a battery (P1), the negative polarity end of the battery (P1) is grounded, the anode of the twelfth diode (D12) is connected to the VCC power supply end, and the VCC pin is grounded through a second thirteen capacitor (C23), and the pin is grounded,
pin and
the pins are suspended.
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| CN201710701177.8A CN107320893B (en) | 2017-08-16 | 2017-08-16 | Device with fire control switch conversion monitoring and recording functions |
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| CN107320893B true CN107320893B (en) | 2022-04-29 |
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| CN110769551B (en) * | 2019-10-23 | 2021-10-08 | 连云港杰瑞自动化有限公司 | Active light source control circuit for explosion-proof occasion |
| CN111459727B (en) * | 2019-12-25 | 2023-07-14 | 山东有人物联网股份有限公司 | Intelligent automatic test system and method for serial port baud rate maximum error-free tolerance range |
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| CN1794307A (en) * | 2005-12-30 | 2006-06-28 | 天津市英克瑞电子技术有限公司 | Control system of fire display disc |
| JP2007213307A (en) * | 2006-02-09 | 2007-08-23 | Machiko Shimizu | Fire monitoring and extinguishment/water discharge control system |
| CN205721269U (en) * | 2016-04-21 | 2016-11-23 | 北京中科精图信息技术有限公司 | A kind of Intelligent fire-fighting control chamber being embedded in body of wall |
| CN206057925U (en) * | 2016-08-29 | 2017-03-29 | 郑州金特莱电子有限公司 | Fire-fighting equipment power supply status monitoring system |
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|---|---|---|---|---|
| CN1794307A (en) * | 2005-12-30 | 2006-06-28 | 天津市英克瑞电子技术有限公司 | Control system of fire display disc |
| JP2007213307A (en) * | 2006-02-09 | 2007-08-23 | Machiko Shimizu | Fire monitoring and extinguishment/water discharge control system |
| CN205721269U (en) * | 2016-04-21 | 2016-11-23 | 北京中科精图信息技术有限公司 | A kind of Intelligent fire-fighting control chamber being embedded in body of wall |
| CN206057925U (en) * | 2016-08-29 | 2017-03-29 | 郑州金特莱电子有限公司 | Fire-fighting equipment power supply status monitoring system |
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