The device of monitoring and writing function is changed with fire-fighting controlling switch
Technical field
The present invention relates to fire control system, and in particular to one kind have fire-fighting control hand/automatic switch conversion monitoring and
The device of writing function.
Background technology
According to《Fire protection control room general technology standard》With management of fire safety system, in quasi-operating status, forbid water
The power distribution cabinet of fire extinguishing system, smoke control system and electronic fire separation facility is placed in manual state of a control.But some units and
The operating personnel of some control rooms because of various reasons, and power distribution cabinet are placed in for a long time manual state of a control, are simply dealing with correlation
Department is just transformed into automatic control state when checking, does not reach the automatic effects of automatic system.
The content of the invention
In view of the above-mentioned problems, the present invention provides a kind of with fire-fighting control hand/automatic switch conversion monitoring and writing function
Device.
To solve the above problems, the technical scheme that the present invention takes is:Monitoring is changed with fire-fighting controlling switch and is recorded
The device of function, including processor circuit (U8), the two lines bus communicating circuit, the monitoring switch that are connected with processor circuit (U8) are defeated
Enter circuit, the sound light alarming circuit of field failure alarm, field failure is alarmed by light emitting diode and buzzer, is
The internal electric source change-over circuit of power supply, is provided for the system power supply circuit and signal isolation power circuit of device needed for device is provided
Power supply, GPRS transmission circuit (U4), data storage circuitry, scene are read 485 communicating circuits of data, carried for system needed for two-way
The system clock circuit that is recorded for correct time and the IP address coding circuit that scene IP address layout is provided for device, it is described
Two lines bus communicating circuit is connected with external fire control system signal communication, keeps the exchange of data, monitoring switch input circuit
It is connected with fire control system hand/automatic switch On-off signal signal, GPRS transmission circuit (U4) is passed by satellite data
Defeated and fire-fighting general headquarters information exchange.
Described processor circuit (U8) includes what is be connected with electrification reset and detail programming circuitPin and
PWM6 pins, the XTAL pins and EXTAL pins being connected with processor clock circuit, are connected with GPRS transmission circuit (U4)
PWM4 pins, PWM5 pins, IOC0 pins-IOC5 pins, PS2 pins and PS3 pins, are connected with data storage circuitry
IOC6 pins and IOC7 pins, the PM0 pins being connected with 485 communicating circuits, PM1 pins and PWM3 pins, with system clock electricity
The ECLK pins and PS6 pins of road connection, the AN0 pins-AN3 pins being connected with IP address coding circuit, AN8 pins-
AN11 pins, the AN5 pins-AN7 pins being connected with sound light alarming circuit, the AN4 being connected with monitoring switch input circuit draws
Pin, the PS0 pins and PS1 pins being connected with two lines bus communicating circuit or two lines bus signal isolation circuit, VDDXRA pins and
VDDA pins are connected to VCC power ends, VSSX pins, VSS pins and VSSA pin power grounds, TEST pins, PWM7 pins,
BKGD pins, PWM0-PWM2 pins, PS4 pins and PS5 pins are hanging;
Described electrification reset and detail programming circuit include BDM debuggers (JP1), BDM debuggers (JP1) BKGD pins
It is connected to processor circuit (U8) PWM6 pins and VCC power ends is connected to by the 24th resistance (R24), VDD pins connects
VCC power ends are connected to, BDM debuggers (JP1) RESET pins are connected to VCC power ends by the 26th resistance (R26),
RESET pins are grounded by the 25th resistance (R25) and the 17th electric capacity (C17) series-connection power supplies, the 25th resistance (R25)
Processor circuit (U8) is connected to the 17th electric capacity (C17) common portPin, NC pins and GND pin power supply connect
Ground, VFP pins are hanging;
Described processor clock circuit includes crystal oscillator (XT1), and crystal oscillator (XT1) two ends are respectively connecting to
Processor circuit (U8) XTAL pins and EXTAL pins, and crystal oscillator (XT1) two ends by the 18th electric capacity (C18) and
19th electric capacity (C19) power ground;
Described power filtering capacitor includes the 20th electric capacity and second being connected in parallel between VCC power ends and power ground
Ten electric capacity.
Described two lines bus communicating circuit is connected by two lines bus signal isolation circuit with processor circuit (U8);
Two lines bus communicating circuit includes bus master communication interface chip (U1) and nonpolarity two-way circuit, and described is electrodeless
Property two-way circuit include series connection the second diode (D2) and the 3rd diode (D3), connect the 4th diode (D4) and the 5th
Diode (D5), and the second diode (D2) negative electrode is connected with the 4th diode (D4) negative electrode, the second diode (D2) anode connects
The 3rd diode (D3) negative electrode is connected to, the 4th diode (D4) anode is connected to the 5th diode (D5) negative electrode, the 3rd diode
(D3) anode is connected with the 5th diode (D5) anode;
Described bus master communication interface chip (U1) SIN pins are connected to the second diode (D2) negative electrode, the four or two
The common port of pole pipe (D4) negative electrode and the 6th diode (D6) anode, the second diode (D2) anode and the 3rd diode (D3) are cloudy
The common port of pole is connected to two lines bus signal first input end (BUS1), the 4th diode (D4) anode and the 5th diode (D5)
The common port of negative electrode is connected to the input of two lines bus signal second (BUS2), two lines bus signal first input end (BUS1) and two total
The first voltage-regulator diode (D1) and the first electric capacity (C1), the second electric capacity (C2) are parallel between the input of line signal second (BUS2)
Series arm, and the first electric capacity (C1) and the second electric capacity (C2) common port signal ground, the first voltage-regulator diode enter for bus
The forceful electric power protection of mouth, the first electric capacity and the second electric capacity are used to coordinate the first voltage-regulator diode to do bus filter processing, bus master
Communication interface chip (U1) VCC pin is connected to the 6th diode (D6) negative electrode, the 3rd electric capacity (C3) by first resistor (R1)
And the 4th electric capacity (C4) be connected in parallel to bus master communication interface chip (U1) between VCC pin and GND pin, the 3rd electric capacity (C3)
Negative pole and GND pin signal ground, VOUT pins and SEL pins are connected to 5V power supplys and connect by the 5th electric capacity (C5) signal
Ground, RXD pins are connected to processor circuit (U8) PS0 pins by two lines bus signal isolation circuit or the 6th resistance, if desired for
By two lines bus signal isolation circuit, two then are passed through if isolating in undesired signal by the 6th resistance, TXD pins for signal isolation
Bus signals isolation circuit or the 7th resistance are connected to processor circuit (U8) PS1 pins, and two are then passed through if desired for signal isolation
Bus signals isolation circuit, by the 7th resistance if isolating in undesired signal, NC pins are hanging;
Two lines bus signal isolation circuit includes the first photo-coupler (U2) and the second photo-coupler (U3), wherein the first optocoupler
Clutch (U2) AN pins are connected to 5V power supplys and the second photo-coupler (U3) VCC pin and EN pins, the first photo-coupler (U2)
CATH pins are connected to bus master communication interface chip (U1) RXD pins, the first photo-coupler by second resistance (R2)
(U2) VCC pin and EN pins are connected to VCC power ends and the second photo-coupler (U3) AN pins, the first photo-coupler (U2)
OUT pins are connected to processor circuit (U8) PS0 pins and are connected to the first photo-coupler (U2) VCC by the 4th resistance (R4)
Pin and EN pins, the first photo-coupler (U2) GND pin power ground and are connected to the first optocoupler by the 7th electric capacity (C7)
Clutch (U2) VCC pin and EN pins, NC pins and NC1 pins are hanging, and two lines bus signal is inputted by SIN pins, through bus master
TTL signal is exported by RXD pins after communication interface chip of standing demodulation, transmitted after the first photo-coupler to processor circuit;
Second photo-coupler (U3) OUT pins are connected to bus master communication interface chip (U1) TXD pins and by
Three resistance (R3) are connected to the second photo-coupler (U3) VCC pin and EN pins, and the second photo-coupler (U3) GND pin signal connects
Ground and 5V power supplys are connected to by the 6th electric capacity (C6), the second photo-coupler (U3) CATH pins are connected by the 5th resistance (R5)
To processor circuit (U8) PS1 pins, NC pins and NC1 pins are hanging, and the TTL signal of processor circuit output is through the second optocoupler
It is up into modulated signal in bus by TXD pin input bus master station communication interface chips after clutch.
Described monitoring switch input circuit includes the 3rd photo-coupler (U5), and the 3rd photo-coupler (U5) CATH pins lead to
Cross the 20th resistance (R20) and be connected to the first nonpolarity switch terminals of fire control system hand/automatic switch (Z1), AN pins connect
It is connected to VDD power ends, the second nonpolarity switch terminals of fire control system hand/automatic switch (Z2) and signal ground, VCC pin
VCC power ends are connected to EN pins, OUT pins are connected to processor circuit (U8) AN4 pins and by the 21st resistance
(R21) it is connected to the 3rd photo-coupler (U5) VCC pin and EN pins, GND pin power ground and passes through the 12nd electric capacity
(C12) VCC pin and EN pins are connected to, NC pins and NC1 pins are hanging, Z1 and Z2 are used to input hand/automatic switch
Nonpolarity switching signal, is transmitted to processor circuit after the 3rd photo-coupler signal isolation;
3rd photo-coupler plays a part of level conversion and signal isolation, and such as undesired signal is isolated, described monitoring
Switch input circuit can be connected between VDD power ends and VCC power ends by the 22nd resistance, the connection of the 23rd resistance
Between signal ground and power ground, by switching signal isolation features short circuit, the effect for making it only serve level conversion, power supply
VDD is obtained by DC-DC power source circuit module.
Described sound light alarming circuit includes buzzer alarm circuit and indicator light circuit, and buzzer alarm circuit includes honeybee
Ring device (M1), and buzzer (M1) IN+ pins are connected to VCC power ends, and IN1 pins are connected to the second triode (Q2) colelctor electrode,
Second triode (Q2) emitter stage power ground, the second triode (Q2) base stage is connected to processing by the 16th resistance (R16)
Device circuit (U8) AN5 pins, the 17th resistance (R17) and the 31st electric capacity (C31) are connected in parallel to the second triode (Q2)
Between base stage and power ground;
Indicator light circuit includes the first light emitting diode (D7) and the second light emitting diode (D8), respectively as working power
Indicator lamp and alarm lamp, the first light emitting diode (D7) anode and the second light emitting diode (D8) anode are connected to VCC electricity
Source, the first light emitting diode (D7) negative electrode is connected to processor circuit (U8) AN7 pins by the 18th resistance (R18), the
Two light emitting diodes (D8) negative electrode is connected to processor circuit (U8) AN6 pins by the 19th resistance (R19).
Described internal electric source change-over circuit includes system power supply circuit and signal isolation power circuit, wherein system power supply
Circuit includes integrated stable voltage circuit (U6), and integrated stable voltage circuit (U6) IN pins are connected to 12V power supplys, the 9th voltage-regulator diode
(D9) negative electrode, the 13rd electric capacity (C13) positive pole and the 14th electric capacity (C14) one end are connected to IN pins, the 9th voltage-regulator diode
(D9) anode, the 13rd electric capacity (C13) negative pole and the 14th electric capacity (C14) other end power ground, OUT pins pass through the first electricity
(L1) output is felt to VCC power ends, and FB pins are connected to VCC power ends, GND pin and ON/OFF pin power grounds, the tenth
Voltage-regulator diode (D10) negative electrode is connected to OUT pins, the 15th electric capacity (C15) positive pole and the connection of the 16th electric capacity (C16) one end
To VCC power ends, the tenth voltage-regulator diode (D10) anode, the 15th electric capacity (C15) negative pole and the 16th electric capacity (C16) are another
Power ground is held, the 12V Power converts that system power supply circuit inputs power interface is the 5V power supplys needed for circuit system;
Signal isolation power circuit includes DC-DC power source circuit (U7), and DC-DC power source circuit (U7) VIN+ pins are connected to
VCC power ends, VOUT+ pins are connected to VDD power ends, VIN- pin power grounds, VOUT- leg signals ground connection, DC-DC electricity
Source circuit generates another group of electrically completely isolated 5V power supply by the 5V power supplys of system, is used as the isolation electricity of nonpolarity input
Source is used.
Described GPRS transmission circuit (U4) LINK1 pins and LINK2 pins are respectively connecting to processor circuit (U8)
IOC0 pins and IOC1 pins, GPRS transmission circuit (U4) LINK3 pins and LINK4 pins respectively by the 8th resistance (R8) and
9th resistance (R9) is connected to processor circuit (U8) IOC2 pins and IOC3 pins, GPRS transmission circuit (U4) UTXD1 pins
Processor circuit (U8) PS2 pins and PS3 pins, GPRS transmission circuit (U4) WORK pins are respectively connecting to URXD1 pins
Processor circuit (U8) PWM4 pins are connected to, GPRS transmission circuit (U4) POWKEY pins are connected to the first FET (Q1)
Drain electrode, grid are connected to processor circuit (U8) PWM5 pins by the tenth resistance (R10), and GPRS transmission circuit (U4) GND draws
Pin is connected to the first FET (Q1) source electrode and power ground, GPRS transmission circuit (U4) RESET pins and RELOAD pins
Reset circuit and data recovery circuit are respectively connecting to, GPRS transmission circuit (U4) RE485_EN pins pass through the 11st resistance
(R11) processor circuit (U8) IOC5 pins are connected to, GPRS transmission circuit (U4) LINK pins are connected to processor circuit
(U8) IOC4 pins, GPRS transmission circuit (U4) VCAP pins are connected to the 8th electric capacity (C8) positive pole, and DC5-18V pins are connected to
VCC power ends and the 9th electric capacity (C9) positive pole, the 8th electric capacity (C8) negative pole and the 9th electric capacity (C9) negative power supply ground connection, NC1 draw
Pin, NC2 pins, RCV_N pins, RCV_P pins, MIC_N pins and MIC_P pins are hanging;
Described reset circuit includes the first button (SW1), and the first button (SW1) one end is connected to GPRS transmission circuit
(U4) RESET pins, be connected to by the 12nd resistance (R12) VCC power ends and by the tenth electric capacity (C10) power ground,
First button (SW1) other end passes through the 13rd resistance (R13) power ground;
Described data recovery circuit includes the second button (SW2), and the second button (SW2) one end is connected to GPRS transmission electricity
Road (U4) RELOAD pins, it is connected to by the 14th resistance (R14) VCC power ends and by the 11st electric capacity (C11) power supply
Ground connection, the second button (SW2) other end passes through the 15th resistance (R15) power ground.
Described data storage circuitry includes programmable read only memory (U9), and programmable read only memory (U9) A0 draws
Pin-A2 pins by the 27th resistance (R27) power ground, WP pins by the 28th resistance (R28) power ground,
VCC pin is connected to VCC power ends and by the 22nd electric capacity (C22) power ground, and SCL pins are connected to processor circuit
(U8) IOC6 pins and VCC power ends are connected to by the 29th resistance (R29), SDA pins are connected to processor circuit
(U8) IOC7 pins and VCC power ends are connected to by the 30th resistance (R30), GND pin power ground, device can be remembered automatically
The retention time of state, data deposit EEPOM data after recording each transition status of hand/automatic switch, conversion time and changing
Holding circuit, is conveniently transferred, and time data memory is long.The power off time of record and integrating device, power-on time, power failure simultaneously
The data such as number of times, and longer-term storage, in case needed for reading.The data of storage are except by communicating the reading of serial mode scene, going back
Data transmission can be carried out by two lines bus and GPRS.
485 described communicating circuits are used for scene and read each item data, including 485 communication chips (U11) and D type interfaces
(J3), 485 communication chips (U11) RO pins are connected to processor circuit (U8) PM0 pins and by the 34th resistance (R34)
It is connected to the 14th light emitting diode (D14) negative electrode, the 14th light emitting diode (D14) anode and is connected to VCC power ends, DI draws
Pin is connected to processor circuit (U8) PM1 pins and is connected to the 13rd light emitting diode by the 33rd resistance (R33)
(D13) negative electrode, the 13rd light emitting diode (D13) anode are connected to VCC power ends, the 33rd resistance (R33) and the 30th
Four resistance (R34) are current-limiting resistance, when the 13rd light emitting diode (D13) and the 14th light emitting diode (D14) is communications
Lamplight pointing, represents the reading state of data,Pin and DE pins are connected to processor circuit (U8) PWM3 pins, A pins
D types interface (J3) TDA-/Y pins and RDB+/B pins are respectively connecting to B pins, VCC pin is connected to VCC power ends and logical
The 24th electric capacity (C24) power ground is crossed, the 24th electric capacity (C24) is filter capacitor, and GND pin power ground, D types connect
Mouth (J3) other pins are hanging.
Described system clock circuit provides correct time record for system, and is configured with battery, and battery passes through circuit
Do not powered with battery under function, normal power-up state is automatically accessed, battery is automatically accessed during power-off, keep outage clock
Normal operation, system clock circuit includes clock chip (U10), and time adjustment can be write by programming mode, can also be led to
Serial port modification is crossed, clock chip (U10) X1 pins and X2 pins are respectively connecting to clock crystal oscillator (Y2) two ends, and Y2 is
32.768KHz clock crystal oscillator, accurate clock signal is provided for chip, and SCL pins are connected to processor circuit (U8) PS6 and drawn
Pin and VCC power ends are connected to by the 31st resistance (R31), SDA pins be connected to processor circuit (U8) ECLK pins and
VCC power ends are connected to by the 32nd resistance (R32), VCC pin is respectively connecting to the 11st diode (D11) and the tenth
Two diodes (D12) negative electrode, the 11st diode (D11) anode is connected to battery (P1) positive ends, battery (P1) negative polarity
End power ground, power supply is clock by the 12nd diode (D12) during P1 is the power circuit of clock chip, normal power-up
Chip power supply, because power supply VCC voltages (5V) are higher than battery (P1) voltage (3V), battery (P1) is not powered;When device is powered off
Battery (P1) is powered for clock chip, and the retention time is uninterrupted, and the 12nd diode (D12) anode is connected to VCC power ends, and
VCC pin is by the 23rd electric capacity (C23) power ground, and the 23rd electric capacity (C23) is filter capacitor, GND pin power supply
Ground connection,Pin andPin is hanging.
Described IP address coding circuit includes toggle switch (SW3), and toggle switch (SW3) pin is respectively connecting to processing
Device circuit (U8) AN0 pins-AN3 pins, AN8 pins-AN11 pins, provide one group of coded address for device, are 0-255,
Convenient scene carries out IP address layout to device.
Two lines bus signal first input end and the input of two lines bus signal second, fire control system hand/automatic switch
First nonpolarity switch terminals and the second nonpolarity switch terminals are connected by input interface with monitoring device, and input interface is used as consumption
The two lines bus signal of control system and the nonpolarity switching signal input interface of hand/automatic switch;External power supply passes through power supply
Interface provides electric energy for monitoring device, power interface as 12V dc sources input interface.
The present invention proposes a kind of device for controlling hand/automatic switch to change monitoring and writing function with fire-fighting, in control
Signal is read on hand/automatic switch inside cabinet processed, except will be controlled automatically by traditional switching signal and two lines bus means
The signal of state processed is sent to fire protection control room, and can by GPRS remote transmission devices by its signal teletransmission to public security fire-fighting department or
Fire remote-monitoring center is monitored in real time, and the control model of monitoring fire fighting device, supervises unit by automatic fire-fighting facility in real time
In auto state, so that it is guaranteed that fire control system plays its practical function.Meanwhile, the device can record fire fighting device automatically
The number of times of hand/automatic conversion and time, except reading corresponding data by serial port, can also by two lines bus and
Corresponding data are passed to switch board and fire-fighting general headquarters master console by GPRS teletransmissions mode, and can be recorded and integrating device
The data such as power off time, power-on time, frequency of power cut, it is necessary to when teletransmission can be to switch board and fire-fighting general headquarters master console, also
Scene is read during inspection.
Brief description of the drawings
Fig. 1 is functional block diagram;
Fig. 2 is processor circuit;
Fig. 3 is electrification reset and detail programming circuit;
Fig. 4 is processor clock circuit;
Fig. 5 is two lines bus communicating circuit;
Fig. 6 is two lines bus signal isolation circuit;
Fig. 7 is monitoring switch input circuit;
Fig. 8 is buzzer alarm circuit;
Fig. 9 is indicator light circuit;
Figure 10 is system power supply circuit;
Figure 11 is signal isolation power circuit;
Figure 12 is GPRS transmission circuit;
Figure 13 is data storage circuitry;
Figure 14 is 485 communicating circuits;
Figure 15 is system clock circuit;
Figure 16 is IP address coding circuit;
Figure 17 is input interface;
Figure 18 is power interface.
Embodiment
As shown in figure 1, the device of monitoring and writing function is changed with fire-fighting controlling switch, including processor circuit
(U8) two lines bus communicating circuit, monitoring switch input circuit, the acousto-optic of field failure alarm, being connected with processor circuit (U8)
Warning circuit, field failure is alarmed by light emitting diode and buzzer, the inside of power supply for needed for being provided device it is electric
Power-switching circuit, power supply, GPRS transmission electricity for needed for the system power supply circuit and signal isolation power circuit of device provide two-way
When road (U4), data storage circuitry, scene read 485 communicating circuits of data, the system of correct time record are provided for system
Clock circuit and the IP address coding circuit that live IP address layout is provided for device, described two lines bus communicating circuit disappear with external
Anti- control system signal communication linking, keeps the exchange of data, and monitoring switch input circuit and fire control system hand/automatic turn
Parallel operation On-off signal signal is connected, and GPRS transmission circuit (U4) passes through satellite data transmission and fire-fighting general headquarters information exchange.
As shown in Fig. 2 microprocessor S9S12G64CALL_s of the described processor circuit U8 from FREESCALE series
48, pin 48 encapsulates LQFP48, and 5V power supplys are powered, 3 tunnel road serial communication interfaces, 24 road I/O input/output ports, processor electricity
Road (U8) includes what is be connected with electrification reset and detail programming circuitPin and PWM6 pins and processor clock circuit
The XTAL pins and EXTAL pins of connection, the PWM4 pins being connected with GPRS transmission circuit (U4), PWM5 pins, IOC0 draw
Pin-IOC5 pins, PS2 pins and PS3 pins, the IOC6 pins and IOC7 pins being connected with data storage circuitry are logical with 485
PM0 pins, PM1 pins and the PWM3 pins of news circuit connection, the ECLK pins and PS6 pins being connected with system clock circuit,
AN0 pins-AN3 pins, the AN8 pins-AN11 pins being connected with IP address coding circuit, are connected with sound light alarming circuit
AN5 pins-AN7 pins, the AN4 pins being connected with monitoring switch input circuit, with two lines bus communicating circuit or two lines bus signal
The PS0 pins and PS1 pins of isolation circuit connection, VDDXRA pins and VDDA pins are connected to VCC power ends, VSSX pins,
VSS pins and VSSA pin power grounds, TEST pins, PWM7 pins, BKGD pins, PWM0-PWM2 pins, PS4 pins and
PS5 pins are hanging;
As shown in figure 3, described electrification reset and detail programming circuit include BDM debuggers (JP1), BDM debuggers
(JP1) BKGD pins are connected to processor circuit (U8) PWM6 pins and are connected to VCC power supplys by the 24th resistance (R24)
End, VDD pins are connected to VCC power ends, and BDM debuggers (JP1) RESET pins are connected to by the 26th resistance (R26)
VCC power ends, RESET pins are grounded by the 25th resistance (R25) and the 17th electric capacity (C17) series-connection power supplies, and the 20th
Five resistance (R25) and the 17th electric capacity (C17) common port are connected to processor circuit (U8)Pin, NC pins and GND
Pin power ground, VFP pins are hanging;
As shown in figure 4, described processor clock circuit includes crystal oscillator (XT1), crystal oscillator (XT1) two ends
Processor circuit (U8) XTAL pins and EXTAL pins are respectively connecting to, and crystal oscillator (XT1) two ends pass through the 18th electricity
Hold (C18) and the 19th electric capacity (C19) power ground;
Described power filtering capacitor includes the 20th electric capacity and second being connected in parallel between VCC power ends and power ground
Ten electric capacity.
Described two lines bus communicating circuit is connected by two lines bus signal isolation circuit with processor circuit (U8);
As shown in figure 5, two lines bus communicating circuit includes bus master communication interface chip (U1) and nonpolarity two-way circuit,
Described nonpolarity two-way circuit includes the second diode (D2) and the 3rd diode (D3) of series connection, the 4th diode of series connection
And the 5th diode (D5), and the second diode (D2) negative electrode is connected with the 4th diode (D4) negative electrode, the second diode (D4)
(D2) anode is connected to the 3rd diode (D3) negative electrode, and the 4th diode (D4) anode is connected to the 5th diode (D5) negative electrode,
3rd diode (D3) anode is connected with the 5th diode (D5) anode;
Described bus master communication interface chip (U1) SIN pins are connected to the second diode (D2) negative electrode, the four or two
The common port of pole pipe (D4) negative electrode and the 6th diode (D6) anode, the second diode (D2) anode and the 3rd diode (D3) are cloudy
The common port of pole is connected to two lines bus signal first input end (BUS1), the 4th diode (D4) anode and the 5th diode (D5)
The common port of negative electrode is connected to the input of two lines bus signal second (BUS2), two lines bus signal first input end (BUS1) and two total
The first voltage-regulator diode (D1) and the first electric capacity (C1), the second electric capacity (C2) are parallel between the input of line signal second (BUS2)
Series arm, and the first electric capacity (C1) and the second electric capacity (C2) common port signal ground, the first voltage-regulator diode enter for bus
The forceful electric power protection of mouth, the first electric capacity and the second electric capacity are used to coordinate the first voltage-regulator diode to do bus filter processing, bus master
Communication interface chip (U1) VCC pin is connected to the 6th diode (D6) negative electrode, the 3rd electric capacity (C3) by first resistor (R1)
And the 4th electric capacity (C4) be connected in parallel to bus master communication interface chip (U1) between VCC pin and GND pin, the 3rd electric capacity (C3)
Negative pole and GND pin signal ground, VOUT pins and SEL pins are connected to 5V power supplys and connect by the 5th electric capacity (C5) signal
Ground, RXD pins are connected to processor circuit (U8) PS0 pins by two lines bus signal isolation circuit or the 6th resistance, if desired for
By two lines bus signal isolation circuit, two then are passed through if isolating in undesired signal by the 6th resistance, TXD pins for signal isolation
Bus signals isolation circuit or the 7th resistance are connected to processor circuit (U8) PS1 pins, and two are then passed through if desired for signal isolation
Bus signals isolation circuit, by the 7th resistance if isolating in undesired signal, NC pins are hanging;
As shown in fig. 6, two lines bus signal isolation circuit includes the first photo-coupler (U2) and the second photo-coupler (U3), its
In the first photo-coupler (U2) AN pins be connected to 5V power supplys and the second photo-coupler (U3) VCC pin and EN pins, the first light
Coupler (U2) CATH pins are connected to bus master communication interface chip (U1) RXD pins, first by second resistance (R2)
Photo-coupler (U2) VCC pin and EN pins are connected to VCC power ends and the second photo-coupler (U3) AN pins, the first optical coupling
Device (U2) OUT pins are connected to processor circuit (U8) PS0 pins and are connected to the first photo-coupler by the 4th resistance (R4)
(U2) VCC pin and EN pins, the first photo-coupler (U2) GND pin power ground and are connected to by the 7th electric capacity (C7)
One photo-coupler (U2) VCC pin and EN pins, NC pins and NC1 pins are hanging, and two lines bus signal is inputted by SIN pins, warp
TTL signal is exported by RXD pins after the demodulation of bus master communication interface chip, transmitted after the first photo-coupler to processor electricity
Road;
Second photo-coupler (U3) OUT pins are connected to bus master communication interface chip (U1) TXD pins and by
Three resistance (R3) are connected to the second photo-coupler (U3) VCC pin and EN pins, and the second photo-coupler (U3) GND pin signal connects
Ground and 5V power supplys are connected to by the 6th electric capacity (C6), the second photo-coupler (U3) CATH pins are connected by the 5th resistance (R5)
To processor circuit (U8) PS1 pins, NC pins and NC1 pins are hanging, and the TTL signal of processor circuit output is through the second optocoupler
It is up into modulated signal in bus by TXD pin input bus master station communication interface chips after clutch.
As shown in fig. 7, described monitoring switch input circuit includes the 3rd photo-coupler (U5), the 3rd photo-coupler (U5)
CATH pins are connected to the nonpolarity switch terminals of fire control system hand/automatic switch first by the 20th resistance (R20)
(Z1), AN pins are connected to VDD power ends, the second nonpolarity switch terminals of fire control system hand/automatic switch (Z2) and letter
Number ground connection, VCC pin and EN pins are connected to VCC power ends, and OUT pins are connected to processor circuit (U8) AN4 pins and logical
Cross the 21st resistance (R21) and be connected to the 3rd photo-coupler (U5) VCC pin and EN pins, GND pin power ground and logical
Cross the 12nd electric capacity (C12) and be connected to VCC pin and EN pins, NC pins and NC1 pins are hanging, Z1 and Z2 be used to inputting hand/
The nonpolarity switching signal of automatic switch, is transmitted to processor circuit after the 3rd photo-coupler signal isolation;
3rd photo-coupler plays a part of level conversion and signal isolation, and such as undesired signal is isolated, described monitoring
Switch input circuit can be connected between VDD power ends and VCC power ends by the 22nd resistance, the connection of the 23rd resistance
Between signal ground and power ground, by switching signal isolation features short circuit, the effect for making it only serve level conversion, power supply
VDD is obtained by DC-DC power source circuit module.
As shown in figure 8, described sound light alarming circuit includes buzzer alarm circuit and indicator light circuit, buzzer warning
Circuit includes buzzer (M1), and buzzer (M1) IN+ pins are connected to VCC power ends, and IN1 pins are connected to the second triode
(Q2) colelctor electrode, the second triode (Q2) emitter stage power ground, the second triode (Q2) base stage passes through the 16th resistance (R16)
Processor circuit (U8) AN5 pins are connected to, the 17th resistance (R17) and the 31st electric capacity (C31) are connected in parallel to second
Triode (Q2) is between base stage and power ground;
As shown in figure 9, indicator light circuit includes the first light emitting diode (D7) and the second light emitting diode (D8), make respectively
For working power indicator lamp and alarm lamp, the first light emitting diode (D7) anode and the second light emitting diode (D8) anode connect
VCC power ends are connected to, the first light emitting diode (D7) negative electrode is connected to processor circuit (U8) by the 18th resistance (R18)
AN7 pins, the second light emitting diode (D8) negative electrode is connected to processor circuit (U8) AN6 pins by the 19th resistance (R19).
As shown in Figure 10, described internal electric source change-over circuit includes system power supply circuit and signal isolation power circuit,
Wherein system power supply circuit includes integrated stable voltage circuit (U6), and integrated stable voltage circuit (U6) IN pins are connected to 12V power supplys, the 9th
Voltage-regulator diode (D9) negative electrode, the 13rd electric capacity (C13) positive pole and the 14th electric capacity (C14) one end are connected to IN pins, the 9th
Voltage-regulator diode (D9) anode, the 13rd electric capacity (C13) negative pole and the 14th electric capacity (C14) other end power ground, OUT pins
By the first inductance (L1) output to VCC power ends, FB pins are connected to VCC power ends, GND pin and ON/OFF pin power supplys
Ground connection, the tenth voltage-regulator diode (D10) negative electrode is connected to OUT pins, the 15th electric capacity (C15) positive pole and the 16th electric capacity
(C16) one end is connected to VCC power ends, the tenth voltage-regulator diode (D10) anode, the 15th electric capacity (C15) negative pole and the 16th
Electric capacity (C16) other end power ground, the 12V Power converts that system power supply circuit inputs power interface are for needed for circuit system
5V power supplys;
As shown in figure 11, signal isolation power circuit includes DC-DC power source circuit (U7), DC-DC power source circuit (U7) VIN
+ pin is connected to VCC power ends, and VOUT+ pins are connected to VDD power ends, VIN- pin power grounds, VOUT- leg signals
Ground connection, DC-DC power source circuit generates another group of electrically completely isolated 5V power supply by the 5V power supplys of system, as nonpolarity
The insulating power supply of input is used.
As shown in figure 12, described GPRS transmission circuit (U4) LINK1 pins and LINK2 pins are respectively connecting to processor
Circuit (U8) IOC0 pins and IOC1 pins, GPRS transmission circuit (U4) LINK3 pins and LINK4 pins pass through the 8th electricity respectively
Resistance (R8) and the 9th resistance (R9) are connected to processor circuit (U8) IOC2 pins and IOC3 pins, GPRS transmission circuit (U4)
UTXD1 pins and URXD1 pins are respectively connecting to processor circuit (U8) PS2 pins and PS3 pins, GPRS transmission circuit (U4)
WORK pins are connected to processor circuit (U8) PWM4 pins, and GPRS transmission circuit (U4) POWKEY pins are connected to first effect
(Q1) drain electrode, grid should be managed processor circuit (U8) PWM5 pins, GPRS transmission circuit are connected to by the tenth resistance (R10)
(U4) GND pin is connected to the first FET (Q1) source electrode and power ground, GPRS transmission circuit (U4) RESET pins and
RELOAD pins are respectively connecting to reset circuit and data recovery circuit, and GPRS transmission circuit (U4) RE485_EN pins pass through
11 resistance (R11) are connected to processor circuit (U8) IOC5 pins, and GPRS transmission circuit (U4) LINK pins are connected to processing
Device circuit (U8) IOC4 pins, GPRS transmission circuit (U4) VCAP pins are connected to the 8th electric capacity (C8) positive pole, DC5-18V pins
VCC power ends and the 9th electric capacity (C9) positive pole, the 8th electric capacity (C8) negative pole and the 9th electric capacity (C9) negative power supply ground connection are connected to,
NC1 pins, NC2 pins, RCV_N pins, RCV_P pins, MIC_N pins and MIC_P pins are hanging;
Described reset circuit includes the first button (SW1), and the first button (SW1) one end is connected to GPRS transmission circuit
(U4) RESET pins, be connected to by the 12nd resistance (R12) VCC power ends and by the tenth electric capacity (C10) power ground,
First button (SW1) other end passes through the 13rd resistance (R13) power ground;
Described data recovery circuit includes the second button (SW2), and the second button (SW2) one end is connected to GPRS transmission electricity
Road (U4) RELOAD pins, it is connected to by the 14th resistance (R14) VCC power ends and by the 11st electric capacity (C11) power supply
Ground connection, the second button (SW2) other end passes through the 15th resistance (R15) power ground.
As shown in figure 13, described data storage circuitry includes programmable read only memory (U9), may be programmed read-only storage
Device (U9) A0 pins-A2 pins pass through the 28th resistance (R28) by the 27th resistance (R27) power ground, WP pins
Power ground, VCC pin is connected to VCC power ends and by the 22nd electric capacity (C22) power ground, and SCL pins are connected to
Processor circuit (U8) IOC6 pins and VCC power ends are connected to by the 29th resistance (R29), SDA pins are connected to place
Manage device circuit (U8) IOC7 pins and VCC power ends, GND pin power ground, device are connected to by the 30th resistance (R30)
The retention time of state, data deposit after each transition status of hand/automatic switch, conversion time can be recorded automatically and changed
EEPOM data holding circuits, are conveniently transferred, and time data memory is long.Power off time, the upper electricity with integrating device are recorded simultaneously
The data such as time, frequency of power cut, and longer-term storage, in case needed for reading.The data of storage by communicating serial mode except being showed
Field is read, and can also pass through two lines bus and GPRS carries out data transmission.
As shown in figure 14,485 described communicating circuits are used for each item data of scene reading, including 485 communication chips (U11)
With D types interface (J3), 485 communication chips (U11) RO pins are connected to processor circuit (U8) PM0 pins and by the 34th
Resistance (R34) is connected to the 14th light emitting diode (D14) negative electrode, the 14th light emitting diode (D14) anode and is connected to VCC electricity
Source, DI pins are connected to processor circuit (U8) PM1 pins and are connected to the 13rd by the 33rd resistance (R33) and light
Diode (D13) negative electrode, the 13rd light emitting diode (D13) anode are connected to VCC power ends, the 33rd resistance (R33) and
34th resistance (R34) is current-limiting resistance, and the 13rd light emitting diode (D13) and the 14th light emitting diode (D14) are logical
Lamplight pointing during news, represents the reading state of data,Pin and DE pins are connected to processor circuit (U8) PWM3 and drawn
Pin, A pins and B pins are respectively connecting to D types interface (J3) TDA-/Y pins and RDB+/B pins, and VCC pin is connected to VCC electricity
Source and by the 24th electric capacity (C24) power ground, the 24th electric capacity (C24) is filter capacitor, and GND pin power supply connects
Ground, D types interface (J3) other pins are hanging.
As shown in figure 15, described system clock circuit provides correct time record for system, and is configured with battery, electricity
Pond has by circuit to be automatically accessed battery under function, normal power-up state and does not power, and battery is automatically accessed during power-off, keeps stopping
Clock is normally run during electricity, and system clock circuit includes clock chip (U10), and time adjustment can be write by programming mode
Enter, can also be changed by serial port, clock chip (U10) X1 pins and X2 pins are respectively connecting to clock crystal oscillator
(Y2) two ends, Y2 is 32.768KHz clock crystal oscillator, provides accurate clock signal for chip, SCL pins are connected to processor
Circuit (U8) PS6 pins and VCC power ends are connected to by the 31st resistance (R31), SDA pins are connected to processor circuit
(U8) ECLK pins and VCC power ends are connected to by the 32nd resistance (R32), VCC pin is respectively connecting to the 11st
Pole pipe (D11) and the 12nd diode (D12) negative electrode, the 11st diode (D11) anode be connected to battery (P1) positive ends,
Battery (P1) negative polarity end power ground, power supply passes through the 12nd during P1 is the power circuit of clock chip, normal power-up
Pole pipe (D12) is powered for clock chip, and because power supply VCC voltages (5V) are higher than battery (P1) voltage (3V), battery (P1) is not supplied
Electricity;When device is powered off, battery (P1) is powered for clock chip, and the retention time continues, and the 12nd diode (D12) anode connects
VCC power ends are connected to, and VCC pin, by the 23rd electric capacity (C23) power ground, the 23rd electric capacity (C23) is filtering
Electric capacity, GND pin power ground,Pin andPin is hanging.
As shown in figure 16, described IP address coding circuit includes toggle switch (SW3), toggle switch (SW3) pin point
Processor circuit (U8) AN0 pins-AN3 pins, AN8 pins-AN11 pins are not connected to, for device one group of coding is provided
Location, is 0-255, and convenient scene carries out IP address layout to device.
As shown in Figure 17, Figure 18, two lines bus signal first input end BUS1 and the second input of two lines bus signal BUS2, disappear
Anti- control system hand/automatic switch first the is nonpolarity nonpolarity switch terminals Z2 of switch terminals Z1 and second by input interface J1 with
Monitoring device is connected, and input interface J1 is opened as the two lines bus signal and the nonpolarity of hand/automatic switch of control of consumption system
OFF signal input interface;External power supply provides electric energy by power interface J2 for monitoring device, and power interface J2 is used as 12V direct currents
The input interface of power supply.
The switch set in the fire separation such as fire resisting shutter of normal automatic sprinkler system and coordinated signals facility
When being placed in auto state, the first nonpolarity nonpolarity switch terminals Z2 of switch terminals Z1 and second nonpolarity switching signal passes through the 3rd
After the isolation conversion of photo-coupler U5 photosignals, processor circuit U8 is input to through input interface J1, by input signal
After level is judged, confirm that the position of the switch now is the normal condition in auto state, therefore processor circuit U8 is not
The function such as sound and light alarm and data remote is started to scene.
When the fire separation facility such as fire resisting shutter of automatic sprinkler system and coordinated signals is arranged on by operating personnel
During manual state of a control, or switching device now is when breaking down, hand/automatic switch first is nonpolarity switch terminals Z1 and
Second nonpolarity switch terminals Z2 nonpolarity switching signal is transmitted to processing by input interface J1 through monitoring switch input circuit
Device circuit U 8, processor circuit U8, will by GPRS transmission circuit U 4 in the case where judging that switch is not in normal requirement
The teletransmission simultaneously of the data such as the state of monitoring signals and the IP address of the present apparatus monitors each in real time to the master console of fire-fighting general headquarters
The control model of fire fighting device, and field failure is alarmed by sound light alarming circuit, it is ensured that fire control system is played
Its practical function.
Except signal transmission, number of times when hand/auto state is changed and time can carried out with recording control apparatus, matched somebody with somebody
Being equipped with the clock chip of battery can continue in the retention time under power down mode, therefore can with accurate recording hand/automatic switch
After conversion time and conversion during the holding of state.The time data recorded by external communication serial mode scene except being read
Take, can also be transmitted by two lines bus and GPRS teletransmission modes, by the main control of data remote to switch board and fire-fighting general headquarters
Platform.
Device power-off after re-power, by reading clock chip, can with the power off time of tape deck, power-on time,
The data such as frequency of power cut, can also read at scene data remote to control centre in inspection.