CN107301972A - 半导体结构及其制造方法 - Google Patents
半导体结构及其制造方法 Download PDFInfo
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- CN107301972A CN107301972A CN201611225663.9A CN201611225663A CN107301972A CN 107301972 A CN107301972 A CN 107301972A CN 201611225663 A CN201611225663 A CN 201611225663A CN 107301972 A CN107301972 A CN 107301972A
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- layer
- semiconductor
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Abstract
本发明的提供了半导体结构,其包括:包括第一表面和第二表面的半导体器件层,其中第一表面位于半导体器件层的前侧处,并且第二表面位于半导体器件层的后侧处;位于半导体器件的第二表面之上的绝缘层;以及穿过绝缘层的硅通孔(TSV)。也提供了半导体结构的制造方法。
Description
技术领域
本发明的实施例涉及具有绝缘体上硅结构的半导体结构及其制造方法。
背景技术
绝缘体上硅(SOI)结构可以由厚非活性基底层(通常是但不一定是由硅制成,它提供了机械稳定性)、电绝缘中间层(通常是但不一定是由二氧化硅(SiO2)制成)和高品质的单晶硅的薄顶层(包含例如通过光刻的方法图案化的微电子器件)。存在许多以适当的几何形状的厚膜和薄膜厚度。
SOI衬底,每个都已发现在某些方面缺乏。通常地,目前提出的某些方法将以相对低的产率和相对高的成本产生厚SOI晶圆。目前已经提出的其它方法将产生具有器件层(具有不可接受的变化或包含缺陷)的SOI晶圆。
尽管已经提出了用于制造具有无缺陷的器件层(具有相对低的变化)的SOI晶圆的各个方法,但是这些方法通常以相对高的产率和有利的成本产生SOI晶圆,但是这些方法通常产生厚度变化或包含缺陷。
发明内容
本发明的实施例提供了一种半导体结构,包括:半导体器件层,包括第一表面和第二表面,其中,所述第一表面位于所述半导体器件层的前侧处,以及所述第二表面位于所述半导体器件层的后侧处;绝缘层,位于所述半导体器件层的所述第二表面之上;以及硅通孔(TSV),穿过所述绝缘层。
本发明的另一实施例提供了一种半导体结构的制造方法,包括:提供临时衬底;在所述临时衬底上方形成蚀刻停止层;在所述蚀刻停止层上方 形成半导体器件层;去除所述临时衬底;在所述半导体器件层的后侧上方形成绝缘层;以及形成穿过所述绝缘层的硅通孔(TSV)。
本发明的又一实施例提供了一种半导体结构的制造方法,包括:提供临时衬底;在所述临时衬底上方形成选择层;在所述选择层上方形成半导体器件层;去除所述临时衬底和所述选择层;在所述半导体器件层的后侧上方形成绝缘层;以及形成穿过所述绝缘层的硅通孔(TSV)。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1至图12B示出根据本发明的一些实施例的半导体结构的示意性截面图并且描述了用于制造半导体结构的操作顺序。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下”、“在…之上”、“上”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地作出相应的解释。
尽管阐述本发明的广泛范围的数值范围和参数是近似的,但是应尽可能精确地报告在具体实例中阐述的数值。任何数值,然而,固有地包含在各自的测试测量结果中发现的由标准偏差产生的某些必然误差。同样,正如此处使用的术语“约”一般指在给定值或范围的10%、5%、1%或0.5%内。或者,术语“约”意思是在本领域普通的技术人员可以考虑到的可接受的平均标准误差内。除了在操作/工作的实例中,或除非另有明确规定,诸如用于材料数量、持续时间、温度、操作条件、数额以及本发明此处公开的其他型似物的所有的数值范围、总额、值和百分比,应该被理解为在所有情况下被术语“约”修改。因此,除非有相反规定,本发明和所附权利要求所记载的数值参数设定是可以根据要求改变的近似值。至少,每个数值参数应该至少被解释为根据被报告的有效数字的数目,并应用普通的四舍五入技术。此处范围可以表示为从一个端点到另一个端点或在两个端点之间。此处公开的所有范围包括端点,除非另有说明。
本发明提供了具有逆转绝缘体上硅(SOI)结构(具有穿过SOI结构的绝缘体的硅通孔(TSV))的半导体结构。特别地,TSV将器件层的前侧上的半导体电路连接至器件层的后侧的半导体电路。本发明也提供了在此描述的半导体结构的制造方法。
参照图1至12B,根据本发明的一些实施例描述了用于制造半导体结构的操作顺序。在图1中,提供主衬底10。例如,主衬底10由P-或N-硅衬底组成。这样市售的衬底具有10μm至20μm的所需的厚度均匀性公差。换言之,10μm至20μm的厚度非均匀性。在一些实施例中,主衬底可以大于约700μm厚。在一些实施例中,由于主衬底10在后续操作中将被变薄为小于约5μm,因此在本发明中主衬底10称为临时衬底。在一些实施例中,主衬底10是具有介于约1E18硼原子/cm3和约5E20硼原子/cm3之间的硼(B)浓度,优选地介于约1E18硼原子/cm3至约3E20硼原子/cm3,约0.01欧姆-厘米至约0.02欧姆-厘米的电阻率,优选地介于约0.01欧姆-厘米至约0.015欧姆-厘米的电阻率,介于约300μm至800μm的厚度并且其直径可以是例如100mm、125mm、150mm、200mm或更大的P+晶圆。在一些实施例中,低温氧化物(LTO)层可以位于在主衬底10的底面上并且与主衬底10一起提供。
参照图2至图4,示出了外延三层的形成顺序。在图2中,在主衬底10上方形成外延缓冲层20。在示例性实施例中,外延缓冲层20可以由P-硅外延组成。在示例性实施例中,外延缓冲层20沉积为具有约3.5μm的厚度。在图3中,在外延缓冲层20上方形成蚀刻选择层22。在示例性实施例中,蚀刻选择层22沉积为具有约200nm或更小的厚度,并且通过将元素周期表中的至少一个Ⅲ族至Ⅴ族元素合并入组成外延缓冲层20的相同材料中来呈现蚀刻选择性。在图4中,在蚀刻选择层22上方形成硅外延层24。在示例性实施例中,硅外延层24沉积为具有约100nm或更小的厚度。
外延缓冲层20、蚀刻选择层22和硅外延层24通常构成外延三层,其通过本领域已知的诸如气体源分子束外延(MBE)、超高真空化学汽相沉积(UHVCVD)或低温常压(AP)CVD或其它的汽相沉积的低温技术来外延生长。汽相沉积方法的实例包括热丝CVD、rf-CVD、激光CVD(LCVD)、共形金刚石涂覆操作、金属有机CVD(MOCVD)、热蒸发PVD、离子化金属PVD(IMPVD)、电子束PVD(EBPVD)、反应PVD、原子层沉积(ALD)、等离子体增强CVD(PECVD)、高密度等离子体CVD(HDPCVD)、低压CVD(LPCVD)等。使用电化学反应的沉积的实例包括电镀、化学镀等。沉积的其它实例包括脉冲激光沉积(PLD)以及原子层沉积(ALD)。
在一些实施例中,蚀刻选择层22包括具有比制成外延缓冲层20和硅外延层24的材料更大的晶格常数的硅锗(SiGe)。蚀刻选择层22中的锗可具有约20%的浓度。为了减少错位,锗的浓度可在与位于外延缓冲层20和蚀刻选择层22之间的界面相距40nm的范围内从约0%逐渐增加至约20%。同样地,锗的浓度可在与位于蚀刻选择层22和硅外延层24之间的界面相距40nm的范围内从约20%逐渐减少至约0%。在一些实施例中,依据所需的选择性性能,蚀刻选择层22中的锗可以具有大于或小于20%的浓度。例如,锗的浓度可以在从约20%至约30%的范围内。
在一些实施例中,提供了具有通过扩散或注入到硅中放置的重掺杂的硼区的蚀刻选择层22。蚀刻选择层22可以具有约或大于1E18硼原子/cm3的硼浓度。在一些实施例中,蚀刻选择层22可包括诸如碳(C)、磷(P)、 镓(Ga)、氮(N)或砷(As)的元素周期表的Ⅲ族至Ⅴ族元素的其它掺杂剂。
在图5中,在蚀刻选择层22上方形成层间(或层次间)介电(ILD)层905,其中硅外延层24和ILD层通常形成器件层30。在一些实施例中,外延地生长器件层30并且接着通过各个操作形成例如半导体器件的晶体管区的有源区。器件层30的厚度优选地为约1.5μm至5μm厚并且具有允许使用在此描述的优选的蚀刻剂的导电类型和电阻率类型(例如,n或p-)。通过本领域已知的诸如气体源分子束外延(“MBE”)、超高真空化学汽相沉积(“UHCVD”)或常压化学汽相沉积(“APCVD”)的外延技术在蚀刻选择性层22上方形成器件层30。可以可选地使用诸如高温(例如,至少约900℃)氢气预烘焙的标准预外延清洁步骤。此外,可以在器件层30上可选地形成氧化物层。如图5所示,器件层30包括第一表面301和第二表面302。第一表面301位于器件层30的前侧,并且第二表面302位于器件层30的后侧。在目前的操作中,器件层30的第二表面302与蚀刻选择层22接触。在一些实施例中,半导体器件可包括具有晶体管区和金属化层的至少一个逻辑结构。
器件层30还包括多层互连件(MLI)903。MLI903连接到晶体管区的各个组件。MLI903包括各个导电部件,导电部件可以是诸如接触件和/或通孔的垂直互连件;和/或诸如导电线的水平互连件。各个导电部件包括诸如金属的导电材料。在实例中,可以使用的金属包括铝、铝/硅/铜合金、钛、氮化钛、钨、多晶硅、金属硅化物或它们的组合,并且各种导电部件可以称为铝互连件。可以通过包括物理汽相沉积(PVD)、化学汽相沉积(CVD)或它们的组合的工艺形成铝互连件。形成各个导电部件的其它制造技术可以包括光刻处理和蚀刻以图案化导电材料以形成垂直和水平连接。也可以实施其它制造工艺以形成MLI903,诸如热退火以形成金属硅化物。在多层互连件中使用的金属硅化物可以包括硅化镍、硅化钴、硅化钨、硅化钽、硅化钛、硅化铂、硅化铒、硅化钯或它们的组合。可选地,各个导电部件可以是包括铜、铜合金、钛、氮化钛、钽、氮化钽、钨、多晶硅、金属硅化物或它们的组合的铜多层互连件。可以通过包括PVD、CVD或它们的组 合的工艺形成铜互连件。MLI903不被描述的导电部件的数量、材料、大小和/或尺寸限制,并且因此,依据器件层30的设计要求,MLI903可包括导电部件的任何数量、材料、大小和/或尺寸。
在ILD层905中设置MLI903的各个导电部件。ILD层905可以包括二氧化硅、氮化硅、氮氧化硅、TEOS氧化物、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟化石英玻璃(FSG)、碳掺杂的氧化硅、Black (加利福尼亚州圣克拉拉的应用材料公司)、干凝胶、气凝胶、无定形氟化碳、帕利灵、BCB(双-苯并环丁烯)、SiLK(密歇根州米特兰的陶氏化学公司)、聚酰亚胺、其它合适的材料或它们的组合。ILD层905可以具有多层结构。可以通过包括旋涂、CVD、溅射或其它合适的工艺的技术形成ILD层905。在实例中,可以在包括诸如双镶嵌工艺或单镶嵌工艺的镶嵌工艺的集成工艺中形成MLI层903或ILD层905。
器件层30的第一表面301可以包括外延层以外的层,诸如如图6所示的介电层150或混合层,混合层包括在促进例如接合操作中的介电材料和金属迹线。在图7中,单独制备半导体衬底40,并且半导体衬底40的第三表面403接合到器件层30的介电层150。半导体衬底40包括与第三表面403相对的第四表面404。在一些实施例中,第四表面是404是半导体衬底40的后侧。在一些实施例中,半导体衬底40的第三表面403可以包括诸如介电层或混合层的其它层,混合层包括介电材料和金属迹线。参照图7至图8,半导体衬底40的第三表面403接合到介电层150的第五表面150’。
在一些实施例中,半导体衬底40可以是具有足够的机械强度以进行后续处理的载体衬底。半导体衬底40可以由类似于主衬底10的原始硅衬底组成,例如,P-或N-硅衬底,具有对应于器件层30的直径的直径,所期望的10μm到20μm的厚度均匀性公差。在一些实施例中,由于半导体衬底40仅仅用作处理主衬底10和其上的外延层的工具,半导体衬底40的导电类型和电阻率类型不是关键的。有利地,因此,半导体衬底40可以由很低成本的硅形成。
晶圆接合是本领域已知的并且在此仅简单地讨论。半导体衬底40优选 地包括硅衬底,如之前所讨论的,并且还具有在硅衬底的顶面上形成的氧化物层。在器件层30上方形成的介电层150或金属化层放置为与半导体衬底40接触,使得器件层30的介电层或金属化层与半导体衬底40上方的氧化物层亲密接触。在两个衬底接合在一起之前,可以实施等离子体处理以激活氧化物层的表面用于接合强度的提高。然后,主衬底10和半导体衬底40经受热处理并且持续预定的一段时间,直到氧化物层和介电层或金属化层接合在一起。由于接合界面被等离子体处理,退火热处理温度可下降到低于约400摄氏度。包括主晶圆10及半导体衬底40的接合的晶圆对的所得总厚度变化(TTV)是主衬底10和半导体衬底40的各自TTV的总和。
图9A和图9B根据蚀刻选择层22的成分描绘蚀刻选择层22如何工作的两种情形。在图9A中,蚀刻选择层22包括具有约10%至约100%的锗浓度(原子百分比)的SiGe。在将主衬底10接合到半导体衬底40之后,如图9A所示去除主衬底10和外延缓冲层20。优选地,以两个步骤完成主衬底10和外延缓冲层20的去除,即,研磨主衬底10的约90%,并且然后选择性地蚀刻主衬底10的剩余部分和外延缓冲层20。与研磨、抛光、湿蚀刻和/或化学机械抛光以大幅降低主衬底10的厚度的常规顺序相比,本发明提供了通过仅对结构进行研磨和湿蚀刻操作来完成主衬底10的主要部分的去除。由于主衬底10和包括SiGe的蚀刻选择层22之间的高选择性,蚀刻选择层22可以用作湿蚀刻操作后暴露的突然蚀刻停止层。
本发明的研磨操作可以包括粗磨和精磨。图4中所示的主衬底10的后侧10’使用具有诸如D46砂轮或320粗砂轮的相对粗的砂轮的传统研磨机接地以使主衬底10变薄。在这个粗研磨步骤中,去除主要部分,而不是主衬底10的整个厚度。由粗磨和额外的工艺步骤(消除在粗磨步骤期间产生的粗糙度和损坏所需要的步骤)后硅表面的总粗糙度部分地确定在此粗磨步骤中去除的材料的量。优选地,粗磨步骤后的平均表面粗糙度小于约0.5μm,更优选地,小于约0.3μm,和粗研磨步骤后的总表面粗糙度小于约5μm,更优选地,小于3μm。可以使用表面光度仪以在1平方厘米的面积上方测量的平均粗糙度来确定粗糙地面的平均粗糙度和总表面粗糙度。
为了去除在粗磨步骤中产生的粗糙度和损坏,可以对器件晶圆的表面 优选地进行第二研磨步骤,即,精磨步骤。对于精磨,可以使用1200目的精砂轮。在精磨步骤中去除的材料的量是粗磨步骤后硅表面的总表面粗糙度值的至少约三倍,优选地至少约5倍。然而,精磨给予其粗糙度和对硅表面的损坏并且通常,精磨步骤后硅表面将具有小于0.1μm的平均表面粗糙度,更优选地是小于约0.02μm,和总表面粗糙度小于约0.75μm。可以使用有能力测量纳米或更小的粗糙度值的表面光度仪以在1平方厘米的面积上方测量的平均粗糙度来确定用于精细地面的平均粗糙度和总表面粗糙度,RT。
研磨后,减薄的主衬底10具有暴露的表面和约20μm至约35μm的厚度,更优选地,约25μm至约30μm的厚度。此外,应控制研磨工艺以最小化横过地面晶圆的TTV。对于200毫米直径的晶圆,例如,TTV应小于2微米,优选地小于0.8微米,甚至优选地不超过约0.5微米。
尽管可以通过选择性蚀刻去除主衬底10的剩余的厚度,选择性蚀刻剂以相对低的速率去除硅。为了提高生产量,因此,优选地通过研磨机械地去除主衬底10的大部分并且在湿蚀刻之前去除在研磨工艺中产生的粗糙度和损坏。相对于含SiGe的材料用作蚀刻选择层22的情形,本发明的湿化学蚀刻剂可以包括四甲基氢氧化铵(TMAH)。TMAH可以用于以每分钟约0.2微米的速率在约60摄氏度处平滑研磨剩余的主衬底10和外延缓冲层20。在同样的温度处,具有约20%Ge的蚀刻选择层22的蚀刻速率仅是90埃每分钟。这样,蚀刻选择层22可以用作湿蚀刻操作后暴露的突然蚀刻停止层,并且硅外延层24可保持不变。在一些实施例中,可以进一步去除包括SiGe的蚀刻选择层22。然而,这并不是对本发明的限制。
在蚀刻选择层22包括上述诸如硼、碳、磷和砷的元素周期表的Ⅲ族至Ⅴ族元素的掺杂剂的情况下,硅外延层24可作为突然蚀刻停止层。湿蚀刻前,通过类似于图9A的研磨和抛光去除硼掺杂的蚀刻选择层22下面的大部分主衬底10和外延缓冲层20。然后通过由氢氟酸、硝酸和乙酸以3:5:3的重量比(HF:HNO3:CH3COOH)(通常称为HNA)组成的蚀刻剂选择性地蚀刻硼掺杂的蚀刻选择层22。使用该蚀刻剂,报道的用于重硼掺杂的蚀刻选择层22的蚀刻速率与未掺杂的硅外延层24的蚀刻速率相比,名 义上的选择性比率是100:1。进一步提供第二修整以精调蚀刻表面的粗糙度。如图9B所示,由于重掺杂的蚀刻选择层22已经大致消耗,可以使用第二修整以去除硅外延层24的硅膜的薄层。例如,蚀刻后实施平坦化操作,并且然后将具有相比上述蚀刻剂更低的蚀刻速率的另外的蚀刻剂应用到粗糙的表面以获得期望的表面粗糙度。上述第二修整不能缓解上述的大表面粗糙度。
图10A、11A和12A是基于图9A的情况描述用于制造半导体结构的操作顺序的示意性截面图。在图10A中,在图9A的蚀刻选择层22的暴露的表面上方形成诸如氧化物层的介电层180。在一些实施例中,根据在此描述的一些制造方法可以测量介电层180和蚀刻选择层22之间的总厚度变化(TTV)是约150nm。提供的介电层180可以用作绝缘层以与器件层30一起形成逆转SOI结构。在图11A中,图案化导通孔190并且从介电层180的表面蚀刻,穿过蚀刻选择层22、器件层30,并且到达设计为接收导通孔的特定的MLI903。在图12A中,将导电材料填充入导通孔190中并且在半导体结构200中形成硅通孔(TSV)201。通常地,通过蚀刻穿过衬底的垂直的孔并且用诸如铜的导电材料填充孔来形成TSV201。TSV201可以用于提供器件层30的前侧上的半导体电路上方至器件层30的后侧上的半导体电路的电接触,或者提供至堆叠管芯(未示出)上的半导体电路的电接触。通常地,用于形成TSV201的工艺包括蚀刻至少部分地穿过器件层30的硅衬底、可能地,上面的介电层180、185、下面的ILD905的孔,并且然后在孔中沉积铜。相对于现有的SOI结构,图12A的半导体结构200可以看作逆转SOI结构。
图10B、11B和12B是基于图9B的情况描述用于制造半导体结构的操作顺序的示意性截面图。在图10B中,在图9B的硅外延层24的暴露的表面上方形成诸如氧化物层的介电层180。在一些实施例中,根据在此描述的一些制造方法可以测量介电层180和硅外延层24之间的总厚度变化(TTV)是约10nm。提供的介电层180可以用作绝缘层以与器件层30一起形成逆转SOI结构。在图11B中,图案化导通孔190并且从介电层180的表面蚀刻,穿过器件层30,并且到达设计为接收导通孔的特定的MLI903。 在图12B中,将导电材料填充入导通孔190中并且在半导体结构202中形成TSV201。通常地,通过蚀刻穿过衬底的垂直的孔并且用诸如铜的导电材料填充孔来形成TSV201。TSV201可以用于提供器件层30的前侧上方至器件层30的后侧上的半导体电路的电接触,或者提供至堆叠管芯(未示出)上的半导体电路的电接触。通常地,用于形成TSV201的工艺包括蚀刻至少部分地穿过器件层30的硅衬底、可能地,上面的介电层180、185、下面的ILD905的孔,并且然后在孔中沉积铜。相对于现有的SOI结构,图12B的半导体结构202可以看做逆转SOI结构。
本发明的实施例提供了半导体结构,其包括:包括第一表面和第二表面的半导体器件层,其中第一表面位于半导体器件层的前侧处,并且第二表面位于半导体器件层的后侧处;绝缘层位于半导体器件的第二表面之上;以及穿过绝缘层的硅通孔(TSV)。
在上述半导体结构中,还包括外延层,所述外延层包括位于所述半导体器件层和所述绝缘层之间的硅锗(SiGe)。
本发明的实施例提供了一种半导体结构的制造方法。该方法包括:提供了临时衬底;在临时衬底上方形成蚀刻停止层;在蚀刻停止层上方形成半导体器件层;去除临时衬底;在半导体器件层的后侧上方形成绝缘层;以及形成穿过绝缘层的硅通孔(TSV)。
在上述制造方法中,还包括在去除所述临时衬底之前,将载体衬底接合至所述半导体器件层的前侧。
在上述制造方法中,其中,所述临时衬底的去除包括研磨所述临时衬底。
在上述制造方法中,其中,所述临时衬底上方的所述蚀刻停止层的形成包括形成硅锗(SiGe)。
在上述制造方法中,其中,所述临时衬底上方的所述蚀刻停止层的形成包括形成硅锗(SiGe),形成所述硅锗(SiGe)包括控制Ge的浓度在从10%至100%的范围。
在上述制造方法中,其中,所述临时衬底上方的所述蚀刻停止层的形成包括形成硅锗(SiGe),所述临时衬底的去除包括实施四甲基氢氧化铵(TMAH)蚀刻。
在上述制造方法中,还包括在去除所述临时衬底后,去除所述蚀刻停止层。
在上述制造方法中,其中,所述半导体器件层的形成包括形成晶体管区。
在上述制造方法中,其中,所述半导体器件层的形成包括形成多层互连件(MLI)。
在上述制造方法中,其中,穿过所述绝缘层的硅通孔的形成包括形成所述硅通孔以将所述半导体器件层连接至位于所述半导体器件层的后侧上的半导体电路。
在上述制造方法中,还包括在所述蚀刻停止层形成之前形成缓冲层。
本发明的实施例提供了一种半导体结构的制造方法。该方法包括:提供了临时衬底;在临时衬底上方形成选择层;在选择层上方形成半导体器件层;去除临时衬底和选择层;在半导体器件层的后侧上方形成绝缘层;以及形成穿过绝缘层的硅通孔(TSV)。
在上述制造方法中,其中,所述临时衬底的去除包括研磨所述临时衬底。
在上述制造方法中,其中,所述临时衬底上方的所述选择层的形成包括将Ⅲ族、Ⅳ族、Ⅴ族的一种元素合并入所述蚀刻停止层。
在上述制造方法中,其中,所述临时衬底上方的所述选择层的形成包括将Ⅲ族、Ⅳ族、Ⅴ族的一种元素合并入所述蚀刻停止层,将Ⅲ族、Ⅳ族、Ⅴ族的一种元素合并入所述蚀刻停止层包括将硼(B)、碳(C)、磷(P)、镓(Ga)、氮(N)和砷(As)的至少一种合并入所述蚀刻停止层。
上述制造方法中,其中,所述临时衬底上方的所述选择层的形成包括将Ⅲ族、Ⅳ族、Ⅴ族的一种元素合并入所述蚀刻停止层,将Ⅲ族、Ⅳ族、Ⅴ族的一种元素合并入所述蚀刻停止层包括将硼(B)、碳(C)、磷(P)、镓(Ga)、氮(N)和砷(As)的至少一种合并入所述蚀刻停止层,将硼合并入所述蚀刻停止层包括控制硼的浓度为至少1E18原子/cm3。
上述制造方法中,其中,所述临时衬底的去除包括实施氢氟酸/硝酸/ 乙酸(HNA)蚀刻。
上述制造方法中,其中,穿过所述绝缘层的硅通孔的形成包括形成所述硅通孔以将所述半导体器件层连接至位于所述半导体器件层的后侧上的半导体电路。
虽然已详细地描述了本发明及其优点,但应了解在不背离通过所附权利要求限定的本发明的精神和范围的情况下,可以对本发明作出各种变化、替代和修改。例如,上述许多工艺可按照不同方法实施并且可被其他工艺或其组合替换。
此外,本申请的范围不旨在限制说明书中所述的工艺、机器、制造、物质组成、工具、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明应很容易理解,根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此,所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。
Claims (1)
1.一种半导体结构,包括:
半导体器件层,包括第一表面和第二表面,其中,所述第一表面位于所述半导体器件层的前侧处,以及所述第二表面位于所述半导体器件层的后侧处;
绝缘层,位于所述半导体器件层的所述第二表面之上;以及
硅通孔(TSV),穿过所述绝缘层。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108233964A (zh) * | 2016-12-14 | 2018-06-29 | 通用汽车环球科技运作有限责任公司 | 采用硅锗四硅通孔技术的紧凑型3d接收机架构 |
CN110504240A (zh) * | 2018-05-16 | 2019-11-26 | 联华电子股份有限公司 | 半导体元件及其制造方法 |
CN110875241A (zh) * | 2018-08-29 | 2020-03-10 | 台湾积体电路制造股份有限公司 | 用于形成绝缘体上半导体(soi)衬底的方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220093466A1 (en) * | 2020-09-24 | 2022-03-24 | Tokyo Electron Limited | Epitaxial high-k etch stop layer for backside reveal integration |
US20220223425A1 (en) * | 2021-01-08 | 2022-07-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | By-site-compensated etch back for local planarization/topography adjustment |
CN112820805A (zh) * | 2021-02-19 | 2021-05-18 | 福建兆元光电有限公司 | 一种芯片外延层结构及其制造方法 |
CN113580557A (zh) * | 2021-07-28 | 2021-11-02 | 沛顿科技(深圳)有限公司 | 一种tsv工艺中替代ncf的3d打印方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5013681A (en) * | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
CN1630933A (zh) * | 2002-02-11 | 2005-06-22 | 国际商业机器公司 | 采用uhv-cvd制作的应变si基底层以及其中的器件 |
US20120193752A1 (en) * | 2011-01-29 | 2012-08-02 | International Business Machines Corporation | Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby |
CN103515355A (zh) * | 2012-06-29 | 2014-01-15 | 联华电子股份有限公司 | 半导体元件与其制作方法 |
CN104810396A (zh) * | 2014-01-23 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5218213A (en) * | 1991-02-22 | 1993-06-08 | Harris Corporation | SOI wafer with sige |
US5906951A (en) * | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
US6633066B1 (en) * | 2000-01-07 | 2003-10-14 | Samsung Electronics Co., Ltd. | CMOS integrated circuit devices and substrates having unstrained silicon active layers |
US6940089B2 (en) * | 2001-04-04 | 2005-09-06 | Massachusetts Institute Of Technology | Semiconductor device structure |
US7670927B2 (en) * | 2006-05-16 | 2010-03-02 | International Business Machines Corporation | Double-sided integrated circuit chips |
JP5442394B2 (ja) * | 2009-10-29 | 2014-03-12 | ソニー株式会社 | 固体撮像装置とその製造方法、及び電子機器 |
EP2333824B1 (en) * | 2009-12-11 | 2014-04-16 | Soitec | Manufacture of thin SOI devices |
US9105588B2 (en) * | 2010-10-21 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor component having a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer |
JP2012146861A (ja) * | 2011-01-13 | 2012-08-02 | Toshiba Corp | 半導体記憶装置 |
US9689835B2 (en) * | 2011-10-31 | 2017-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Amplified dual-gate bio field effect transistor |
US9299640B2 (en) * | 2013-07-16 | 2016-03-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Front-to-back bonding with through-substrate via (TSV) |
-
2016
- 2016-04-15 US US15/130,182 patent/US11049797B2/en active Active
- 2016-12-27 CN CN201611225663.9A patent/CN107301972B/zh active Active
-
2021
- 2021-06-11 US US17/346,186 patent/US20210305131A1/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5013681A (en) * | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
CN1630933A (zh) * | 2002-02-11 | 2005-06-22 | 国际商业机器公司 | 采用uhv-cvd制作的应变si基底层以及其中的器件 |
US20120193752A1 (en) * | 2011-01-29 | 2012-08-02 | International Business Machines Corporation | Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby |
CN103515355A (zh) * | 2012-06-29 | 2014-01-15 | 联华电子股份有限公司 | 半导体元件与其制作方法 |
CN104810396A (zh) * | 2014-01-23 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108233964A (zh) * | 2016-12-14 | 2018-06-29 | 通用汽车环球科技运作有限责任公司 | 采用硅锗四硅通孔技术的紧凑型3d接收机架构 |
CN110504240A (zh) * | 2018-05-16 | 2019-11-26 | 联华电子股份有限公司 | 半导体元件及其制造方法 |
US10903314B2 (en) | 2018-05-16 | 2021-01-26 | United Microelectronics Corp. | Semiconductor device and method for manufacturing the same |
CN110504240B (zh) * | 2018-05-16 | 2021-08-13 | 联华电子股份有限公司 | 半导体元件及其制造方法 |
US11398548B2 (en) | 2018-05-16 | 2022-07-26 | United Microelectronics Corp. | Semiconductor device |
CN110875241A (zh) * | 2018-08-29 | 2020-03-10 | 台湾积体电路制造股份有限公司 | 用于形成绝缘体上半导体(soi)衬底的方法 |
CN110875241B (zh) * | 2018-08-29 | 2023-09-19 | 台湾积体电路制造股份有限公司 | 用于形成绝缘体上半导体(soi)衬底的方法 |
US11830764B2 (en) | 2018-08-29 | 2023-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming a semiconductor-on-insulator (SOI) substrate |
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US20210305131A1 (en) | 2021-09-30 |
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US11049797B2 (en) | 2021-06-29 |
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