CN107293555A - The preparation method and its structure of bottom emitting type white light OLED panel - Google Patents
The preparation method and its structure of bottom emitting type white light OLED panel Download PDFInfo
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- CN107293555A CN107293555A CN201710466286.6A CN201710466286A CN107293555A CN 107293555 A CN107293555 A CN 107293555A CN 201710466286 A CN201710466286 A CN 201710466286A CN 107293555 A CN107293555 A CN 107293555A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 65
- 239000004020 conductor Substances 0.000 claims abstract description 60
- 239000010408 film Substances 0.000 claims abstract description 60
- 239000012212 insulator Substances 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 39
- 230000008569 process Effects 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000010409 thin film Substances 0.000 claims abstract description 18
- 238000003851 corona treatment Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 183
- 239000011229 interlayer Substances 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 238000002161 passivation Methods 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 238000010276 construction Methods 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 8
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 8
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 8
- 229910052750 molybdenum Inorganic materials 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 230000000903 blocking effect Effects 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- HRHKULZDDYWVBE-UHFFFAOYSA-N indium;oxozinc;tin Chemical compound [In].[Sn].[Zn]=O HRHKULZDDYWVBE-UHFFFAOYSA-N 0.000 claims description 4
- 239000011787 zinc oxide Substances 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 238000012545 processing Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 12
- 229910004205 SiNX Inorganic materials 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- -1 IGZO) Chemical compound 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000003086 colorant Substances 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000027756 respiratory electron transport chain Effects 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004040 coloring Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The present invention provides a kind of preparation method and its structure of bottom emitting type white light OLED panel.On the one hand thin film transistor (TFT) is produced on same underlay substrate by the preparation method of the bottom emitting type white light OLED panel with color film layer, without setting polaroid, can reduce cost of manufacture；On the other hand the corona treatment for carrying out whole face after grid and gate insulator to the oxide semiconductor layer is produced on oxide semiconductor layer, so that the partial ohmic that the oxide semiconductor layer is not blocked by the grid and gate insulator is reduced, form conductor layer, and the part blocked by grid and gate insulator is still semiconductor, form semiconductor channel area, the anode of white light OLED is used as using the conductor layer, the gold-tinted and etch process that anode is fabricated separately can be saved, light shield layer can be saved in addition, flatness layer, with the preparation of pixel defining layer, so as to simplify process, reduce gold-tinted processing procedure road number, save light shield quantity, further reduce cost of manufacture.
Description
Technical field
The present invention relates to OLED display technology fields, more particularly to a kind of preparation method of bottom emitting type white light OLED panel
And its structure.
Background technology
In display technology field, liquid crystal display panel (Liquid Crystal Display, LCD) and organic light-emitting diodes
The panel display apparatus such as pipe display panel (Organic Light Emitting Diode, OLED) progressively penetrate by substitution negative electrode
Spool (Cathode Ray Tube, CRT) display.
Wherein, oled panel have that self-luminous, driving voltage are low, luminous efficiency is high, the response time is short, definition and contrast
High, the nearly 180 ° of visual angles of degree, temperature in use scope are wide, many advantages, such as Flexible Displays are with large area total colouring can be achieved, by industry
Boundary is known as being the display device for most having development potentiality.
Existing oled panel is generally included：Substrate, be placed in the ito thin film being only used on substrate as anode, be placed in ITO sun
Hole injection layer (HIL) on extremely, hole transmission layer (HTL), the hair being placed on hole transmission layer being placed on hole injection layer
Photosphere (EML), the electron transfer layer (ETL) being placed on luminescent layer, the electron injecting layer (EIL) being placed on electron transfer layer and
The negative electrode being placed on electron injecting layer, in order to improve efficiency, luminescent layer generally uses master/object doped system.
At present, the making of oled panel has two kinds of technology paths：One kind is RGB (Red, Green, Blue, RGB) three
Primary colours OLED lights, and its advantage is that technique is simply ripe, easy to operate but due to needing height when preparing sharpness screen
Precision mask and accurate contraposition, cause that production capacity is relatively low, cost is higher, and life-span due to RGB three primary colours OLED, firing rate
And dough softening difference is larger, easily causes the colour cast of oled panel.
Another is white light OLED technology, it is not necessary to which mask is aligned, and generally uses bottom emitting type illumination mode, greatly simple
Evaporation process is changed, can be used in preparing large scale high-resolution oled panel.
However, existing bottom emitting type white light OLED generally requires polaroid (Polarizer), and the quantity of each structure sheaf
It is more, such as light shield layer, flatness layer, pixel defining layer, add by single one of gold-tinted processing procedure specially to make anode, it is existing
The preparation method of some bottom emitting type white light OLEDs needs more light shield number, and more numerous and diverse process prepares cost higher.
The content of the invention
It is an object of the invention to provide a kind of preparation method of bottom emitting type white light OLED panel, process can be simplified,
Gold-tinted processing procedure road number is reduced, light shield quantity is saved, cost of manufacture is reduced.
Another object of the present invention is to provide a kind of bottom emitting type white light OLED panel construction, its is simple in construction, makes
Cost is low.
To achieve the above object, present invention firstly provides a kind of preparation method of bottom emitting type white light OLED panel, including
Following steps：
Step S1, provide underlay substrate simultaneously clean, be sequentially depositing on the underlay substrate red color resistance, green color blocking,
And blue color blocking, form color film layer；
Step S2, the buffer layer in the color film layer；
Step S3, on the cushion deposition oxide semiconductive thin film and patterned process is carried out, form oxide
Semiconductor layer；
Step S4, on the oxide semiconductor layer and cushion it is sequentially depositing insulation film and the first metal layer；
Step S5, patterned process first is carried out to the first metal layer, grid is formed, then using the grid as autoregistration
Figure etches insulation film, forms the gate insulator being located at below the grid；The grid is blocked with gate insulator
Partial oxide semiconductor layer, exposes the both sides of oxide semiconductor layer；
Step S6, the corona treatment that whole face is carried out to the oxide semiconductor layer so that the oxide is partly led
The partial ohmic that body layer is not blocked by the grid and gate insulator is reduced, and forms conductor layer, and by the grid and grid
The part that insulating barrier is blocked still is semiconductor, forms semiconductor channel area；
Step S7, deposit interlayer insulating film on the grid, conductor layer and cushion and carry out patterned process, shape
Determined into through the interlayer insulating film with the source contact openings, drain contact hole and pixel that expose conductor layer portion surface respectively
Adopted hole；The source contact openings are located at the both sides of the grid and gate insulator with drain contact hole respectively, and the pixel is determined
Adopted hole is close to the source contact openings；
Step S8, on the interlayer insulating film depositing second metal layer and patterned process is carried out, form source electrode and leakage
Pole, the source electrode contacts the conductor layer through the source contact openings, and the drain electrode described in drain contact hole contact through leading
Body layer；
The source electrode, drain electrode, grid, gate insulator, the conductor layer portion with the source contact, with it is described drain electrode connect
Tactile conductor layer portion and semiconductor channel area constitute thin film transistor (TFT)；
Step S9, on the source electrode, drain electrode and interlayer insulating film deposit passivation layer and patterned process is carried out, formed
Expose the through hole in the pixel definition hole；
Step S10, by anode of the conductor layer the pixel definition inner hole deposition accumulate white light OLED luminescent layer；
Step S11, the deposited metal negative electrode on the white light OLED luminescent layer and passivation layer.
The material of cushion is silica or silicon nitride in the step S2, and thickness is
The material of oxide semiconductor thin-film is indium gallium zinc oxide, indium zinc tin oxide, indium gallium zinc in the step S3
One kind in tin-oxide, thickness is
The material of insulation film is silica or silicon nitride in the step S4, and thickness is
The material of the first metal layer is one or more of stacked combinations in molybdenum, aluminium, copper, titanium in the step S5, thick
Spend and be
The step S6 carries out corona treatment using helium or argon gas.
The material of interlayer insulating film is silica or silicon nitride in the step S7, and thickness is
The material of second metal layer is one or more of stacked combinations in molybdenum, aluminium, copper, titanium in the step S8, thick
Spend and be
The material of passivation layer is silica or silicon nitride in the step S9, and thickness is
The present invention also provides a kind of bottom emitting type white light OLED panel construction, including：
Underlay substrate；
Cover the color film layer of the underlay substrate；
Cover the cushion of the color film layer；
The semiconductor channel area that is located on the cushion and the conductor for connecting the semiconductor channel area both sides respectively
Layer；
Cover the gate insulator of the semiconductor channel area；
Cover the grid of the gate insulator；
The interlayer insulating film on the grid, conductor layer and cushion is located at, the interlayer insulating film, which has, runs through the layer
Between insulating barrier to expose the source contact openings, drain contact hole and pixel definition hole on conductor layer portion surface, the source respectively
Pole contact hole is located at the both sides of the grid and gate insulator with drain contact hole respectively, and the pixel definition hole is close to described
Source contact openings；
The source electrode being located on the interlayer insulating film and drain electrode, the source electrode described in source contact openings contact through leading
Body layer, the drain electrode contacts the conductor layer through the drain contact hole；
The passivation layer on the source electrode, drain electrode and interlayer insulating film is located at, the passivation layer, which has, exposes the pixel
Define the through hole in hole；
It is located at the white light OLED luminescent layer in the pixel definition hole and by anode of the conductor layer；
And it is located at the white light OLED luminescent layer and the metallic cathode on passivation layer；
The source electrode, drain electrode, grid, gate insulator, the conductor layer portion with the source contact, with it is described drain electrode connect
Tactile conductor layer portion and semiconductor channel area constitute thin film transistor (TFT).
Beneficial effects of the present invention：A kind of preparation method for bottom emitting type white light OLED panel that the present invention is provided, a side
Thin film transistor (TFT) is produced on same underlay substrate by face with color film layer, without setting polaroid, can reduce cost of manufacture；Separately
On the one hand produced on oxide semiconductor layer and whole face is carried out to the oxide semiconductor layer after grid and gate insulator
Corona treatment so that the partial ohmic that the oxide semiconductor layer is not blocked by the grid and gate insulator drops
It is low, conductor layer is formed, and the part blocked by the grid and gate insulator is still semiconductor, forms semiconductor channel area,
Using the conductor layer as the anode of white light OLED, the gold-tinted and etch process that anode is fabricated separately can be saved, can be saved in addition
Light shield layer, flatness layer, the preparation with pixel defining layer are gone, so as to simplify process, gold-tinted processing procedure road number is reduced, saves light shield
Quantity, further reduces cost of manufacture.A kind of bottom emitting type white light OLED panel construction that the present invention is provided, by above method system
Form, simple in construction, low manufacture cost.
Brief description of the drawings
In order to be able to be further understood that the feature and technology contents of the present invention, refer to below in connection with the detailed of the present invention
Illustrate and accompanying drawing, however accompanying drawing only provide with reference to and explanation use, not for being any limitation as to the present invention.
In accompanying drawing,
Fig. 1 is the flow chart of the preparation method of the bottom emitting type white light OLED panel of the present invention；
Fig. 2 is the step S1 of the preparation method of the bottom emitting type white light OLED panel of present invention schematic diagram；
Fig. 3 is the step S2 of the preparation method of the bottom emitting type white light OLED panel of present invention schematic diagram；
Fig. 4 is the step S3 of the preparation method of the bottom emitting type white light OLED panel of present invention schematic diagram；
Fig. 5 is the step S4 of the preparation method of the bottom emitting type white light OLED panel of present invention schematic diagram；
Fig. 6 is the step S5 of the preparation method of the bottom emitting type white light OLED panel of present invention schematic diagram；
Fig. 7 is the step S6 of the preparation method of the bottom emitting type white light OLED panel of present invention schematic diagram；
Fig. 8 is the step S7 of the preparation method of the bottom emitting type white light OLED panel of present invention schematic diagram；
Fig. 9 is the step S8 of the preparation method of the bottom emitting type white light OLED panel of present invention schematic diagram；
Figure 10 is the step S9 of the preparation method of the bottom emitting type white light OLED panel of present invention schematic diagram；
Figure 11 is the step S10 of the preparation method of the bottom emitting type white light OLED panel of present invention schematic diagram；
Schematic diagram and the present invention that Figure 12 is the step S11 of the preparation method of the bottom emitting type white light OLED panel of the present invention
Bottom emitting type white light OLED panel construction schematic diagram.
Embodiment
Further to illustrate the technological means and its effect of the invention taken, below in conjunction with being preferable to carry out for the present invention
Example and its accompanying drawing are described in detail.
Referring to Fig. 1, present invention firstly provides a kind of preparation method of bottom emitting type white light OLED panel, including following step
Suddenly：
Step S1, there is provided underlay substrate 1 and clean as shown in Figure 2, red color is sequentially depositing on the underlay substrate 1
R, green color blocking G and blue color blocking B are hindered, color film layer (Color Filter, CF) 2 is formed.
Specifically, the preferred glass substrate of the underlay substrate 1.
Step S2, as shown in figure 3, in the color film layer 2 buffer layer 3.
Specifically, in step S2, the material of cushion 3 is silica (SiOx) or silicon nitride (SiNx), and thickness is
Step S3, as shown in figure 4, deposition oxide semiconductive thin film and carry out patterned process on the cushion 3,
Form oxide semiconductor layer 4 '.
Specifically, in step S3, the material of oxide semiconductor thin-film can be indium gallium zinc oxide (Indium
Gallium Zinc Oxide, IGZO), indium zinc tin oxide (Indium Zinc Tin Oxide, IZTO), indium gallium zinc-tin oxygen
One kind in compound (Indium Gallium Zinc Tin Oxide, IGZTO), thickness is
Step S4, as shown in figure 5, be sequentially depositing on the oxide semiconductor layer 4 ' and cushion 3 insulation film 5 ',
With the first metal layer 6 '.
Specifically, in step S4, the material of insulation film 5 ' is SiOx or SiNx, and thickness isThe material of the first metal layer is the one or more in molybdenum (Mo), aluminium (Al), copper (Cu), titanium (Ti)
Stacked combination, thickness is
Step S5, as shown in fig. 6, first pass through gold-tinted, etch process to the first metal layer 6 ' carry out patterned process,
Grid 6 is formed, then insulation film 5 ' is etched so that the grid 6 is autoregistration figure, the grid for being located at the lower section of grid 6 are formed
Pole insulating barrier 5.
Further, the grid 6 and the shield portions oxide semiconductor layer 4 ' of gate insulator 5, expose oxide
The both sides of semiconductor layer 4 '.
Step S6, as shown in fig. 7, carrying out plasma (Plasma) place in whole face to the oxide semiconductor layer 4 '
Reason so that the partial ohmic that the oxide semiconductor layer 4 ' is not blocked by the grid 6 and gate insulator 5 is reduced, is formed
Conductor layer 41, and the part blocked by the grid 6 and gate insulator 5 is still semiconductor, forms semiconductor channel area 42.
Specifically, step S6 carries out corona treatment using helium (He) or argon gas (Ar).
Step S7, interlayer insulating film 7 and lead to as shown in figure 8, being deposited on the grid 6, conductor layer 41 and cushion 3
Cross gold-tinted, etch process and carry out patterned process, formed through the interlayer insulating film 7 to expose the part table of conductor layer 41 respectively
Source contact openings 71, drain contact hole 72 and the pixel definition hole 73 in face.
Further, the source contact openings 71 are located at the grid 6 and gate insulator 5 respectively with drain contact hole 72
Both sides, the pixel definition hole 73 is close to the source contact openings 71.
Specifically, in step S7, the material of interlayer insulating film 7 is SiOx or SiNx, and thickness is
Step S8, as shown in figure 9, depositing second metal layer and passing through gold-tinted, etch process on the interlayer insulating film 7
Patterned process is carried out, source S and drain D is formed.The source S contacts the conductor layer 41 through the source contact openings 71,
The drain D contacts the conductor layer 41 through the drain contact hole 72.
The source S, drain D, grid 6, gate insulator 5, the part of conductor layer 41 contacted with the source S and institute
The part of conductor layer 41 and semiconductor channel area 42 for stating drain D contact constitute thin film transistor (TFT) T.
Specifically, in step S8, the material of second metal layer is one or more of stacking groups in Mo, Al, Cu, Ti
Close, thickness is
Step S9, as shown in Figure 10, deposit passivation layer 9 and passes through on the source S, drain D and interlayer insulating film 7
Gold-tinted, etch process carry out patterned process, form the through hole 91 for exposing the pixel definition hole 73.
Specifically, in step S9, the material of passivation layer 9 is SiOx or SiNx, and thickness is
Step S10, as shown in figure 11, is anode deposition white light in the pixel definition hole 73 with the conductor layer 41
OLED luminescent layers 10.
Step S11, on the white light OLED luminescent layer 10 and passivation layer 9 in the way of hot evaporation or sputter deposited metal
Negative electrode 11.
So far, the making of bottom emitting type white light OLED panel is completed.
The preparation method of the bottom emitting type white light OLED panel of the present invention, on the one hand using TOC (Transistor On
Color Filter) thin film transistor (TFT) T is produced on same underlay substrate 1 by technology with color film layer 2, white light OLED luminescent layer 10
The white light sent carries out colored display after being filtered through color film layer 2, without setting polaroid, can reduce cost of manufacture；The opposing party
Produced on oxide semiconductor layer 4 ' whole to the oxide semiconductor layer 4 ' progress after grid 6 and gate insulator 5 in face
The corona treatment in face so that the part that the oxide semiconductor layer 4 ' is not blocked by the grid 6 and gate insulator 5
Resistance is reduced, and forms conductor layer 41, and the part blocked by the grid 6 and gate insulator 5 is still semiconductor, and formation is partly led
Bulk channel area 42, using the conductor layer 41 as the anode of white light OLED, can save the gold-tinted that anode is fabricated separately and etching
Processing procedure, in addition, light shield layer, flatness layer, the preparation with pixel defining layer are also eliminated, with the pixel definition in interlayer insulating film 7
Pixel region is defined in hole 73, can simplify process, reduces by 4 road gold-tinted processing procedure road numbers, saves 4 light shields, further reduction system
Make cost.
Figure 12 is referred to, based on same inventive concept, the present invention also provides a kind of bottom emitting type as made from the above method
White light OLED panel construction, including：
Underlay substrate 1；
Cover the color film layer 2 of the underlay substrate 1；
Cover the cushion 3 of the color film layer 2；
The semiconductor channel area 42 that is located on the cushion 3 and the both sides of semiconductor channel area 42 are connected respectively
Conductor layer 41；
Cover the gate insulator 5 of the semiconductor channel area 42；
Cover the grid 6 of the gate insulator 5；
The interlayer insulating film 7 on the grid 6, conductor layer 41 and cushion 3 is located at, the interlayer insulating film 7, which has, to be passed through
The interlayer insulating film 7 is worn to expose the source contact openings 71, drain contact hole 72 and pixel of the part surface of conductor layer 41 respectively
Hole 73 is defined, the source contact openings 71 are located at the both sides of the grid 6 and gate insulator 5 with drain contact hole 72 respectively,
The pixel definition hole 73 is close to the source contact openings 71；
Source S and drain D on the interlayer insulating film 7 are located at, the source S is contacted through the source contact openings 71
The conductor layer 41, the drain D contacts the conductor layer 41 through the drain contact hole 72；
The passivation layer 9 on the source S, drain D and interlayer insulating film 7 is located at, the passivation layer 9, which has, exposes institute
State the through hole 91 in pixel definition hole 73；
It is located in the pixel definition hole 73 and with white light OLED luminescent layer 10 of the conductor layer 41 for anode；
And it is located at the white light OLED luminescent layer 10 and the metallic cathode 11 on passivation layer 9.
Wherein, the source S, drain D, grid 6, gate insulator 5, the part of conductor layer 41 contacted with the source S,
The part of conductor layer 41 contacted with the drain D and semiconductor channel area 42 constitute thin film transistor (TFT) T；
As described in the step S6 in above-mentioned method, the semiconductor channel area 42 and the semiconductor channel is connected respectively
The conductor layer 4 of the both sides of area 42 is obtained by carrying out the corona treatment in whole face to oxide semiconductor layer 4 ', the oxide
The partial ohmic that semiconductor layer 4 ' is not blocked by the grid 6 and gate insulator 5 is reduced, and forms conductor layer 41, and described
The part that grid 6 and gate insulator 5 are blocked still is semiconductor, forms semiconductor channel area 42.
The bottom emitting type white light OLED panel construction of the present invention, same substrate is arranged on by thin film transistor (TFT) T with color film layer 2
On substrate 1, the white light that white light OLED luminescent layer 10 is sent carries out colored display after being filtered through color film layer 2, without setting polaroid,
Cost of manufacture is relatively low；Using with semiconductor channel area 42 be located at the other conductor layer 41 of same layer as white light OLED anode, without
Single anode is specially set, in addition, light shield layer, flatness layer, the setting with pixel defining layer are also eliminated, with interlayer insulating film
Pixel region is defined in pixel definition hole 73 in 7, not only simplify structure, additionally it is possible to further reduce cost of manufacture.
Specifically：The preferred glass substrate of the underlay substrate 1；
The material of the cushion 3 is SiOx or SiNx, and thickness is
The original material of the conductor layer 41 and semiconductor channel area 42 is one kind in IGZO, IZTO, IGZTO, thickness
For
The material of the gate insulator 5 is SiOx or SiNx, and thickness is
The material of the grid 6 is one or more of stacked combinations in Mo, Al, Cu, Ti, and thickness is
The material of the interlayer insulating film 7 is SiOx or SiNx, and thickness is
The material of the source S and drain D is one or more of stacked combinations in Mo, Al, Cu, Ti, and thickness is
The material of the passivation layer 9 is SiOx or SiNx, and thickness is
In summary, the preparation method of bottom emitting type white light OLED panel of the invention, on the one hand by thin film transistor (TFT) with
Color film layer is produced on same underlay substrate, without setting polaroid, can reduce cost of manufacture；On the other hand in oxide half
The corona treatment for carrying out whole face after grid and gate insulator to the oxide semiconductor layer is produced in conductor layer, is made
The partial ohmic reduction that the oxide semiconductor layer is not blocked by the grid and gate insulator is obtained, conductor layer is formed, and
The part blocked by the grid and gate insulator still be semiconductor, formed semiconductor channel area, using the conductor layer as
The anode of white light OLED, can save the gold-tinted and etch process that anode is fabricated separately, can save in addition light shield layer, flatness layer,
With the preparation of pixel defining layer, so as to simplify process, gold-tinted processing procedure road number is reduced, light shield quantity is saved, further reduction
Cost of manufacture.
It is described above, for the person of ordinary skill of the art, can be with technique according to the invention scheme and technology
Other various corresponding changes and deformation are made in design, and all these changes and deformation should all belong to the claim of the present invention
Protection domain.
Claims (10)
1. a kind of preparation method of bottom emitting type white light OLED panel, it is characterised in that comprise the following steps：
Step S1, offer underlay substrate (1) are simultaneously cleaned, and red color resistance (R), green are sequentially depositing on the underlay substrate (1)
Color blocking (G) and blue color blocking (B), form color film layer (2)；
Step S2, the buffer layer (3) on the color film layer (2)；
Step S3, on the cushion (3) deposition oxide semiconductive thin film and patterned process is carried out, form oxide half
Conductor layer (4 ')；
Step S4, be sequentially depositing on the oxide semiconductor layer (4 ') and cushion (3) insulation film (5 '), with the first gold medal
Belong to layer (6 ')；
Step S5, patterned process first is carried out to the first metal layer (6 '), form grid (6), then be with the grid (6)
Autoregistration figure etches insulation film (5 '), forms the gate insulator (5) being located at below the grid (6)；The grid
(6) with gate insulator (5) shield portions oxide semiconductor layer (4 '), the both sides of oxide semiconductor layer (4 ') are exposed；
Step S6, the corona treatment that whole face is carried out to the oxide semiconductor layer (4 ') so that the oxide is partly led
The partial ohmic that body layer (4 ') is not blocked by the grid (6) and gate insulator (5) is reduced, formation conductor layer (41), and by
The part that the grid (6) and gate insulator (5) are blocked still is semiconductor, forms semiconductor channel area (42)；
Step S7, deposit interlayer insulating film on the grid (6), conductor layer (41) and cushion (3) and (7) and carry out pattern
Change handle, formed through the interlayer insulating film (7) with expose respectively conductor layer (41) part surface source contact openings (71),
Drain contact hole (72) and pixel definition hole (73)；The source contact openings (71) are located at institute respectively with drain contact hole (72)
The both sides of grid (6) and gate insulator (5) are stated, the pixel definition hole (73) is close to the source contact openings (71)；
Step S8, on the interlayer insulating film (7) depositing second metal layer and carry out patterned process, formed source electrode (S) and
Drain (D), the source electrode (S) contacts the conductor layer (41) through the source contact openings (71), and the drain electrode (D) is through the leakage
Pole contact hole (72) contacts the conductor layer (41)；
The source electrode (S), drain electrode (D), grid (6), gate insulator (5), conductor layer (41) portion contacted with the source electrode (S)
Conductor layer (41) part and semiconductor channel area (42) divide, contacted with the drain electrode (D) constitutes thin film transistor (TFT) (T)；
Step S9, deposit passivation layer (9) and carry out at patterning on the source electrode (S), drain electrode (D) and interlayer insulating film (7)
Reason, forms the through hole (91) for exposing the pixel definition hole (73)；
Step S10, with the conductor layer (41) it is anode deposition white light OLED luminescent layer in the pixel definition hole (73)
(10)；
Step S11, the deposited metal negative electrode (11) on the white light OLED luminescent layer (10) and passivation layer (9).
2. the preparation method of bottom emitting type white light OLED panel as claimed in claim 1, it is characterised in that in the step S2
The material of cushion (3) is silica or silicon nitride, and thickness is
3. the preparation method of bottom emitting type white light OLED panel as claimed in claim 1, it is characterised in that in the step S3
The material of oxide semiconductor thin-film is one kind in indium gallium zinc oxide, indium zinc tin oxide, indium gallium zinc tin oxide, thickness
For
4. the preparation method of bottom emitting type white light OLED panel as claimed in claim 1, it is characterised in that in the step S4
The material of insulation film (5 ') is silica or silicon nitride, and thickness is
5. the preparation method of bottom emitting type white light OLED panel as claimed in claim 1, it is characterised in that in the step S4
The material of the first metal layer is one or more of stacked combinations in molybdenum, aluminium, copper, titanium, and thickness is
6. the preparation method of bottom emitting type white light OLED panel as claimed in claim 1, it is characterised in that the step S6 profits
Corona treatment is carried out with helium or argon gas.
7. the preparation method of bottom emitting type white light OLED panel as claimed in claim 1, it is characterised in that in the step S7
The material of interlayer insulating film (7) is silica or silicon nitride, and thickness is
8. the preparation method of bottom emitting type white light OLED panel as claimed in claim 1, it is characterised in that in the step S8
The material of second metal layer is one or more of stacked combinations in molybdenum, aluminium, copper, titanium, and thickness is
9. the preparation method of bottom emitting type white light OLED panel as claimed in claim 1, it is characterised in that in the step S9
The material of passivation layer (9) is silica or silicon nitride, and thickness is
10. a kind of bottom emitting type white light OLED panel construction, it is characterised in that including：
Underlay substrate (1)；
Cover the color film layer (2) of the underlay substrate (1)；
Cover the cushion (3) of the color film layer (2)；
The semiconductor channel area (42) that is located on the cushion (3) and the semiconductor channel area (42) both sides are connected respectively
Conductor layer (41)；
Cover the gate insulator (5) of the semiconductor channel area (42)；
Cover the grid (6) of the gate insulator (5)；
It is located at the interlayer insulating film (7) on the grid (6), conductor layer (41) and cushion (3), the interlayer insulating film (7)
With through the interlayer insulating film (7) with expose respectively conductor layer (41) part surface source contact openings (71), drain electrode connect
Contact hole (72) and pixel definition hole (73), the source contact openings (71) are located at the grid respectively with drain contact hole (72)
(6) and gate insulator (5) both sides, the pixel definition hole (73) is close to the source contact openings (71)；
The source electrode (S) being located on the interlayer insulating film (7) and drain electrode (D), the source electrode (S) is through the source contact openings
(71) conductor layer (41) is contacted, the drain electrode (D) contacts the conductor layer (41) through the drain contact hole (72)；
The passivation layer (9) on the source electrode (S), drain electrode (D) and interlayer insulating film (7) is located at, the passivation layer (9) has sudden and violent
Expose the through hole (91) of the pixel definition hole (73)；
It is located in the pixel definition hole (73) and with white light OLED luminescent layer (10) of the conductor layer (41) for anode；
And it is located at the white light OLED luminescent layer (10) and the metallic cathode (11) on passivation layer (9)；
The source electrode (S), drain electrode (D), grid (6), gate insulator (5), conductor layer (41) portion contacted with the source electrode (S)
Conductor layer (41) part and semiconductor channel area (42) divide, contacted with the drain electrode (D) constitutes thin film transistor (TFT) (T).
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