CN110459475A - A kind of thin film transistor (TFT) and its manufacturing method - Google Patents
A kind of thin film transistor (TFT) and its manufacturing method Download PDFInfo
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- CN110459475A CN110459475A CN201910665610.6A CN201910665610A CN110459475A CN 110459475 A CN110459475 A CN 110459475A CN 201910665610 A CN201910665610 A CN 201910665610A CN 110459475 A CN110459475 A CN 110459475A
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- tft
- contact hole
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- 239000010409 thin film Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 170
- 239000004065 semiconductor Substances 0.000 claims abstract description 57
- 239000004020 conductor Substances 0.000 claims abstract description 50
- 239000000463 material Substances 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000010408 film Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000012774 insulation material Substances 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000003475 lamination Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 4
- 238000004062 sedimentation Methods 0.000 claims description 4
- 229910004205 SiNX Inorganic materials 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 238000003851 corona treatment Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 239000011241 protective layer Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Abstract
The present invention provides a kind of thin film transistor (TFT) and its manufacturing method, thin film transistor (TFT) includes buffer layer, the semiconductor layer on buffer layer, the first conductor electrode formed by semiconductor layer material by conductorization and the second conductor electrode, covers gate insulating layer on the semiconductor layer, the grid on gate insulating layer, source electrode, drain electrode and source and drain connection electrode, the source electrode contacts in pixel region with the first conductor electrode, the drain electrode contacts in pixel region with the second conductor electrode, and the source and drain connection electrode is in terminal area and gate contact.The present invention improves the interface between semiconductor layer and gate insulating layer by semiconductor layer and gate insulating layer continuous film forming, and source-drain electrode metal can be caused to generate broken string during etching to avoid gate insulating layer；Semiconductor layer of the present invention can spend quarter as protective layer to avoid buffer layer.
Description
Technical field
The present invention relates to the technical field of semiconductor more particularly to a kind of thin film transistor (TFT) and its manufacturing methods.
Background technique
Capacitor Cgs between grid and source electrode and grid and drain electrode can be effectively reduced in the thin film transistor (TFT) of existing top-gated
Between capacitor Cgd, manufacturing method deposits one layer of buffer layer 20 as shown in Figure 1, the first step first on glass substrate 10,
Then on buffer layer 20 deposited semiconductor layer material and graphically formed semiconductor layer 30；Second step is forming first step figure
Successive sedimentation gate insulating film (GI) 40 and gate metal layer, gate metal layer graphically form grid 50 on the basis of shape；The
Three steps carry out whole face etching to gate insulating film 40 and only retain the gate insulating film being located at below grid 50；4th step, to not by
The semiconductor layer 30 that grid carries out layer covering carries out conductor processing and forms conductor electrode；5th step deposits interlayer dielectric 60
And form various contact holes；6th step, deposited metal layer simultaneously graphically form the source-drain electrode 70 connecting with conductor electrode.
As shown in Figures 2 and 3, for gate insulating film 40 in whole face etching process, there is etched groove in the edge of semiconductor layer 30
100, broken string is also easy to produce after source-drain electrode 70 is graphical.
Summary of the invention
The purpose of the present invention causes source-drain electrode metal to generate during providing one kind and avoiding gate insulating layer in etching
The thin film transistor (TFT) and its manufacturing method of broken string.
The present invention provides a kind of manufacturing method of thin film transistor (TFT), includes the following steps:
S1: successive sedimentation buffer layer, semiconductor material layer, the first insulation material layer and the first metal layer；
S2: processing is patterned to the first metal layer and the first insulation material layer and forms grid and below grid
Gate insulating layer；
S3: performing etching the semiconductor layer to be formed below gate insulating layer to semiconductor material layer, wherein in pixel
The length of semiconductor layer in region is greater than the length of gate insulating layer, and the length of the semiconductor layer in terminal area is equal to grid
The length of insulating layer；
S4: to the semiconductor layer progress conductor processing being exposed to outside gate insulating layer so that the half of gate insulating layer two sides
Conductor layer is respectively formed the first conductor electrode and the second conductor electrode；
S5: the second insulation material layer of deposition simultaneously carve hole to the second insulation material layer and forms interlayer insulating film, is located at the
The first contact hole on one conductor electrode, the second contact hole on the second conductor electrode and the grid positioned at terminal area
On third contact hole；
S6: depositing second metal layer and second metal layer is patterned the source electrode to be formed in the first contact hole,
Drain electrode in the second contact hole and the source and drain connection electrode in third contact hole.
Further, the grid of step S2 and gate insulating layer are formed simultaneously.
Further, the specific steps of step S2 are as follows: first the first metal layer is patterned and is formed positioned at first absolutely
Then grid in edge material layer carries out whole face etching to the first insulation material layer and forms the gate insulator being located at below grid
Layer.
Further, the semiconductor material is metal oxide semiconductor material.
Further, the first metal layer and the material of second metal layer include but is not limited to Mo single layer, Ti and Cu lamination,
Mo/Al/Mo lamination and MoNb/Cu lamination.
Further, the method packet that conductor processing is carried out to the semiconductor layer being exposed to outside gate insulating layer of step S4
It includes: corona treatment, ion implanting and high-temperature baking.
Further, the first insulating layer material and second insulating layer material include but is not limited to SiO2、SiOx、Al2O3With
SiNx。
The present invention also provides a kind of thin film transistor (TFT)s comprising buffer layer, the semiconductor layer on buffer layer, by partly leading
The first conductor electrode and the second conductor electrode, the gate insulator of covering on the semiconductor layer that body layer material is formed by conductorization
Layer, the grid on gate insulating layer, source electrode, drain electrode and source and drain connection electrode, the source electrode is in pixel region with first
Conductor electrode contact, the drain electrode contact in pixel region with the second conductor electrode, and the source and drain connection electrode is in terminal region
Domain and gate contact.
It further, further include the interlayer insulating film on grid, the source electrode, drain electrode and source and drain connection electrode are located at
On interlayer insulating film.
Further, the interlayer insulating film is equipped with the first contact hole being located on the first conductor electrode, leads positioned at second
The second contact hole on body electrode and the third contact hole on the grid of terminal area, the source electrode pass through the first contact
Hole is connect with the first conductor electrode, and drain electrode is connect by the second contact hole with the second conductor electrode, and source and drain connection electrode passes through the
Three contact holes are connect with grid.
The present invention is improved between semiconductor layer and gate insulating layer by semiconductor layer and gate insulating layer continuous film forming
Interface can cause source-drain electrode metal to generate broken string to avoid gate insulating layer during etching；Semiconductor layer of the present invention is made
For protective layer, quarter can be spent to avoid buffer layer.
Detailed description of the invention
Fig. 1 is the schematic diagram of the manufacturing process of the thin film transistor (TFT) of existing top-gated；
Fig. 2 is that the gate insulating film of the thin film transistor (TFT) of existing top-gated the signal of etched groove occurs in whole face etching process
Figure；
Fig. 3 is partial sectional view shown in Fig. 2；
Fig. 4 is the schematic diagram of one of manufacturing process of thin film transistor (TFT) of the present invention；
Fig. 5 is two schematic diagram of the manufacturing process of thin film transistor (TFT) of the present invention.
Specific embodiment
In the following with reference to the drawings and specific embodiments, the present invention is furture elucidated, it should be understood that these embodiments are merely to illustrate
It the present invention rather than limits the scope of the invention, after the present invention has been read, those skilled in the art are to of the invention each
The modification of kind equivalent form falls within the application range as defined in the appended claims.
To make simplified form, part related to the present invention is only schematically shown in each figure, they are not represented
Its practical structures as product.In addition, there is identical structure or function in some figures so that simplified form is easy to understand
Component only symbolically depicts one of those, or has only marked one of those.Herein, "one" is not only indicated
" only this ", can also indicate the situation of " more than one ".
As shown in figure 4, a kind of manufacturing method of thin film transistor (TFT), includes the following steps:
S1: successive sedimentation buffer layer 20, semiconductor material layer 30, the first insulation material layer 40 and first on the substrate 10
Metal layer 50；
S2: while processing formation scan line is patterned to the first metal layer 50 and the first insulation material layer 40 and (is schemed not
Show), the gate insulating layer 41 of 51 lower section of the grid 51 that connect with scan line and grid or figure first is carried out to the first metal layer 50
Shape simultaneously forms the grid 51 being located on the first insulation material layer 40, then carries out whole face etching simultaneously to the first insulation material layer 40
Form the gate insulating layer 41 for being located at 51 lower section of grid, in the etching process of the first insulation material layer 40, semiconductor material layer
30 are not etched as etching barrier layer guarantee buffer layer 20；
S3: performing etching the semiconductor layer 31 to be formed positioned at 41 lower section of gate insulating layer to semiconductor material layer 30, wherein
The length of semiconductor layer 31 in pixel region is greater than the length of gate insulating layer 41, the semiconductor layer 31 in terminal area
Length is equal to the length of gate insulating layer 41；
S4: conductor processing is carried out so that 41 liang of gate insulating layer to the semiconductor layer 31 being exposed to outside gate insulating layer 41
The semiconductor layer 31 of side is respectively formed the first conductor electrode 61 and the second conductor electrode 62, to being exposed to outside gate insulating layer 41
Semiconductor layer 31 carry out conductor treatment process in, etching liquid is to the corrosion-free effect of grid 51；
S5: as shown in figure 5, depositing the second insulation material layer and carrying out carving hole formation layer insulation to the second insulation material layer
Layer 70, the first contact hole 71 on the first conductor electrode 61, the second contact hole 72 on the second conductor electrode 62 with
And the third contact hole 73 on the grid 51 of terminal area；
S6: depositing second metal layer is simultaneously patterned the source electrode to be formed in the first contact hole 71 to second metal layer
81, the drain electrode 82 in the second contact hole 72, the source and drain connection electrode 83 in third contact hole 73 and with source electrode 81
The data line (not shown) of connection.
Wherein, semiconductor material is metal oxide semiconductor material, including but not limited to IGZO, IGZTO, IZO etc.；
The first metal layer and the material of second metal layer include but is not limited to Mo single layer, Ti and Cu lamination, Mo/Al/Mo lamination and
MoNb/Cu lamination etc..
The method for carrying out conductor processing to the semiconductor layer 31 that is exposed to outside gate insulating layer 41 of step S4 includes:
Gas ions processing, ion implanting, high-temperature baking etc..
First insulating layer material and second insulating layer material include but is not limited to SiO2、SiOx、Al2O3、SiNxDeng or root
Preferred multi-layer insulation superposition is required according to device property.
As shown in figure 5, the present invention also discloses a kind of thin film transistor (TFT), the above method is used to manufacture comprising to be located at glass
Buffer layer 20 on glass substrate 10, the semiconductor layer 31 on buffer layer 20 are formed by semiconductor layer material by conductor
The first conductor electrode 61 and the second conductor electrode 62, be covered on semiconductor layer 31 gate insulating layer 41, be located at grid it is exhausted
Grid 51, source electrode 81, drain electrode 82, source and drain connection electrode 83 in edge layer 41 and the interlayer insulating film 70 on grid 51,
Source electrode 81, drain electrode 82 and source and drain connection electrode 83 are located on interlayer insulating film 70.
Interlayer insulating film 70 is equipped with the first contact hole 71 being located on the first conductor electrode 61, is located at the second conductor electrode 62
On the second contact hole 72 and the third contact hole 73 on the grid 51 of terminal area, the source electrode 61 connect by first
Contact hole 71 is connect with the first conductor electrode 61, and drain electrode 62 is connect by the second contact hole 72 with the second conductor electrode 62, and source and drain connects
Receiving electrode 83 is connect by third contact hole 73 with grid 51, so that source electrode 61 is using the first conductor electrode 61 as intermediary and partly
The connection of conductor layer 31, drain electrode 62 connect using the second conductor electrode 62 as intermediary with semiconductor layer 31, source and drain connection electrode 83 and
The connection of grid 51 forms the terminal for being located at terminal area.
The present invention is improved between semiconductor layer and gate insulating layer by semiconductor layer and gate insulating layer continuous film forming
Interface can cause source-drain electrode metal to generate broken string to avoid gate insulating layer during etching；Semiconductor layer of the present invention is made
For protective layer, quarter can be spent to avoid buffer layer.
The preferred embodiment of the present invention has been described above in detail, but during present invention is not limited to the embodiments described above
Detail can carry out a variety of equivalents to technical solution of the present invention (in full within the scope of the technical concept of the present invention
Amount, shape, position etc.), these equivalents all belong to the scope of protection of the present invention.
Claims (10)
1. a kind of manufacturing method of thin film transistor (TFT), which comprises the steps of:
S1: successive sedimentation buffer layer, semiconductor material layer, the first insulation material layer and the first metal layer；
S2: processing is patterned to the first metal layer and the first insulation material layer and forms grid and the grid below grid
Insulating layer；
S3: performing etching the semiconductor layer to be formed below gate insulating layer to semiconductor material layer, wherein in pixel region
The length of interior semiconductor layer is greater than the length of gate insulating layer, and the length of the semiconductor layer in terminal area is equal to gate insulator
The length of layer；
S4: to the semiconductor layer progress conductor processing being exposed to outside gate insulating layer so that the semiconductor of gate insulating layer two sides
Layer is respectively formed the first conductor electrode and the second conductor electrode；
S5: the second insulation material layer of deposition is simultaneously carried out carving hole formation interlayer insulating film, be led positioned at first to the second insulation material layer
The first contact hole on body electrode, the second contact hole on the second conductor electrode and on the grid of terminal area
Third contact hole；
S6: depositing second metal layer is simultaneously patterned the source electrode to be formed in the first contact hole to second metal layer, is located at
Drain electrode in second contact hole and the source and drain connection electrode in third contact hole.
2. the manufacturing method of thin film transistor (TFT) according to claim 1, it is characterised in that: the grid and grid of step S2 is exhausted
Edge layer is formed simultaneously.
3. the manufacturing method of thin film transistor (TFT) according to claim 1, it is characterised in that: the specific steps of step S2 are as follows:
First the first metal layer is patterned and forms the grid on the first insulation material layer, then to the first insulation material layer
It carries out whole face etching and forms the gate insulating layer being located at below grid.
4. the manufacturing method of thin film transistor (TFT) according to claim 1, it is characterised in that: the semiconductor material is metal
Oxide semiconductor material.
5. the manufacturing method of thin film transistor (TFT) according to claim 1, it is characterised in that: the first metal layer and the second metal
The material of layer includes but is not limited to Mo single layer, Ti and Cu lamination, Mo/Al/Mo lamination and MoNb/Cu lamination.
6. the manufacturing method of thin film transistor (TFT) according to claim 1, it is characterised in that: step S4 to being exposed to grid
The method that semiconductor layer outside insulating layer carries out conductor processing includes: corona treatment, ion implanting and high-temperature baking.
7. the manufacturing method of thin film transistor (TFT) according to claim 1, it is characterised in that: the first insulating layer material and second
Insulating layer material includes but is not limited to SiO2、SiOx、Al2O3And SiNx。
8. a kind of thin film transistor (TFT), it is characterised in that: it includes buffer layer, the semiconductor layer on buffer layer, by semiconductor
The first conductor electrode and the second conductor electrode, the gate insulator of covering on the semiconductor layer that layer material is formed by conductorization
Layer, the grid on gate insulating layer, source electrode, drain electrode and source and drain connection electrode, the source electrode is in pixel region with first
Conductor electrode contact, the drain electrode contact in pixel region with the second conductor electrode, and the source and drain connection electrode is in terminal region
Domain and gate contact.
9. thin film transistor (TFT) according to claim 8, it is characterised in that: it further include the interlayer insulating film on grid,
The source electrode, drain electrode and source and drain connection electrode are located on interlayer insulating film.
10. thin film transistor (TFT) according to claim 9, it is characterised in that: the interlayer insulating film is equipped with leads positioned at first
The first contact hole on body electrode, the second contact hole on the second conductor electrode and on the grid of terminal area
Third contact hole, the source electrode are connect by the first contact hole with the first conductor electrode, and drain electrode passes through the second contact hole and second
Conductor electrode connection, source and drain connection electrode are connect by third contact hole with grid.
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| CN201910665610.6A CN110459475A (en) | 2019-07-23 | 2019-07-23 | A kind of thin film transistor (TFT) and its manufacturing method |
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Application publication date: 20191115 |