CN107293503B - Test structure, preparation method and the test method of shared contact hole circuit defect - Google Patents
Test structure, preparation method and the test method of shared contact hole circuit defect Download PDFInfo
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- CN107293503B CN107293503B CN201710276138.8A CN201710276138A CN107293503B CN 107293503 B CN107293503 B CN 107293503B CN 201710276138 A CN201710276138 A CN 201710276138A CN 107293503 B CN107293503 B CN 107293503B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Abstract
The present invention provides test structure, preparation method and the test methods of a kind of shared contact hole circuit defect, and testing structure has the first conductivity type of transistor；First conductivity type of transistor includes: that the bottom of one end of active area, the first grid being arranged on active area and second grid, second grid is not provided with source region；Contact hole is shared in first grid source on first grid and contact hole is shared in the second gate source on one end of second grid；Share contact hole connection first grid one end and active area in first grid source；One end that contact hole only connects second grid is shared in second gate source, and the bottom that contact hole is shared in second gate source is not connected to active area.It can intuitively judge very much that second gate source shares whether contact hole occurs short circuit using test structure of the invention, be conducive to the monitoring for carrying out the Pingdu, technique and board of subsequent technique window.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, and in particular to a kind of test structure of shared contact hole circuit defect
And test method.
Background technique
With the development of integrated circuit technology, semiconductor processing dimensions are smaller and smaller, also become increasingly complex.Many techniques are whole
The process window of conjunction is smaller and smaller, such as the short circuit problem of contact hole and polysilicon, by alignment precision and contact hole and more
The influence of crystal silicon critical size etc. is one of the difficulties of 28nm or less research and development technique.
As shown in Fig. 1 to 5, wherein Fig. 1 be wafer yield test schematic diagram, Fig. 2 be existing grid source share contact hole with
Grid generates the scanning electron microscope diagram piece of short circuit, and Fig. 3 is that the shared contact hole in existing grid source is normally swept with gate structure
Electron microscope picture is retouched, Fig. 4 is the electron beam scan-image schematic diagram of normal SRAM structure, and Fig. 5 is the shared contact in grid source
Hole and grid generate the electron beam scan-image schematic diagram of the SRAM structure of short circuit.Product shown in Fig. 2 is by crystal round fringes
Independent position (Single Bit, SB) fail serious problem, physics failure analysis (Physical Failure
Analysis, PFA) contact hole and polysilicon short problem are shared for grid source as the result is shown, as shown in dotted line frame in Fig. 2.However,
For this electrical property failure problem, optical check does not have enough precision to be monitored online, simultaneously because shared contact hole exists
In conventional SRAM structure, one end can be connected with polysilicon, when its other end and another polysilicon short, not have electricity
The variation of position, so the monitoring of electrical defect can not be carried out to it, as shown in Figure 5.
Summary of the invention
In order to overcome the above problems, the present invention is intended to provide a kind of the test structure and test of shared contact hole circuit defect
Method, to promote product yield.
In order to achieve the above object, the present invention provides a kind of grid source share contact hole circuit defect test structure,
With the first conductivity type of transistor；First conductivity type of transistor includes: active area, the first grid being arranged on active area
The bottom of pole and one end of second grid, second grid is not provided with source region；First grid source on first grid, which is shared, to be connect
Contact hole is shared in contact hole and the second gate source on described one end of second grid；Share contact hole connection first in first grid source
Grid one end and active area；Share described one end that contact hole only connects second grid, the shared contact in second gate source in second gate source
The bottom in hole is not connected to active area；Wherein,
When contact hole is shared in first grid source is on state, the normal condition that contact hole is shared in second gate source is not lead
Logical, the abnormality that contact hole is shared in second gate source is conducting.
Preferably, second gate source shares contact hole bottom and is provided with isolation structure, second gate source share contact hole be isolated
Structure is in contact and is in contact simultaneously with described one end of second grid.
Preferably, it is fleet plough groove isolation structure that the isolation structure of contact hole bottom setting is shared in the second gate source.
Preferably, parallel arrangement between first grid and second grid.
Preferably, the active area includes N-type deep-well region and the P-doped zone in N-type deep-well region, the first grid
Pole is set on N-type deep-well region, and the first grid source is shared contact hole and is set in P-doped zone and the first grid；Or
Active area described in person includes N-type deep-well region and the N-doped zone in N-type deep-well region, and the first grid is set to N-type depth
On well region, the first grid source is shared contact hole and is set in N-doped zone and the first grid；Or the active area packet
P-type deep-well region and the P-doped zone in p-type deep-well region are included, the first grid is set on p-type deep-well region, and described
It shares contact hole and is set in P-doped zone and the first grid in one grid source.
Preferably, the active area includes p-type deep-well region and the N-doped zone in p-type deep-well region, the first grid
Pole is set on p-type deep-well region, and the first grid source is shared contact hole and is set in N-doped zone and the first grid；Or
Active area described in person includes p-type deep-well region and the P-doped zone in p-type deep-well region, and the first grid is set to p-type depth
On well region, the first grid source is shared contact hole and is set in P-doped zone and the first grid；Or the active area packet
N-type deep-well region and the N-doped zone in N-type deep-well region are included, the first grid is set on N-type deep-well region, and described
It shares contact hole and is set in N-doped zone and the first grid in one grid source.
It preferably, further include the second conductivity type of transistor；First conductivity type of transistor and the second conduction type crystal
Pipe is arranged alternately.
In order to achieve the above object, the present invention also provides a kind of preparation method using above-mentioned test structure, packets
It includes:
Step 01: a substrate is provided；The active area for the first conductivity type of transistor is prepared in the substrate；
Step 02: preparing first grid and second grid on the active area of the first conductivity type of transistor；Wherein, second
One end bottom of grid is not located on active area；
Step 03: preparing first grid source on first grid and active area and share contact hole, described the one of second grid
Second gate source is prepared on end shares contact hole；Wherein, described one end that contact hole only connects second grid is shared in second gate source, and
It shares contact hole bottom and is not connected to active area in second gate source.
Preferably, in the step 01, further includes: active area exterior domain and to correspond to second gate source to be formed total
It enjoys and forms isolation structure below contact hole.
Preferably, the active area includes N-type deep-well region and the P-doped zone in N-type deep-well region, the first grid
Pole is set on N-type deep-well region, and the first grid source is shared contact hole and is set in P-doped zone and the first grid；Or
Active area described in person includes N-type deep-well region and the N-doped zone in N-type deep-well region, and the first grid is set to N-type depth
On well region, the first grid source is shared contact hole and is set in N-doped zone and the first grid；Or the active area packet
P-type deep-well region and the P-doped zone in p-type deep-well region are included, the first grid is set on p-type deep-well region, and described
It shares contact hole and is set in P-doped zone and the first grid in one grid source.
Preferably, the active area includes p-type deep-well region and the N-doped zone in p-type deep-well region, the first grid
Pole is set on p-type deep-well region, and the first grid source is shared contact hole and is set in N-doped zone and the first grid；Or
Active area described in person includes p-type deep-well region and the P-doped zone in p-type deep-well region, and the first grid is set to p-type depth
On well region, the first grid source is shared contact hole and is set in P-doped zone and the first grid；Or the active area packet
N-type deep-well region and the N-doped zone in N-type deep-well region are included, the first grid is set on N-type deep-well region, and described
It shares contact hole and is set in N-doped zone and the first grid in one grid source.
In order to achieve the above object, the shared contact in grid source is carried out using above-mentioned test structure the present invention also provides a kind of
The test method of hole circuit defect comprising:
Firstly, sharing the shared contact hole of contact hole and second gate source to first grid source carries out electronics beam scanning, first is obtained
Contact hole is shared in grid source and the scan-image of contact hole is shared in second gate source；
Then, according to obtained scan-image, judge whether shared contact hole circuit defect occur；Wherein, judge brightness
The shared contact hole in abnormal second gate source is presented and circuit defect occurs.
Preferably, the active area of first conductivity type of transistor include N-type deep-well region and be located at N-type deep-well region
Interior P-doped zone, the first grid are set on N-type deep-well region, and the shared contact hole in the first grid source is set to p-type and mixes
In miscellaneous area and the first grid；Or the active area includes N-type deep-well region and the N-doped zone in N-type deep-well region,
The first grid is set on N-type deep-well region, and the first grid source shares contact hole and is set to N-doped zone and described first
On grid；Or the active area includes p-type deep-well region and the P-doped zone in p-type deep-well region, the first grid is set
It is placed on p-type deep-well region, the first grid source is shared contact hole and is set in P-doped zone and the first grid；
Positive potential electronics beam scanning is then used, the shared contact hole in first grid source is obtained and sweeping for contact hole is shared in second gate source
Shading picture；
Sharing contact hole when first grid source is in bright hole, and it is in dark holes that contact hole is shared in second gate source, and judgement obtains second gate source
Shared contact hole does not have circuit defect；Sharing contact hole when first grid source is in bright hole, when contact hole is shared in bright hole in second gate source,
Judgement show that the second gate source shares contact hole and circuit defect occurs.
Preferably, the active area of first conduction type includes p-type deep-well region and the N in p-type deep-well region
Type doped region, the first grid are set on p-type deep-well region, and the first grid source shares contact hole and is set to N-doped zone
On the first grid；Or the active area includes p-type deep-well region and the P-doped zone in p-type deep-well region, it is described
First grid is set on p-type deep-well region, and the first grid source shares contact hole and is set to P-doped zone and the first grid
On；Or the active area includes N-type deep-well region and the N-doped zone in N-type deep-well region, the first grid is set to
On N-type deep-well region, the first grid source is shared contact hole and is set in N-doped zone and the first grid；
Negative potential electronics beam scanning is then used, the shared contact hole in first grid source is obtained and sweeping for contact hole is shared in second gate source
Shading picture；
Sharing contact hole when first grid source is in dark holes, and it is in bright hole that contact hole is shared in second gate source, and judgement obtains second gate source
Shared contact hole does not have circuit defect；Sharing contact hole when first grid source is in dark holes, when contact hole is shared in dark holes in second gate source,
Judgement show that the second gate source shares contact hole and circuit defect occurs.
The test structure and test method of contact hole circuit defect are shared in grid source of the invention, total by setting first grid source
Contact hole connection first grid and active area are enjoyed, second gate source shares contact hole and only connects second grid, and its bottom is not connected to
Active area, when contact hole is shared in second gate source and short circuit occurs for neighbouring grid, the shared contact hole in second gate source, which can be presented, is led
Logical state, thus the scanning shadow obtained according to the electronics beam scanning that the shared contact hole of contact hole and second gate source is shared in first grid source
As can intuitively judge to show that second gate source shares contact hole and circuit defect occurs very much, is conducive to progress subsequent technique window and comments
Estimate and technique and board condition monitoring.
Detailed description of the invention
Fig. 1 is wafer yield test schematic diagram
Fig. 2 is the scanning electron microscope diagram piece that contact hole is shared in existing grid source and grid generates short circuit
Fig. 3 is that contact hole and the normal scanning electron microscope diagram piece of gate structure are shared in existing grid source
Fig. 4 is the electron beam scan-image schematic diagram of normal SRAM structure
Fig. 5 is the electron beam scan-image schematic diagram that contact hole is shared in grid source and grid generates short-circuit SRAM structure
Fig. 6 is the electron beam scan-image schematic diagram of the normal SRAM structure of a preferred embodiment of the invention
Fig. 7 is that the electronics that contact hole circuit defect is shared in grid source occurs for the SRAM structure of a preferred embodiment of the invention
Beam scanning image schematic diagram
Fig. 8 is the equivalent structure schematic diagram of the normal test structure of a preferred embodiment of the invention
Fig. 9 is the equivalent knot that grid source occurs and shares the test structure of contact hole short circuit of a preferred embodiment of the invention
Structure schematic diagram
Figure 10 is that contact hole short circuit is shared in the preparation method of the test structure of a preferred embodiment of the invention and grid source
The flow diagram of the test method of defect
Specific embodiment
To keep the contents of the present invention more clear and easy to understand, below in conjunction with Figure of description, the contents of the present invention are made into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, general replacement known to those skilled in the art
It is included within the scope of protection of the present invention.
Below in conjunction with attached drawing 6~10 and specific embodiment, invention is further described in detail.It should be noted that attached drawing
It is all made of very simplified form, using non-accurate ratio, and only to facilitate, clearly reach aid illustration the present embodiment
Purpose.
Please refer to Fig. 6 and Fig. 8, the test structure of contact hole circuit defect is shared in a kind of grid source of the present embodiment, has the
One conductivity type of transistor is here PMOS transistor.In the present embodiment, test structure further includes the second conduction type crystal
Pipe can be here NMOS transistor, as shown in dotted line frame in Fig. 6；First conductivity type of transistor PMOS and second is conductive
Type of transistor NMOS is arranged alternately.
Referring to Fig. 6, first conductivity type of transistor PMOS includes:
One end of active area AA, the first grid G1 being arranged on active area AA and second grid G2, second grid G2
Bottom be not provided with source region AA；It shares contact hole K1 and positioned at second grid G2's in first grid source on first grid G1
Share contact hole K2 in second gate source on one end；Share one end and the active area of contact hole K1 connection first grid G1 in first grid source
AA；One end that contact hole K2 only connects second grid G2 is shared in second gate source, and the bottom of contact hole hole K2 is shared not in second gate source
Connect active area AA.
In the present embodiment, referring to Fig. 8, the bottom contact hole K2 is shared in second gate source is provided with fleet plough groove isolation structure STI,
Second gate source shares contact hole K2 and is in contact with isolation structure STI and is in contact simultaneously with one end of second grid G2, needs
Bright, in the present embodiment, the isolation structure that the setting of the bottom contact hole K2 is shared in second gate source is fleet plough groove isolation structure STI.
In other embodiments of the invention, second gate source share the setting of the bottom contact hole K2 isolation structure can also for it is other can be with
Play the structure of buffer action.
Referring to Fig. 6, parallel arrangement at certain intervals between first grid G1 and second grid G2.
Referring to Fig. 8, according to when contact hole K2 is shared in second gate source and short circuit occurs for neighbouring grid, second gate
Contact hole K2 is shared in source can be presented on state, and the first conductivity type of transistor of the test structure of the present embodiment includes: active
Area AA includes N-type deep-well region N-Well and the P-doped zone P+ in N-type deep-well region, and first grid K1 is set to N-type deep trap
On area N-Well, first grid source is shared contact hole K1 and is set on P-doped zone P+ and first grid G1；Or first conductive-type
It includes N-type deep-well region and the N-doped zone in N-type deep-well region that transistor npn npn, which is also provided with source region, and first grid is set
It is placed on N-type deep-well region, first grid source is shared contact hole and is set in N-doped zone and the first grid；Or first lead
It includes p-type deep-well region and the P-doped zone in p-type deep-well region, the first grid that electric type of transistor, which is also provided with source region,
Pole is set on p-type deep-well region, and first grid source is shared contact hole and is set in P-doped zone and first grid.In addition, second leads
The type of electric type of transistor and the first conductivity type of transistor on the contrary, when the first conductivity type of transistor be PMOS when, second
Conductivity type of transistor is NMOS, as shown in figure 8, the second conductivity type of transistor NMOS is N-doped zone N+ on p-type deep-well region
It constitutes.
In addition, test structure shares contact hole and neighbouring grid according to when second gate source in other embodiments of the invention
When short circuit occurs for pole, contact hole is shared in second gate source can be presented on state, and the transistor of the first conduction type can also be arranged:
Active area includes p-type deep-well region and the N-doped zone in p-type deep-well region, and first grid is set on p-type deep-well region, the
It shares contact hole and is set in N-doped zone and first grid in one grid source；Or first the transistor of conduction type can also set
Being equipped with source region includes p-type deep-well region and the P-doped zone in p-type deep-well region, and first grid is set on p-type deep-well region,
It shares contact hole and is set in P-doped zone and first grid in first grid source；Or first the transistor of conduction type can be with
It includes N-type deep-well region and the N-doped zone in N-type deep-well region that active area, which is arranged, and first grid is set to N-type deep-well region
On, first grid source is shared contact hole and is set in N-doped zone and first grid.
For above-mentioned all possible test structure, when contact hole is shared in first grid source is on state, second gate source
The normal condition of shared contact hole is to be not turned on, that is, illustrates that second gate source shares contact hole and do not occur circuit defect；Second gate source
The abnormality of shared contact hole is conducting, then illustrates that second gate source shares contact hole and circuit defect occurs.
In addition, please referring to Fig. 6 to 10, the preparation of the above-mentioned test structure of a kind of pair of the present embodiment is also provided in the present embodiment
Method includes:
Step 01: a substrate is provided；The active area AA for the first conductivity type of transistor PMOS is prepared in the substrate；
Specifically, this step further include: active area exterior domain and correspond to the shared contact in second gate source to be formed
Isolation structure STI is formed below the K2 of hole.It should be noted that also there is the second conductivity type of transistor NMOS in the present embodiment,
When preparing the first conductivity type of transistor NMOS at this time, the second conductivity type of transistor PMOS can synchronize preparation, can also be first
Prepare the first conductivity type of transistor NMOS and prepare the second conductivity type of transistor PMOS again, or vice versa also may be used.In addition it is also necessary to
Illustrate, since the present embodiment is test structure, the preparation process for testing structure can be with the preparation work of proper device structure
Skill is mutually compatible with, and that is to say can synchronize preparation, only in this step 01, is tested in structure in the exterior domain of active area AA and right
It should be shared in second gate source to be formed and form isolation structure STI below contact hole K2；And this is not required in proper device structure
Step.
Step 02: preparing first grid G2 and second grid on the active area AA of the first conductivity type of transistor NMOS
G2；Wherein, one end bottom of second grid G2 is not located on active area AA；
Step 03: preparing first grid source on first grid G1 and active area AA and share contact hole K1, in second grid G2
On prepare second gate source share contact hole K2；Wherein, the shared contact hole K2 in second gate source only connects second grid G2, and its bottom
It is not connected to active area AA；
It connects, description carries out the test for sharing contact hole circuit defect in grid source using the above-mentioned test structure of the present embodiment
Method, comprising:
Step 04: contact hole K1 being shared to first grid source and second gate source shares contact hole K2 and carries out electronics beam scanning, is obtained
Contact hole K1 is shared to first grid source and the scan-image of contact hole K2 is shared in second gate source；
Step 05: according to obtained scan-image, judging whether shared contact hole circuit defect occur；Wherein, judge bright
Degree is presented the shared contact hole in abnormal second gate source and circuit defect occurs.
Sharing contact hole K1 when first grid source is on state, when contact hole K2 is shared in not on-state in second gate source,
Judgement show that second gate source shares contact hole K2 and do not have circuit defect；Sharing contact hole K1 when first grid source is on state, the
When contact hole K2 is shared on state in two grid sources, judgement show that second gate source shares contact hole K2 and circuit defect occurs.
For example, referring to Fig. 8, the active area AA of the first conductivity type of transistor PMOS of the present embodiment includes N-type
Deep-well region N-Well and the P-doped zone P+ in N-type deep-well region, first grid K1 are set on the N-Well of N-type deep-well region,
It shares contact hole K1 and is set on P-doped zone P+ and first grid G1 in first grid source；Or first conductivity type of transistor also
It includes N-type deep-well region and the N-doped zone in N-type deep-well region that active area, which can be set, and first grid is set to N-type deep trap
Qu Shang, first grid source are shared contact hole and are set in N-doped zone and the first grid；Or first conductivity type of transistor
Being also provided with source region includes p-type deep-well region and the P-doped zone in p-type deep-well region, and first grid is set to p-type depth
On well region, first grid source is shared contact hole and is set in P-doped zone and first grid.
For above-mentioned possible several test structures, when contact hole K1 conducting is shared in first grid source, second gate source is shared to be connect
Contact hole K2 is not turned on to be normal, is abnormal if it is also on state that contact hole K2 is shared in second gate source.Above-mentioned steps 04
In, using positive potential electronics beam scanning, obtain the scanning that contact hole K1 is shared in first grid source and contact hole K2 is shared in second gate source
Image, such as Fig. 6 and 7；
In above-mentioned steps 05, if it is in bright hole that contact hole K1 is shared in first grid source, it is in dark holes that contact hole K2 is shared in second gate source,
Illustrate that contact hole K1 conducting is shared in first grid source, second gate source is shared contact hole K2 and is not turned on, and judgement show that second gate source is shared
Contact hole K2 does not have circuit defect, as seen in figs. 6 and 8；Sharing contact hole K1 when first grid source is in bright hole, and second gate source is shared to be connect
When contact hole K2 is in bright hole, illustrate that contact hole K1 conducting is shared in first grid source, the shared contact hole K2 conducting in second gate source occurs different
Often, judgement show that second gate source shares contact hole K2 and circuit defect occurs, as shown in figures 7 and 9, arrow is signified in Fig. 7 one
Second gate source shares contact hole K2 and brightness change occurs, indicates that this second gate source shares contact hole K2 and short circuit occurs.
In addition, the active area for other embodiments of the present invention includes p-type deep-well region and the N-type in p-type deep-well region
Doped region, first grid are set on p-type deep-well region, and first grid source shares contact hole and is set to N-doped zone and first grid
On；Or active area includes p-type deep-well region and the P-doped zone in p-type deep-well region, first grid is set to p-type deep trap
Qu Shang, first grid source are shared contact hole and are set in P-doped zone and first grid；Or active area include N-type deep-well region and
N-doped zone in N-type deep-well region, first grid are set on N-type deep-well region, and first grid source is shared contact hole and is set to
In N-doped zone and the first grid；For such test structure, in above-mentioned steps 04, swept using negative potential electron beam
It retouches, obtains the scan-image that contact hole is shared in first grid source and contact hole is shared in second gate source；In above-mentioned steps 05, work as the first grid
It is in dark holes that contact hole is shared in source, and it is in bright hole that contact hole is shared in second gate source, illustrates that contact hole conducting, second gate are shared in first grid source
Source is shared contact hole and is not turned on, and judgement show that second gate source shares contact hole and do not have circuit defect；When the shared contact in first grid source
Hole is in dark holes, when contact hole is shared in dark holes in second gate source, illustrates that contact hole conducting is shared in first grid source, and second gate source is shared
Contact hole conducting is abnormal, and judgement show that second gate source shares contact hole and circuit defect occurs.
Although the present invention is disclosed as above with preferred embodiment, right embodiment is illustrated only for the purposes of explanation, and
It is non-to limit the present invention, those skilled in the art can make without departing from the spirit and scope of the present invention it is several more
Dynamic and retouching, the protection scope that the present invention is advocated should be subject to claims.
Claims (13)
1. the test structure that contact hole circuit defect is shared in a kind of grid source, which is characterized in that have the first conductivity type of transistor；
First conductivity type of transistor includes: active area, the first grid being arranged on active area and second grid, second grid
The bottom of one end is not provided with source region；It shares contact hole and positioned at described in second grid in first grid source on first grid
Share contact hole in second gate source on one end；Share contact hole connection first grid one end and active area in first grid source；Second gate
Described one end that contact hole only connects second grid is shared in source, and the bottom that contact hole is shared in second gate source is not connected to active area；Its
In,
When contact hole is shared in first grid source is on state, the normal condition that contact hole is shared in second gate source is to be not turned on, the
The abnormality that contact hole is shared in two grid sources is conducting；Wherein, the shared contact hole bottom in second gate source is provided with isolation structure, the
Two grid sources share contact hole and are in contact with isolation structure and are in contact simultaneously with described one end of second grid, at this point, described the
It shares contact hole and is in normal condition in two grid sources；When contact hole is shared in second gate source and adjacent gate is shorted, the second gate
It shares contact hole and is in abnormality in source.
2. test structure according to claim 1, which is characterized in that share the setting of contact hole bottom in the second gate source
Isolation structure is fleet plough groove isolation structure.
3. test structure according to claim 1, which is characterized in that parallel arrangement between first grid and second grid.
4. test structure according to claim 1, which is characterized in that the active area include N-type deep-well region and be located at N-type
P-doped zone in deep-well region, the first grid are set on N-type deep-well region, and contact hole setting is shared in the first grid source
In in P-doped zone and the first grid；Or the active area includes N-type deep-well region and the N-type in N-type deep-well region
Doped region, the first grid are set on N-type deep-well region, the first grid source share contact hole be set to N-doped zone and
On the first grid；Or the active area includes p-type deep-well region and the P-doped zone in p-type deep-well region, described
One grid is set on p-type deep-well region, and the first grid source shares contact hole and is set to P-doped zone and the first grid
On.
5. test structure according to claim 1, which is characterized in that the active area include p-type deep-well region and be located at p-type
N-doped zone in deep-well region, the first grid are set on p-type deep-well region, and contact hole setting is shared in the first grid source
In in N-doped zone and the first grid；Or the active area includes p-type deep-well region and the p-type in p-type deep-well region
Doped region, the first grid are set on p-type deep-well region, the first grid source share contact hole be set to P-doped zone and
On the first grid；Or the active area includes N-type deep-well region and the N-doped zone in N-type deep-well region, described
One grid is set on N-type deep-well region, and the first grid source shares contact hole and is set to N-doped zone and the first grid
On.
6. test structure according to claim 1, which is characterized in that further include the second conductivity type of transistor；First leads
Electric type of transistor and the second conductivity type of transistor are arranged alternately.
7. a kind of preparation method using test structure described in claim 1 characterized by comprising
Step 01: a substrate is provided；The active area for the first conductivity type of transistor is prepared in the substrate；
Step 02: preparing first grid and second grid on the active area of the first conductivity type of transistor；Wherein, second grid
One end bottom be not located on active area；
Step 03: preparing first grid source on first grid and active area and share contact hole, on described one end of second grid
It prepares second gate source and shares contact hole；Wherein, described one end that contact hole only connects second grid, and second are shared in second gate source
It shares contact hole bottom and is not connected to active area in grid source.
8. preparation method according to claim 7, which is characterized in that in the step 01, further includes: except active area
Region and correspond to second gate source to be formed share contact hole below formed isolation structure.
9. preparation method according to claim 7, which is characterized in that the active area include N-type deep-well region and be located at N-type
P-doped zone in deep-well region, the first grid are set on N-type deep-well region, and contact hole setting is shared in the first grid source
In in P-doped zone and the first grid；Or the active area includes N-type deep-well region and the N-type in N-type deep-well region
Doped region, the first grid are set on N-type deep-well region, the first grid source share contact hole be set to N-doped zone and
On the first grid；Or the active area includes p-type deep-well region and the P-doped zone in p-type deep-well region, described
One grid is set on p-type deep-well region, and the first grid source shares contact hole and is set to P-doped zone and the first grid
On.
10. preparation method according to claim 7, which is characterized in that the active area include p-type deep-well region and be located at P
N-doped zone in moldeed depth well region, the first grid are set on p-type deep-well region, and the first grid source is shared contact hole and set
It is placed in N-doped zone and the first grid；Or the active area includes p-type deep-well region and the P in p-type deep-well region
Type doped region, the first grid are set on p-type deep-well region, and the first grid source shares contact hole and is set to P-doped zone
On the first grid；Or the active area includes N-type deep-well region and the N-doped zone in N-type deep-well region, it is described
First grid is set on N-type deep-well region, and the first grid source shares contact hole and is set to N-doped zone and the first grid
On.
11. a kind of test method for carrying out sharing contact hole circuit defect in grid source using test structure described in claim 1,
It is characterized in that, comprising:
Firstly, sharing the shared contact hole of contact hole and second gate source to first grid source carries out electronics beam scanning, first grid source is obtained
The scan-image of contact hole is shared in shared contact hole and second gate source；
Then, according to obtained scan-image, judge whether shared contact hole circuit defect occur；Wherein, judge that brightness is presented
It shares contact hole and circuit defect occurs in abnormal second gate source.
12. the test method that contact hole circuit defect is shared in grid source according to claim 11, which is characterized in that described the
The active area of one conductivity type of transistor includes N-type deep-well region and the P-doped zone in N-type deep-well region, and described
One grid is set on N-type deep-well region, and the first grid source shares contact hole and is set to P-doped zone and the first grid
On；Or the active area includes N-type deep-well region and the N-doped zone in N-type deep-well region, the first grid is set to
On N-type deep-well region, the first grid source is shared contact hole and is set in N-doped zone and the first grid；Or described have
Source region includes p-type deep-well region and the P-doped zone in p-type deep-well region, and the first grid is set on p-type deep-well region,
It shares contact hole and is set in P-doped zone and the first grid in the first grid source；
Positive potential electronics beam scanning is then used, the scanning shadow that contact hole is shared in first grid source and contact hole is shared in second gate source is obtained
Picture；
Sharing contact hole when first grid source is in bright hole, and it is in dark holes that contact hole is shared in second gate source, and judgement show that second gate source is shared
Contact hole does not have circuit defect；Sharing contact hole when first grid source is in bright hole, when contact hole is shared in bright hole in second gate source, judgement
Show that the second gate source shares contact hole and circuit defect occurs.
13. the test method that contact hole circuit defect is shared in grid source according to claim 11, which is characterized in that described the
The active area of one conduction type includes p-type deep-well region and the N-doped zone in p-type deep-well region, the first grid
It is set on p-type deep-well region, the first grid source is shared contact hole and is set in N-doped zone and the first grid；Or
The active area includes p-type deep-well region and the P-doped zone in p-type deep-well region, and the first grid is set to p-type deep trap
Qu Shang, the first grid source are shared contact hole and are set in P-doped zone and the first grid；Or the active area includes
N-type deep-well region and the N-doped zone in N-type deep-well region, the first grid are set on N-type deep-well region, and described first
It shares contact hole and is set in N-doped zone and the first grid in grid source；
Negative potential electronics beam scanning is then used, the scanning shadow that contact hole is shared in first grid source and contact hole is shared in second gate source is obtained
Picture；
Sharing contact hole when first grid source is in dark holes, and it is in bright hole that contact hole is shared in second gate source, and judgement show that second gate source is shared
Contact hole does not have circuit defect；Sharing contact hole when first grid source is in dark holes, when contact hole is shared in dark holes in second gate source, judgement
Show that the second gate source shares contact hole and circuit defect occurs.
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| CN102376600A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Evaluation method for failure of contact hole |
| CN103107163A (en) * | 2011-11-11 | 2013-05-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor test structure and forming method and testing method thereof |
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Effective date of registration: 20200421 Address after: 201203 1060, room 1, 298 Cambridge East Road, Pudong New Area, Shanghai. Patentee after: SHANGHAI HUALI INTEGRATED CIRCUIT MANUFACTURING Co.,Ltd. Address before: 201210, Gauss road 568, Zhangjiang hi tech park, Shanghai, Pudong New Area Patentee before: Shanghai Huali Microelectronics Corp. |