CN107293503A - Test structure, preparation method and the method for testing of shared contact hole circuit defect - Google Patents
Test structure, preparation method and the method for testing of shared contact hole circuit defect Download PDFInfo
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- CN107293503A CN107293503A CN201710276138.8A CN201710276138A CN107293503A CN 107293503 A CN107293503 A CN 107293503A CN 201710276138 A CN201710276138 A CN 201710276138A CN 107293503 A CN107293503 A CN 107293503A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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Abstract
The invention provides a kind of test structure, preparation method and the method for testing of shared contact hole circuit defect, test structure has the first conductivity type of transistor；First conductivity type of transistor includes：Active area, the first grid set on active area and second grid, the bottom of one end of second grid are not provided with source region；Contact hole is shared in first grid source on first grid and contact hole is shared in the second gate source on one end of second grid；Share contact hole connection first grid one end and active area in first grid source；One end that contact hole only connects second grid is shared in second gate source, and the bottom that contact hole is shared in second gate source is not connected to active area.It can intuitively judge very much that second gate source shares whether contact hole occurs short circuit using the test structure of the present invention, be conducive to carrying out the monitoring of the Pingdu, technique and board of subsequent technique window.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, and in particular to a kind of test structure of shared contact hole circuit defect
And method of testing.
Background technology
With the development of integrated circuit technology, semiconductor processing dimensions are less and less, also become increasingly complex.Many techniques are whole
The process window of conjunction is less and less, such as the short circuit problem of contact hole and polysilicon, and it is by alignment precision and contact hole and many
The influence of crystal silicon critical size etc., is one of difficulties of below 28nm research and development techniques.
As shown in Fig. 1 to 5, wherein, Fig. 1 be wafer yield test schematic diagram, Fig. 2 be existing grid source share contact hole with
Grid produces the scanning electron microscope diagram piece of short circuit, and Fig. 3 is that the shared contact hole in existing grid source is normally swept with grid structure
Electron microscope picture is retouched, Fig. 4 is the electron beam scanning image schematic diagram of normal SRAM structures, and Fig. 5 is the shared contact in grid source
Hole produces the electron beam scanning image schematic diagram of the SRAM structures of short circuit with grid.Product shown in Fig. 2 is by crystal round fringes
Independent position (Single Bit, SB) failure it is serious the problem of, its physics failure analysis (Physical Failure
Analysis, PFA) result is shown as grid source and shares contact hole and polysilicon short problem, as shown in dotted line frame in Fig. 2.However,
For this electrical property failure problem, optical check does not have enough precision to carry out on-line monitoring, simultaneously because shared contact hole exists
In conventional SRAM structures, its one end can be connected with polysilicon, when its other end and another polysilicon short, not have electricity
The change of position, so the monitoring of electrical defect can not be carried out to it, as shown in Figure 5.
The content of the invention
In order to overcome problem above, the present invention is intended to provide test structure and the test of a kind of shared contact hole circuit defect
Method, so as to lift product yield.
In order to achieve the above object, the invention provides the test structure that contact hole circuit defect is shared in a kind of grid source, its
With the first conductivity type of transistor；First conductivity type of transistor includes：Active area, the first grid set on active area
Pole and second grid, the bottom of one end of second grid are not provided with source region；First grid source on first grid, which is shared, to be connect
Contact hole is shared in contact hole and the second gate source on described one end of second grid；Share contact hole connection first in first grid source
Grid one end and active area；Share described one end that contact hole only connects second grid, the shared contact in second gate source in second gate source
The bottom in hole is not connected to active area；Wherein,
When it is in conducting state that contact hole is shared in first grid source, second gate source shares the normal condition of contact hole not lead
Logical, it is conducting that the abnormality of contact hole is shared in second gate source.
Preferably, the shared contact hole bottom in second gate source is provided with isolation structure, and contact hole is shared with isolating in second gate source
Structure is in contact and is in contact simultaneously with described one end of second grid.
Preferably, the isolation structure that the setting of contact hole bottom is shared in the second gate source is fleet plough groove isolation structure.
Preferably, parallel arrangement between first grid and second grid.
Preferably, the active area includes N-type deep-well region and the p-type doped region in N-type deep-well region, the first grid
Pole is arranged on N-type deep-well region, and the first grid source is shared contact hole and is arranged on p-type doped region and the first grid；Or
Active area described in person includes N-type deep-well region and the n-type doping area in N-type deep-well region, and it is deep that the first grid is arranged at N-type
On well region, the first grid source is shared contact hole and is arranged in n-type doping area and the first grid；Or the active area bag
P-type deep-well region and the p-type doped region in p-type deep-well region are included, the first grid is arranged on p-type deep-well region, described
Share contact hole and be arranged on p-type doped region and the first grid in one grid source.
Preferably, the active area includes p-type deep-well region and the n-type doping area in p-type deep-well region, the first grid
Pole is arranged on p-type deep-well region, and the first grid source is shared contact hole and is arranged in n-type doping area and the first grid；Or
Active area described in person includes p-type deep-well region and the p-type doped region in p-type deep-well region, and it is deep that the first grid is arranged at p-type
On well region, the first grid source is shared contact hole and is arranged on p-type doped region and the first grid；Or the active area bag
N-type deep-well region and the n-type doping area in N-type deep-well region are included, the first grid is arranged on N-type deep-well region, described
Share contact hole and be arranged in n-type doping area and the first grid in one grid source.
Preferably, in addition to the second conductivity type of transistor；First conductivity type of transistor and the second conduction type crystal
Pipe is arranged alternately.
In order to achieve the above object, present invention also offers a kind of preparation method using above-mentioned test structure, it is wrapped
Include：
Step 01：One substrate is provided；The active area for the first conductivity type of transistor is prepared in the substrate；
Step 02：First grid and second grid are prepared on the active area of the first conductivity type of transistor；Wherein, second
One end bottom of grid is not located on active area；
Step 03：First grid source is prepared on first grid and active area and shares contact hole, described the one of second grid
Second gate source is prepared on end and shares contact hole；Wherein, described one end that contact hole only connects second grid is shared in second gate source, and
Share contact hole bottom and be not connected to active area in second gate source.
Preferably, in the step 01, in addition to：Active area exterior domain and corresponding to second gate source to be formed be total to
Enjoy contact hole isolation structure formed below.
Preferably, the active area includes N-type deep-well region and the p-type doped region in N-type deep-well region, the first grid
Pole is arranged on N-type deep-well region, and the first grid source is shared contact hole and is arranged on p-type doped region and the first grid；Or
Active area described in person includes N-type deep-well region and the n-type doping area in N-type deep-well region, and it is deep that the first grid is arranged at N-type
On well region, the first grid source is shared contact hole and is arranged in n-type doping area and the first grid；Or the active area bag
P-type deep-well region and the p-type doped region in p-type deep-well region are included, the first grid is arranged on p-type deep-well region, described
Share contact hole and be arranged on p-type doped region and the first grid in one grid source.
Preferably, the active area includes p-type deep-well region and the n-type doping area in p-type deep-well region, the first grid
Pole is arranged on p-type deep-well region, and the first grid source is shared contact hole and is arranged in n-type doping area and the first grid；Or
Active area described in person includes p-type deep-well region and the p-type doped region in p-type deep-well region, and it is deep that the first grid is arranged at p-type
On well region, the first grid source is shared contact hole and is arranged on p-type doped region and the first grid；Or the active area bag
N-type deep-well region and the n-type doping area in N-type deep-well region are included, the first grid is arranged on N-type deep-well region, described
Share contact hole and be arranged in n-type doping area and the first grid in one grid source.
In order to achieve the above object, present invention also offers a kind of using the above-mentioned shared contact in test structure progress grid source
The method of testing of hole circuit defect, it includes：
First, contact hole is shared to first grid source and second gate source shares contact hole and carries out electron beam scanning, first is obtained
Contact hole is shared in grid source and the scan-image of contact hole is shared in second gate source；
Then, according to obtained scan-image, judge whether shared contact hole circuit defect occur；Wherein, brightness is judged
The shared contact hole in abnormal second gate source is presented and circuit defect occurs.
Preferably, the active area of first conductivity type of transistor includes N-type deep-well region and positioned at N-type deep-well region
Interior p-type doped region, the first grid is arranged on N-type deep-well region, and the shared contact hole in the first grid source is arranged at p-type and mixed
In miscellaneous area and the first grid；Or the active area includes N-type deep-well region and the n-type doping area in N-type deep-well region,
The first grid is arranged on N-type deep-well region, and the first grid source shares contact hole and is arranged at n-type doping area and described first
On grid；Or the active area includes p-type deep-well region and the p-type doped region in p-type deep-well region, the first grid is set
It is placed on p-type deep-well region, the first grid source is shared contact hole and is arranged on p-type doped region and the first grid；
Positive potential electron beam scanning is then used, the shared contact hole in first grid source is obtained and sweeping for contact hole is shared in second gate source
Shading picture；
It is in bright hole to share contact hole when first grid source, and it is in dark holes that contact hole is shared in second gate source, and judgement draws second gate source
Shared contact hole does not have circuit defect；It is in bright hole to share contact hole when first grid source, when contact hole is shared in bright hole in second gate source,
Judgement show that the second gate source shares contact hole and circuit defect occurs.
Preferably, the active area of first conduction type includes p-type deep-well region and the N in p-type deep-well region
Type doped region, the first grid is arranged on p-type deep-well region, and the first grid source shares contact hole and is arranged at n-type doping area
On the first grid；It is described or the active area includes p-type deep-well region and the p-type doped region in p-type deep-well region
First grid is arranged on p-type deep-well region, and the first grid source shares contact hole and is arranged at p-type doped region and the first grid
On；Or the active area includes N-type deep-well region and the n-type doping area in N-type deep-well region, the first grid is arranged at
On N-type deep-well region, the first grid source is shared contact hole and is arranged in n-type doping area and the first grid；
Negative potential electron beam scanning is then used, the shared contact hole in first grid source is obtained and sweeping for contact hole is shared in second gate source
Shading picture；
It is in dark holes to share contact hole when first grid source, and it is in bright hole that contact hole is shared in second gate source, and judgement draws second gate source
Shared contact hole does not have circuit defect；It is in dark holes to share contact hole when first grid source, when contact hole is shared in dark holes in second gate source,
Judgement show that the second gate source shares contact hole and circuit defect occurs.
The test structure and method of testing of contact hole circuit defect are shared in the grid source of the present invention, by setting first grid source to be total to
Contact hole connection first grid and active area are enjoyed, second gate source shares contact hole and only connects second grid, and its bottom is not connected to
Active area, when contact hole is shared in second gate source occurs short circuit with neighbouring grid, the shared contact hole in second gate source, which can be presented, leads
Logical state, so that the scanning shadow that the electron beam scanning for sharing the shared contact hole of contact hole and second gate source according to first grid source is obtained
As can intuitively judge to show that second gate source shares contact hole and occurs circuit defect very much, progress subsequent technique window is conducive to comment
Estimate and technique and board condition monitoring.
Brief description of the drawings
Fig. 1 is wafer yield test schematic diagram
Fig. 2 is that the scanning electron microscope diagram piece that contact hole produces short circuit with grid is shared in existing grid source
Fig. 3 is that contact hole and the normal scanning electron microscope diagram piece of grid structure are shared in existing grid source
Fig. 4 is the electron beam scanning image schematic diagram of normal SRAM structures
Fig. 5 is that the electron beam scanning image schematic diagram that contact hole produces the SRAM structures of short circuit with grid is shared in grid source
Fig. 6 is the electron beam scanning image schematic diagram of the normal SRAM structures of the preferred embodiment of the present invention
For the SRAM structures of the preferred embodiment of the present invention electronics that contact hole circuit defect is shared in grid source occurs for Fig. 7
Beam scanning image schematic diagram
Fig. 8 is the equivalent structure schematic diagram of the normal test structure of the preferred embodiment of the present invention
Fig. 9 shares the equivalent knot of the test structure of contact hole short circuit for the generation grid source of the preferred embodiment of the present invention
Structure schematic diagram
Figure 10 is that contact hole short circuit is shared in the preparation method of the test structure of the preferred embodiment of the present invention and grid source
The schematic flow sheet of the method for testing of defect
Embodiment
To make present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is made into one
Walk explanation.Certainly the invention is not limited in the specific embodiment, the general replacement known to those skilled in the art
Cover within the scope of the present invention.
The present invention is described in further detail below in conjunction with accompanying drawing 6~10 and specific embodiment.It should be noted that, accompanying drawing
Using very simplified form, using non-accurately ratio, and only to facilitate, clearly reach aid illustration the present embodiment
Purpose.
Fig. 6 and Fig. 8 are referred to, the test structure of contact hole circuit defect is shared in a kind of grid source of the present embodiment, with the
One conductivity type of transistor, is here PMOS transistor.In the present embodiment, test structure also includes the second conduction type crystal
Pipe, can be here nmos pass transistor, as shown in dotted line frame in Fig. 6；First conductivity type of transistor PMOS and second is conductive
Type of transistor NMOS is arranged alternately.
Referring to Fig. 6, first conductivity type of transistor PMOS includes：
Active area AA, the first grid G1 set on active area AA and second grid G2, second grid G2 one end
Bottom be not provided with source region AA；Share contact hole K1 and positioned at second grid G2's in first grid source on first grid G1
Share contact hole K2 in second gate source on one end；Share contact hole K1 connection first grids G1 one end and active area in first grid source
AA；One end that contact hole K2 only connects second grid G2 is shared in second gate source, and contact hole hole K2 bottom is shared not in second gate source
Connect active area AA.
In the present embodiment, referring to Fig. 8, contact hole K2 bottoms are shared in second gate source is provided with fleet plough groove isolation structure STI,
Share contact hole K2 and be in contact and be in contact simultaneously with second grid G2 one end, it is necessary to say with isolation structure STI in second gate source
Bright, in the present embodiment, the isolation structure that the setting of contact hole K2 bottoms is shared in second gate source is fleet plough groove isolation structure STI.
In other embodiments of the invention, second gate source share isolation structure that contact hole K2 bottoms set can also for it is other can be with
Play the structure of buffer action.
Referring to Fig. 6, parallel arrangement at certain intervals between first grid G1 and second grid G2.
Referring to Fig. 8, according to when second gate source shares contact hole K2 and occurs short circuit with neighbouring grid, second gate
Contact hole K2 is shared in source can be presented conducting state, and the first conductivity type of transistor of the test structure of the present embodiment includes：It is active
Area AA includes N-type deep-well region N-Well and p-type doped region P+, first grid K1 in N-type deep-well region are arranged at N-type deep trap
On area N-Well, first grid source is shared contact hole K1 and is arranged on p-type doped region P+ and first grid G1；Or first conductive-type
Transistor npn npn, which is also provided with source region, includes N-type deep-well region and the n-type doping area in N-type deep-well region, and first grid is set
It is placed on N-type deep-well region, first grid source is shared contact hole and is arranged in n-type doping area and the first grid；Or first lead
Electric type of transistor, which is also provided with source region, includes p-type deep-well region and the p-type doped region in p-type deep-well region, the first grid
Pole is arranged on p-type deep-well region, and first grid source is shared contact hole and is arranged on p-type doped region and first grid.In addition, second leads
The type of electric type of transistor and the first conductivity type of transistor is on the contrary, when the first conductivity type of transistor is PMOS, second
Conductivity type of transistor is NMOS, as shown in figure 8, the second conductivity type of transistor NMOS is n-type doping area N+ on p-type deep-well region
Constitute.
In addition, in other embodiments of the invention, test structure shares contact hole and neighbouring grid according to when second gate source
When short circuit occurs for pole, contact hole is shared in second gate source can be presented conducting state, and the transistor of the first conduction type can also be set：
Active area includes p-type deep-well region and the n-type doping area in p-type deep-well region, and first grid is arranged on p-type deep-well region, the
Share contact hole and be arranged on n-type doping area and first grid in one grid source；Or first the transistor of conduction type can also set
Being equipped with source region includes p-type deep-well region and the p-type doped region in p-type deep-well region, and first grid is arranged on p-type deep-well region,
Share contact hole and be arranged on p-type doped region and first grid in first grid source；Or first the transistor of conduction type can be with
Active area is set to include N-type deep-well region and the n-type doping area in N-type deep-well region, first grid is arranged at N-type deep-well region
On, first grid source is shared contact hole and is arranged on n-type doping area and first grid.
For above-mentioned all possible test structure, when it is in conducting state that contact hole is shared in first grid source, second gate source
The normal condition of shared contact hole illustrates that second gate source shares contact hole and do not occur circuit defect to be not turned on；Second gate source
The abnormality of shared contact hole is conducting, then illustrates that second gate source shares contact hole and circuit defect occurs.
In addition, referring to the preparation that a kind of test structure above-mentioned to the present embodiment is also provided in Fig. 6 to 10, the present embodiment
Method includes：
Step 01：One substrate is provided；The active area AA for the first conductivity type of transistor PMOS is prepared in the substrate；
Specifically, this step also includes：Active area exterior domain and corresponding to the shared contact in second gate source to be formed
Hole K2 isolation structure STI formed below.It should be noted that also there is the second conductivity type of transistor NMOS in the present embodiment,
When now preparing the first conductivity type of transistor NMOS, the second conductivity type of transistor PMOS can be prepared synchronously, can also be first
Prepare the first conductivity type of transistor NMOS and prepare the second conductivity type of transistor PMOS again, or vice versa also may be used.In addition it is also necessary to
Illustrate, because the present embodiment is test structure, the preparation work that the preparation technology of test structure can be with proper device structure
Skill is mutually compatible, and that is to say synchronously to prepare, simply in this step 01, in active area AA exterior domain and right in test structure
Contact hole K2 isolation structure STI formed below should be shared in second gate source to be formed；And it is not required to this in proper device structure
Step.
Step 02：First grid G2 and second grid are prepared on the first conductivity type of transistor NMOS active area AA
G2；Wherein, second grid G2 one end bottom is not located on active area AA；
Step 03：First grid source is prepared on first grid G1 and active area AA and shares contact hole K1, in second grid G2
On prepare second gate source and share contact hole K2；Wherein, the shared contact hole K2 in second gate source only connects second grid G2, and its bottom
It is not connected to active area AA；
Connect, description carries out the test that contact hole circuit defect is shared in grid source using the above-mentioned test structure of the present embodiment
Method, including：
Step 04：Contact hole K1 is shared to first grid source and second gate source shares contact hole K2 and carries out electron beam scanning, is obtained
Contact hole K1 is shared to first grid source and contact hole K2 scan-image is shared in second gate source；
Step 05：According to obtained scan-image, judge whether shared contact hole circuit defect occur；Wherein, judge bright
Degree is presented the shared contact hole in abnormal second gate source and circuit defect occurs.
It is in conducting state to share contact hole K1 when first grid source, when contact hole K2 is shared in not on-state in second gate source,
Judgement show that second gate source shares contact hole K2 and do not have circuit defect；It is in conducting state to share contact hole K1 when first grid source, the
When contact hole K2 is shared in conducting state in two grid sources, judgement show that second gate source shares contact hole K2 and circuit defect occurs.
For example, referring to Fig. 8, the first conductivity type of transistor PMOS of the present embodiment active area AA includes N-type
Deep-well region N-Well and the p-type doped region P+ in N-type deep-well region, first grid K1 are arranged on the N-Well of N-type deep-well region,
Share contact hole K1 and be arranged on p-type doped region P+ and first grid G1 in first grid source；Or first conductivity type of transistor also
Active area can be set to include N-type deep-well region and the n-type doping area in N-type deep-well region, first grid is arranged at N-type deep trap
Share contact hole and be arranged in n-type doping area and the first grid in Qu Shang, first grid source；Or first conductivity type of transistor
Being also provided with source region includes p-type deep-well region and the p-type doped region in p-type deep-well region, and it is deep that first grid is arranged at p-type
On well region, first grid source is shared contact hole and is arranged on p-type doped region and first grid.
For above-mentioned possible several test structures, when contact hole K1 conductings are shared in first grid source, second gate source is shared to be connect
Contact hole K2 is not turned on to be normal, if it is also in conducting state that contact hole K2 is shared in second gate source, to be abnormal.Above-mentioned steps 04
In, using positive potential electron beam scanning, obtain the scanning that contact hole K1 and the shared contact hole K2 in second gate source are shared in first grid source
Image, such as Fig. 6 and 7；
In above-mentioned steps 05, if it is in bright hole that contact hole K1 is shared in first grid source, it is in dark holes that contact hole K2 is shared in second gate source,
Illustrate that contact hole K1 conductings are shared in first grid source, second gate source is shared contact hole K2 and is not turned on, and judgement show that second gate source is shared
Contact hole K2 does not have circuit defect, as seen in figs. 6 and 8；It is in bright hole to share contact hole K1 when first grid source, and second gate source is shared to be connect
When contact hole K2 is in bright hole, illustrate that contact hole K1 conductings are shared in first grid source, the shared contact hole K2 conductings in second gate source occur different
Often, judge to show that second gate source shares contact hole K2 and circuit defect occurs, as shown in figures 7 and 9, arrow is signified in Fig. 7 one
Second gate source shares contact hole K2 and brightness change occurs, represents that this second gate source shares contact hole K2 and short circuit occurs.
In addition, including p-type deep-well region and the N-type in p-type deep-well region for the active area of other embodiments of the present invention
Doped region, first grid is arranged on p-type deep-well region, and first grid source shares contact hole and is arranged at n-type doping area and first grid
On；Or active area includes p-type deep-well region and the p-type doped region in p-type deep-well region, first grid is arranged at p-type deep trap
Share contact hole and be arranged on p-type doped region and first grid in Qu Shang, first grid source；Or active area include N-type deep-well region and
N-type doping area in N-type deep-well region, first grid is arranged on N-type deep-well region, and first grid source is shared contact hole and is arranged at
In n-type doping area and the first grid；For such test structure, in above-mentioned steps 04, swept using negative potential electron beam
Retouch, obtain the scan-image that the shared contact hole of contact hole and second gate source is shared in first grid source；In above-mentioned steps 05, work as the first grid
It is in dark holes that contact hole is shared in source, and it is in bright hole that contact hole is shared in second gate source, illustrates that contact hole conducting, second gate are shared in first grid source
Source is shared contact hole and is not turned on, and judgement show that second gate source shares contact hole and do not have circuit defect；When the shared contact in first grid source
Hole is in dark holes, when contact hole is shared in dark holes in second gate source, illustrates that contact hole conducting is shared in first grid source, and second gate source is shared
Exception occurs for contact hole conducting, and judgement show that second gate source shares contact hole and circuit defect occurs.
Although the present invention is disclosed as above with preferred embodiment, right embodiment is illustrated only for the purposes of explanation, and
Be not used to limit the present invention, those skilled in the art can make without departing from the spirit and scope of the present invention it is some more
Dynamic and retouching, the protection domain that the present invention is advocated should be defined by claims.
Claims (14)
1. the test structure of contact hole circuit defect is shared in a kind of grid source, it is characterised in that with the first conductivity type of transistor；
First conductivity type of transistor includes：Active area, the first grid set on active area and second grid, second grid
The bottom of one end is not provided with source region；Share contact hole and positioned at described in second grid in first grid source on first grid
Share contact hole in second gate source on one end；Share contact hole connection first grid one end and active area in first grid source；Second gate
Described one end that contact hole only connects second grid is shared in source, and the bottom that contact hole is shared in second gate source is not connected to active area；Its
In,
When it is in conducting state that contact hole is shared in first grid source, the normal condition of contact hole is shared to be not turned in second gate source, the
It is conducting that the abnormality of contact hole is shared in two grid sources.
2. test structure according to claim 1, it is characterised in that share contact hole bottom and be provided with isolation in second gate source
Share contact hole and be in contact and be in contact simultaneously with described one end of second grid with isolation structure in structure, second gate source.
3. test structure according to claim 2, it is characterised in that share what contact hole bottom was set in the second gate source
Isolation structure is fleet plough groove isolation structure.
4. test structure according to claim 1, it is characterised in that parallel arrangement between first grid and second grid.
5. test structure according to claim 1 or 2, it is characterised in that the active area includes N-type deep-well region and is located at
P-type doped region in N-type deep-well region, the first grid is arranged on N-type deep-well region, and the first grid source is shared contact hole and set
It is placed on p-type doped region and the first grid；Or the active area includes N-type deep-well region and the N in N-type deep-well region
Type doped region, the first grid is arranged on N-type deep-well region, and the first grid source shares contact hole and is arranged at n-type doping area
On the first grid；It is described or the active area includes p-type deep-well region and the p-type doped region in p-type deep-well region
First grid is arranged on p-type deep-well region, and the first grid source shares contact hole and is arranged at p-type doped region and the first grid
On.
6. test structure according to claim 1 or 2, it is characterised in that the active area includes p-type deep-well region and is located at
N-type doping area in p-type deep-well region, the first grid is arranged on p-type deep-well region, and the first grid source is shared contact hole and set
It is placed in n-type doping area and the first grid；Or the active area includes p-type deep-well region and the P in p-type deep-well region
Type doped region, the first grid is arranged on p-type deep-well region, and the first grid source shares contact hole and is arranged at p-type doped region
On the first grid；It is described or the active area includes N-type deep-well region and the n-type doping area in N-type deep-well region
First grid is arranged on N-type deep-well region, and the first grid source shares contact hole and is arranged at n-type doping area and the first grid
On.
7. test structure according to claim 1, it is characterised in that also including the second conductivity type of transistor；First leads
Electric type of transistor and the second conductivity type of transistor are arranged alternately.
8. a kind of preparation method of the test structure described in use claim 1, it is characterised in that including：
Step 01：One substrate is provided；The active area for the first conductivity type of transistor is prepared in the substrate；
Step 02：First grid and second grid are prepared on the active area of the first conductivity type of transistor；Wherein, second grid
One end bottom not be located at active area on；
Step 03：First grid source is prepared on first grid and active area and shares contact hole, on described one end of second grid
Prepare second gate source and share contact hole；Wherein, described one end that contact hole only connects second grid, and second are shared in second gate source
Share contact hole bottom and be not connected to active area in grid source.
9. preparation method according to claim 8, it is characterised in that in the step 01, in addition to：Outside active area
Region and share contact hole isolation structure formed below corresponding to second gate source to be formed.
10. preparation method according to claim 8, it is characterised in that the active area includes N-type deep-well region and positioned at N
P-type doped region in moldeed depth well region, the first grid is arranged on N-type deep-well region, and the first grid source is shared contact hole and set
It is placed on p-type doped region and the first grid；Or the active area includes N-type deep-well region and the N in N-type deep-well region
Type doped region, the first grid is arranged on N-type deep-well region, and the first grid source shares contact hole and is arranged at n-type doping area
On the first grid；It is described or the active area includes p-type deep-well region and the p-type doped region in p-type deep-well region
First grid is arranged on p-type deep-well region, and the first grid source shares contact hole and is arranged at p-type doped region and the first grid
On.
11. preparation method according to claim 8, it is characterised in that the active area includes p-type deep-well region and positioned at P
N-type doping area in moldeed depth well region, the first grid is arranged on p-type deep-well region, and the first grid source is shared contact hole and set
It is placed in n-type doping area and the first grid；Or the active area includes p-type deep-well region and the P in p-type deep-well region
Type doped region, the first grid is arranged on p-type deep-well region, and the first grid source shares contact hole and is arranged at p-type doped region
On the first grid；It is described or the active area includes N-type deep-well region and the n-type doping area in N-type deep-well region
First grid is arranged on N-type deep-well region, and the first grid source shares contact hole and is arranged at n-type doping area and the first grid
On.
12. the test structure described in a kind of use claim 1 carries out the method for testing that contact hole circuit defect is shared in grid source, its
It is characterised by, including：
First, contact hole is shared to first grid source and second gate source shares contact hole and carries out electron beam scanning, first grid source is obtained
The scan-image of contact hole is shared in shared contact hole and second gate source；
Then, according to obtained scan-image, judge whether shared contact hole circuit defect occur；Wherein, judge that brightness is presented
Share contact hole and circuit defect occur in abnormal second gate source.
13. the method for testing of contact hole circuit defect is shared in grid source according to claim 12, it is characterised in that described the
The active area of one conductivity type of transistor includes N-type deep-well region and the p-type doped region in N-type deep-well region, described the
One grid is arranged on N-type deep-well region, and the first grid source shares contact hole and is arranged at p-type doped region and the first grid
On；Or the active area includes N-type deep-well region and the n-type doping area in N-type deep-well region, the first grid is arranged at
On N-type deep-well region, the first grid source is shared contact hole and is arranged in n-type doping area and the first grid；Or described have
Source region includes p-type deep-well region and the p-type doped region in p-type deep-well region, and the first grid is arranged on p-type deep-well region,
Share contact hole and be arranged on p-type doped region and the first grid in the first grid source；
Positive potential electron beam scanning is then used, the scanning shadow that the shared contact hole of contact hole and second gate source is shared in first grid source is obtained
Picture；
It is in bright hole to share contact hole when first grid source, and it is in dark holes that contact hole is shared in second gate source, and judgement show that second gate source is shared
Contact hole does not have circuit defect；It is in bright hole to share contact hole when first grid source, when contact hole is shared in bright hole in second gate source, is judged
Show that the second gate source shares contact hole and circuit defect occurs.
14. the method for testing of contact hole circuit defect is shared in grid source according to claim 12, it is characterised in that described the
The active area of one conduction type includes p-type deep-well region and the n-type doping area in p-type deep-well region, the first grid
It is arranged on p-type deep-well region, the first grid source is shared contact hole and is arranged in n-type doping area and the first grid；Or
The active area includes p-type deep-well region and the p-type doped region in p-type deep-well region, and the first grid is arranged at p-type deep trap
Share contact hole and be arranged on p-type doped region and the first grid in Qu Shang, the first grid source；Or the active area includes
N-type deep-well region and the n-type doping area in N-type deep-well region, the first grid are arranged on N-type deep-well region, and described first
Share contact hole and be arranged in n-type doping area and the first grid in grid source；
Negative potential electron beam scanning is then used, the scanning shadow that the shared contact hole of contact hole and second gate source is shared in first grid source is obtained
Picture；
It is in dark holes to share contact hole when first grid source, and it is in bright hole that contact hole is shared in second gate source, and judgement show that second gate source is shared
Contact hole does not have circuit defect；It is in dark holes to share contact hole when first grid source, when contact hole is shared in dark holes in second gate source, is judged
Show that the second gate source shares contact hole and circuit defect occurs.
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| US11955195B2 (en) | 2021-10-06 | 2024-04-09 | Samsung Electronics Co., Ltd. | Semiconductor memory device with defect detection capability |
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| CN102376600A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Evaluation method for failure of contact hole |
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| CN103107163A (en) * | 2011-11-11 | 2013-05-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor test structure and forming method and testing method thereof |
| CN103354211A (en) * | 2013-06-25 | 2013-10-16 | 上海华力微电子有限公司 | Method for measuring and calculating alignment deviation of contact holes and polycrystalline silicon gates |
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| CN102376600A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Evaluation method for failure of contact hole |
| CN103107163A (en) * | 2011-11-11 | 2013-05-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor test structure and forming method and testing method thereof |
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