CN107275212B - Method for forming semiconductor structure - Google Patents
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- CN107275212B CN107275212B CN201610213608.1A CN201610213608A CN107275212B CN 107275212 B CN107275212 B CN 107275212B CN 201610213608 A CN201610213608 A CN 201610213608A CN 107275212 B CN107275212 B CN 107275212B
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- 238000000034 method Methods 0.000 title claims abstract description 112
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 239000010410 layer Substances 0.000 claims abstract description 255
- 238000005530 etching Methods 0.000 claims abstract description 105
- 230000008569 process Effects 0.000 claims abstract description 81
- 239000011241 protective layer Substances 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000001312 dry etching Methods 0.000 claims abstract description 37
- 238000001039 wet etching Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 239000003085 diluting agent Substances 0.000 claims description 7
- 230000005281 excited state Effects 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 239000006227 byproduct Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000009825 accumulation Methods 0.000 claims description 3
- 241000695274 Processa Species 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000011068 loading method Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 238000000635 electron micrograph Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
A method of forming a semiconductor structure, comprising: providing a substrate; forming a gate structure on a substrate; forming a protective layer on the top of the gate structure; forming a stop layer on the side wall of the gate structure and the protective layer; forming a dielectric layer exposing the stop layer on the substrate between the grid structures; and etching and removing the stop layer on the top of the protective layer by adopting a plasma dry etching process, and etching by adopting plasma in a discontinuous mode to ensure that the etching rate of the protective layer is less than that of the stop layer. The energy of the plasma can be reduced in a discontinuous mode, so that the energy is between the energy required for removing the stop layer and the energy required for removing the protective layer, and the etching rate of the protective layer by the plasma is lower than that of the stop layer. When the residual stop layer is continuously etched in a part of the area with the residual stop layer, the loss of the exposed protective layer can be reduced, or the damage of the grid structure caused by excessive loss of the protective layer can be avoided, so that the electrical performance of the semiconductor device is improved.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a method for forming a semiconductor structure.
Background
In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. To accommodate the reduction in feature size, the channel length of MOSFET fets has also been correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE) phenomenon, so-called short-channel effect (SCE), is easier to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFET transistors to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) at least from two sides, the control capability of the gate on a channel is much stronger than that of a planar MOSFET device, and the short channel effect can be well inhibited; and compared with other devices, the FinFET has better compatibility of the existing integrated circuit manufacturing technology.
However, even with the introduction of the finfet, the electrical performance of the prior art semiconductor device is still poor.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which optimizes the electrical performance of a semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising the steps of: providing a substrate; forming a gate structure on the substrate; forming a protective layer on the top of the gate structure; forming a stop layer on the side wall of the gate structure and the protective layer; forming a dielectric layer on the substrate between the grid electrode structures, wherein the dielectric layer exposes out of the stop layer on the protective layer; and etching and removing the stop layer on the top surface of the protective layer by adopting a plasma dry etching process, wherein in the plasma dry etching process, the stop layer is etched by the plasma in a discontinuous mode, so that the etching rate of the plasma on the protective layer is smaller than that on the stop layer.
Optionally, the step of etching the stop layer by the plasma in an intermittent manner includes: and outputting radio frequency power in a pulse output mode, outputting radio frequency bias in a pulse output mode, and synchronizing the radio frequency power and the pulse of the radio frequency bias so as to etch the stop layer in an intermittent mode.
Optionally, the plasma dry etching process includes a plurality of pulse periods; and within one pulse period, the duty ratio of the radio frequency bias voltage or the radio frequency power is output to be 20-90%.
Optionally, the process time of the plasma dry etching process is 5s to 30s, and the time of one pulse period is 0.2ms to 0.07 ms.
Optionally, the plasma dry etching process includes: the etching gas is NF3And CF4And the diluent gas is Ar.
Optionally, in the step of the plasma dry etching process, NF3The gas flow rate of (1) is 20sccm to 100sccm, CF4The gas flow of the gas is 60sccm to 300sccm, the gas flow of Ar is 50sccm to 500sccm, the pressure is 10mTorr to 50mTorr, the etching frequency is 5000HZ to 15000HZ, the radio frequency bias is 5V to 35V, and the radio frequency power is 10W to 70W.
Optionally, the etching selection ratio of the plasma dry etching process to the protective layer and the stop layer is 1:1 to 1: 20.
Optionally, the material of the protective layer is silicon oxide.
Optionally, the thickness of the protective layer is 1.8nm to 2.2 nm.
Optionally, the stop layer is made of silicon nitride.
Optionally, after the dielectric layer is formed, the thickness of the stop layer is 0nm to 8.5 nm.
Optionally, the forming method further includes: and after the dielectric layer is formed, removing the natural oxide layer on the surface of the stop layer before the stop layer on the top surface of the protective layer is removed by adopting a plasma dry etching process.
Optionally, the natural oxide layer is made of silicon oxide.
Optionally, the process of removing the natural oxide layer on the surface of the stop layer is a wet etching process or a dry etching process.
Optionally, removing the natural oxide layer on the surface of the stop layer by using a wet etching process, wherein an etching solution used by the wet etching process is hydrofluoric acid; or, removing the natural oxide layer on the surface of the stop layer by adopting a dry etching process, wherein the etching gas of the dry etching process is CF4。
Optionally, the substrate includes an N-type region and a P-type region; and in the step of removing the stop layer on the top surface of the protective layer by adopting a plasma dry etching process, the etching rate of the stop layer in the P-type area is greater than that of the stop layer in the N-type area.
Optionally, the base includes a substrate and a fin portion protruding from the substrate; the gate structure crosses over the fin and covers a portion of a top surface and a sidewall surface of the fin.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the invention, the stop layer is etched by the plasma in a discontinuous mode, and the energy of the plasma can be reduced in a discontinuous mode, so that the energy of the plasma is between the energy required for removing the stop layer and the energy required for removing the protective layer, and the etching rate of the protective layer by the plasma is lower than the etching rate of the stop layer. When the residual stop layer is continuously etched in a part of the area, the loss of the exposed protective layer can be reduced, or the problem of grid structure damage caused by excessive loss of the protective layer can be avoided, so that the electrical performance of the semiconductor device is improved.
In an alternative scheme, the substrate comprises an N-type region and a P-type region, when a stop layer of the P-type region is removed and a residual stop layer of the N-type region is continuously etched, because the stop layer is etched by plasma in an intermittent mode, the etching rate of the protective layer by the plasma is smaller than that of the stop layer, and the etching selection ratio of the protective layer to the stop layer can reach 1:1 to 1:20, the stop layer of the N-type region can be removed to overcome the load effect between the N-type region and the P-type region, the loss of the protective layer of the P-type region can be reduced when the residual stop layer of the N-type region is continuously etched, or the problem of damage of a grid structure of the P-type region caused by excessive loss of the protective layer of the P-type region is avoided, so that the electrical performance of a semiconductor device is improved.
In an alternative scheme, the stopping layer is etched by the plasma in a discontinuous mode, and when the radio frequency bias voltage and the radio frequency power are in an off state, the plasma is in a non-excited state, so that etching polymers generated by an etching process can be discharged, accumulation of etching byproducts is avoided, and the etching efficiency can be improved.
Drawings
FIGS. 1-4 are schematic structural diagrams corresponding to steps in a method of forming a semiconductor structure according to the prior art;
FIGS. 5-12 are schematic structural diagrams corresponding to steps of a method of forming a semiconductor structure according to an embodiment of the present invention;
FIG. 13 is a schematic diagram of the plasma discontinuous output mode in the plasma dry etching process of the present invention;
fig. 14 and 15 are electron micrographs of a semiconductor structure after removal of the stop layer in an embodiment of the method of forming the semiconductor structure of the invention.
Detailed Description
The electrical performance of the semiconductor device of the prior art is poor, and referring to fig. 1 to 4, a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the prior art is shown.
Referring to fig. 1 and 2, a substrate 100 is provided, the substrate 100 being used to form a finfet transistor. The substrate 100 includes a P-type region (shown in fig. 1) and an N-type region (shown in fig. 2), wherein the P-type region substrate 100 is used to form a PMOS (shown in fig. 1) and the N-type region substrate 100 is used to form an NMOS (shown in fig. 2).
A first gate structure 110 is formed on the P-type region substrate 100, a first protective layer 112 is formed on the top of the first gate structure 110, and a first stop layer 111 is formed on the sidewall of the first gate structure 110 and the top of the first protective layer 112; a second gate structure 120 is formed on the N-type region substrate 100, a second protection layer 122 is formed on the top of the second gate structure 120, and a second stop layer 121 is formed on the sidewall of the second gate structure 120 and the top of the second protection layer 122. A dielectric layer 130 is formed on the substrate 100 to cover sidewalls of the first gate structure 110 and the second gate structure 120.
When the dielectric layer 130 is polished, the dielectric layer is first polished until the tops of the first stop layer 111 and the second stop layer 121 are exposed; when further grinding is performed, the first stop layer 111 and the second stop layer 121 are ground and removed while the dielectric layer 130 is ground and removed.
However, due to the loading effect between the PMOS region and the NMOS region, the polishing rate of the first stop layer 111 of the PMOS region is much greater than that of the second stop layer 121 of the NMOS region, and when the first stop layer 111 is removed by polishing and the first passivation layer 112 is exposed (as shown in fig. 1), the second stop layer 121 remains (as shown in fig. 2) and has a large residual amount; when the polishing process is continued to remove the remaining second stop layer 121, the polishing process also polishes the PMOS region, which easily results in the first protection layer 112 being worn. Even when the second stop layer 121 is polished to remove and expose the second protection layer 122 (as shown in fig. 4), the first protection layer 112 is polished to remove and expose the first gate structure 110 (as shown in fig. 3), and the first gate structure 110 is easily damaged, thereby deteriorating the electrical performance of the semiconductor device.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate; forming a gate structure on the substrate; forming a protective layer on the top of the gate structure; forming a stop layer on the side wall of the gate structure and the protective layer; forming a dielectric layer on the substrate between the grid electrode structures, wherein the dielectric layer exposes out of the stop layer on the protective layer; and etching and removing the stop layer on the top surface of the protective layer by adopting a plasma dry etching process, wherein in the plasma dry etching process, the stop layer is etched by the plasma in a discontinuous mode, so that the etching rate of the plasma on the protective layer is smaller than that on the stop layer.
According to the invention, the stop layer is etched by the plasma in a discontinuous mode, and the energy of the plasma can be reduced in a discontinuous mode, so that the energy of the plasma is between the energy required for removing the stop layer and the energy required for removing the protective layer, and the etching rate of the protective layer by the plasma is lower than the etching rate of the stop layer. When the residual stop layer is continuously etched in a part of the area, the loss of the exposed protective layer can be reduced, or the problem of grid structure damage caused by excessive loss of the protective layer can be avoided, so that the electrical performance of the semiconductor device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 5 and 6, a substrate is provided.
The substrate comprises an N-type region and a P-type region, wherein the P-type region is used for forming a P-type semiconductor device (shown in figure 5), and the N-type region is used for forming an N-type semiconductor device (shown in figure 6).
In this embodiment, the N-type region and the P-type region are non-adjacent regions. In other embodiments, the N-type region and the P-type region may also be adjacent regions.
In this embodiment, the base is used to form a fin field effect transistor (FinFET), and accordingly, the base includes a substrate 200 and a fin (not shown) protruding from the substrate 200.
The substrate 200 is made of silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide, and the substrate 200 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; the fin portion comprises silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide. In this embodiment, the substrate 200 is a silicon substrate, and the fin portion is made of silicon.
In another embodiment, the base may also be used to form a planar transistor, the base being a planar base that is a silicon substrate, a germanium substrate, a silicon germanium substrate or a silicon carbide substrate, a silicon-on-insulator substrate or a germanium-on-insulator substrate, a glass substrate, or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate, etc.).
With continued reference to fig. 5 and 6, a gate structure is formed on the substrate.
In this embodiment, a first gate structure 210 is formed on the P-type region substrate (as shown in fig. 5), and a second gate structure 220 is formed on the N-type region substrate (as shown in fig. 6).
The base is used for forming a fin field effect transistor (FinFET), and includes a substrate 200 and a fin (not labeled) protruding from the substrate 200. Correspondingly, the first gate structure 210 spans across the P-region fins and covers a portion of the top surface and the sidewall surface of the P-region fins, and the second gate structure 220 spans across the N-region fins and covers a portion of the top surface and the sidewall surface of the N-region fins.
In this embodiment, the material of the first gate structure 210 and the second gate structure 220 includes polysilicon.
In another embodiment, the substrate may also be used to form a planar transistor, the substrate being a planar substrate. Correspondingly, the gate structure is formed on the surface of the planar substrate.
With continued reference to fig. 5 and 6, a protective layer is formed atop the gate structure.
The protective layer is used for protecting the top of the grid structure and preventing the grid structure from being damaged in the subsequent process.
In this embodiment, the step of forming the protection layer on the top of the gate structure includes: a first passivation layer 212 is formed on the surface of the first gate structure 210 (as shown in fig. 5), and a second passivation layer 222 is formed on the surface of the second gate structure 220 (as shown in fig. 6).
In this embodiment, a rapid thermal oxidation process is adopted to oxidize the surface of the gate structure layer to form the first protection layer 212 and the second protection layer 222. The first gate structure 210 and the second gate structure 220 are made of polysilicon, and correspondingly, the first protection layer 212 and the second protection layer 222 are made of silicon oxide.
In this embodiment, the thickness of the first protective layer 212 and the second protective layer 222 is 1.8nm to 2.2 nm.
Referring to fig. 7 and 8, fig. 7 is a schematic structural diagram based on fig. 5, and fig. 8 is a schematic structural diagram based on fig. 6, and a stop layer is formed on the side wall of the gate structure and the protective layer.
The stop layer is used as an etching stop layer in the subsequent contact hole etching process and also can be used as a stop position of the subsequent planarization process.
In this embodiment, the stop layer includes a first stop layer 211 (shown in fig. 7) covering the sidewall surface of the first gate structure 210 and the top surface of the first protection layer 212, and a second stop layer 221 (shown in fig. 8) covering the sidewall surface of the second gate structure 220 and the top surface of the second protection layer 222.
In this embodiment, the first stop layer 211 and the second stop layer 221 are formed by a chemical vapor deposition process.
The material of the first stop layer 211 and the second stop layer 221 is silicon nitride.
Referring to fig. 9 and 10, fig. 9 is a schematic structural diagram based on fig. 7, and fig. 10 is a schematic structural diagram based on fig. 8, a dielectric layer 230 is formed on the substrate between the gate structures, and the dielectric layer 230 exposes the stop layer on the protection layer.
The dielectric layer 230 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the dielectric layer 230 is made of silicon oxide.
In this embodiment, the top of the dielectric layer 230 is flush with the top surfaces of the first stop layer 211 (shown in fig. 9) and the second stop layer 221 (shown in fig. 10) and exposes the top surfaces of the first stop layer 211 and the second stop layer 221.
In this embodiment, the dielectric layer 230 is a stacked structure, and includes a first dielectric layer (not shown) on the surface of the substrate and a second dielectric layer (not shown) on the surface of the first dielectric layer.
Specifically, the step of forming the dielectric layer 230 includes: filling a first dielectric film on the substrate between the fin portion (not labeled) and the fin portion, wherein the first dielectric film further covers the first gate structure 210 (shown in fig. 9) and the second gate structure 220 (shown in fig. 10), and the top of the first dielectric film is higher than the top of the first stop layer 211 and the second stop layer 221; planarizing the first dielectric film until the top surfaces of the first stop layer 211 and the second stop layer 221 are exposed; etching back to remove part of the first dielectric film to form a first dielectric layer; forming a second dielectric film on the surface of the first dielectric layer, wherein the second dielectric film also covers the surfaces of the first gate structure 210 and the second gate structure 220, and the top of the second dielectric film is higher than the tops of the first stop layer 211 and the second stop layer 221; and flattening the second dielectric film until the top of the first stop layer 211 and the top surface of the second stop layer 221 are exposed so as to form a second dielectric layer.
The density of the second dielectric layer is greater than that of the first dielectric layer, and the second dielectric layer is used for improving the surface flatness of the second dielectric layer in a planarization process.
In this embodiment, in order to improve a gap-filling capability of the first dielectric film, so that the first dielectric layer has better adhesion, and avoid forming a cavity in the first dielectric layer later, a Flowable Chemical Vapor Deposition (FCVD) process is used to form the first dielectric film. In addition, in order to improve the compactness of the second dielectric film, a High Aspect Ratio (HARP) deposition process is adopted to form the second dielectric film.
After the second dielectric layer is formed, the stop layer in a partial region is removed by grinding, and a partial thickness of the stop layer in a partial region is still remained. Therefore, in this embodiment, after the dielectric layer is formed, the thicknesses of the first stop layer 211 and the second stop layer 221 are 0nm to 8.5 nm.
Referring to fig. 11 and 12, fig. 11 is a schematic structural diagram based on fig. 9, and fig. 12 is a schematic structural diagram based on fig. 11, and a plasma dry etching process is used to etch and remove the stop layer on the top surface of the protection layer, in the plasma dry etching process, the plasma etches the stop layer in an intermittent manner, so that the etching rate of the plasma on the protection layer is less than the etching rate on the stop layer.
When the stopping layer is etched by the plasma in a discontinuous mode, the energy of the plasma can be reduced in a discontinuous mode, so that the energy of the plasma is between the energy required for removing the stopping layer and the energy required for removing the protective layer, the etching rate of the plasma on the protective layer is lower than the etching rate on the stopping layer, the protective layer which is excessively lost in the process of removing the stopping layer can be avoided, and the top of the grid structure is prevented from being damaged due to the excessive loss of the protective layer.
Specifically, the step of etching the stop layer in an intermittent manner by the plasma comprises: and outputting radio frequency power in a pulse output mode, outputting radio frequency bias in a pulse output mode, and synchronizing the radio frequency power and the pulse of the radio frequency bias so as to etch the stop layer in an intermittent mode. That is, after the etching process continues to output the rf bias and the rf power for a certain time, the output of the rf bias and the rf power is stopped, so that the plasma etches the stop layer in an intermittent manner rather than a continuous manner.
Specifically, fig. 13 is a schematic diagram illustrating a plasma intermittent output mode in a plasma dry etching process, where the abscissa represents the time required from the start of the etching process to the end of the etching process, and the ordinate represents the rf power and the rf voltage. Wherein, the curve 301 is a variation curve of the rf power with time, the curve 302 is a variation curve of the rf bias with time, and the rf power and the rf bias are output in a synchronous pulse manner.
The plasma dry etching process comprises a plurality of pulse periods, and in one pulse period, the etching process comprises an etching period and a stopping period. And continuously outputting the radio frequency bias voltage and the radio frequency power in the etching period to enable the plasma to continuously etch the stop layer, stopping outputting the radio frequency bias voltage and the radio frequency power in the stop period, enabling the plasma to be in a non-excited state and not to etch the stop layer, and simultaneously outputting and turning off the radio frequency bias voltage and the radio frequency power in the whole etching process.
It should be noted that, in the stop period, the output of the rf bias and the rf power is stopped, the plasma is in a non-excited state, and the etching by-products generated by the etching process are discharged in the stop period, so that the accumulation of the etching by-products can be avoided, and the etching efficiency can be improved.
In this embodiment, the process time of the plasma dry etching process is 5s to 30s, and the time of one pulse period is 0.2ms to 0.07 ms.
It should be noted that, in a pulse period, the duty ratio of the rf bias and the rf power output should not be too high or too low. When the duty ratio of the radio frequency bias voltage and the radio frequency power is too high, the time for stopping outputting the radio frequency bias voltage and the radio frequency power is too short, so that etching byproducts are difficult to discharge, and the etching efficiency is reduced; when the duty ratio of the radio frequency bias voltage and the radio frequency power is too low, the etching amount in one etching period is easy to be too small, so that the process time is increased, the production efficiency is reduced, in addition, the time that the plasma is in a non-excited state is too long, and the plasma is difficult to activate when the radio frequency bias voltage and the radio frequency power are output again. For this reason, in this embodiment, the duty ratio of the rf bias or rf power output is 20% to 90% in one pulse period.
In this embodiment, the etching gas used in the plasma dry etching process is NF3And CF4And the diluent gas is Ar.
The etching gas has a fast reaction speed, and when the radio frequency bias voltage and the radio frequency power are output, the plasma can be rapidly converted from a non-excited state to an excited state, so that the etching period can be rapidly started from a stop period, and the etching efficiency is improved.
It should be noted that the flow rate of the etching gas needs to be controlled within a reasonable range. When the etching gas flow is too much, the etching rate is easy to be too fast, so that the stability of the etching process is difficult to control; when the flow of the etching gas is too small, the etching rate is too slow, and accordingly, the etching process time is increased, thereby reducing the production efficiency. For this reason, NF in the present embodiment3The gas flow rate of (1) is 20sccm to 100sccm, CF4The gas flow rate of (1) is 60sccm to 300 sccm.
It should also be noted that the dilution gas is also controlled within a reasonable range according to the flow rate setting of the etching gas. When the flow of the diluent gas is too small, the stability of the etching process is easily reduced, and the dilution effect is not obvious; when the flow of the diluent gas is too high, the etching rate is easily too low, and accordingly, the etching process time is increased, thereby reducing the production efficiency. Therefore, in the present embodiment, the gas flow rate of Ar is 50sccm to 500 sccm. Further, the flow rates of the etching gas and the diluent gas are affected by the pressure, which is set to be 10mTorr to 50mTorr according to the flow rates of the etching gas and the diluent gas.
It should be noted that the etching frequency should not be too high, nor too low. When the etching frequency is too low, the concentration of the plasma is too low, so that the stability of the plasma is poor, and the etching efficiency is easy to reduce; when the etching frequency is too high, the etching rate is too high, and it is difficult to realize a high etching selection ratio of the protective layer and the stop layer. For this reason, in the present embodiment, the etching frequency is 5000HZ to 15000 HZ.
In addition, both the rf bias and the rf power affect the stability of the plasma, and in order to ensure the etching efficiency, in this embodiment, the rf bias is 5V to 35V, and the rf power is 10W to 70W.
Due to the loading effect between the P-type region and the N-type region, the etching rate of the first stop layer 211 (shown in fig. 9) of the P-type region is much greater than that of the second stop layer 221 (shown in fig. 10) of the N-type region. After the first stop layer 211 is etched and removed to expose the first protection layer 212 (as shown in fig. 11), the second stop layer 221 still remains or even has a large residual amount; the plasma also etches the exposed first protective layer 212 during the process of continuing to etch the remaining second stop layer 221 in an intermittent manner until the second protective layer 222 is exposed (as shown in fig. 12). In the process of etching the stop layer by the plasma in an intermittent manner, because the energy of the plasma can be reduced in an intermittent manner, and the energy of the plasma is between the energy required for removing the stop layer and the energy required for removing the protective layer, the etching rate of the protective layer by the plasma is lower than the etching rate of the stop layer, and therefore, the loss of the first protective layer 212 by the etching process for removing the residual second stop layer 221 can be reduced; in addition, the first protection layer 212 is used to protect the first gate structure 210 (as shown in fig. 11), and the problem that the first gate structure 210 is damaged due to excessive loss of the first protection layer 212 can be avoided.
In this embodiment, the etching selection ratio of the plasma dry etching process to the protective layer and the stop layer is 1:1 to 1: 20.
As shown in fig. 14 and 15, fig. 14 and 15 show electron micrographs of the P-type region and the N-type region after removing the first stop layer 211 (shown in fig. 9) and the second stop layer 221 (shown in fig. 10), respectively. As can be seen from the figure, after the first stop layer 211 and the second stop layer 221 are etched by plasma in an intermittent manner, the first stop layer 211 on the top of the first protection layer 212 (shown in fig. 14) is removed, the second stop layer 221 on the top of the second protection layer 222 (shown in fig. 15) is remained, and the first protection layer 212 is still remained on the top of the first gate structure 210 (shown in fig. 14), and the etching process can reduce the loss of the first protection layer 212 caused by the etching process for removing the remaining second stop layer 221.
It should be noted that, after the dielectric layer 230 is formed, the top of the dielectric layer 230 is flush with the top surfaces of the first stop layer 211 (shown in fig. 9) and the second stop layer 221 (shown in fig. 10) and exposes the top surfaces of the first stop layer 211 and the second stop layer 221, so that a natural oxide layer (not shown) is easily formed on the top surfaces of the first stop layer 211 and the second stop layer 221. Specifically, the material of the natural oxidation layer is silicon oxide.
In order to avoid the natural oxide layer becoming a barrier layer in the process of etching the first stop layer 211 and the second stop layer 221, before the first stop layer 211 and the second stop layer 221 are removed by etching using a plasma dry etching process, the forming method further includes: and removing the natural oxide layer on the surfaces of the first stop layer 211 and the second stop layer 221.
The process of removing the natural oxide layer on the surfaces of the first stop layer 211 and the second stop layer 221 may be a wet etching process, and may also be a dry etching process. Specifically, when the natural oxide layers on the surfaces of the first stop layer 211 and the second stop layer 221 are removed by using a wet etching process, an etching solution used by the wet etching process is hydrofluoric acid; when the natural oxide layers on the surfaces of the first stop layer 211 and the second stop layer 221 are removed by adopting a dry etching process, the etching gas of the dry etching process is CF4。
According to the invention, the stop layer is etched by the plasma in a discontinuous mode, and the energy of the plasma can be reduced in a discontinuous mode, so that the energy of the plasma is between the energy required for removing the stop layer and the energy required for removing the protective layer, and the etching rate of the protective layer by the plasma is lower than the etching rate of the stop layer. When the residual stop layer is continuously etched in a part of the area, the loss of the exposed protective layer can be reduced, or the problem of grid structure damage caused by excessive loss of the protective layer can be avoided, so that the electrical performance of the semiconductor device is improved.
In addition, the substrate includes an N-type region and a P-type region, wherein the P-type region is used for forming a P-type device (as shown in fig. 9), the N-type region is used for forming an N-type device (as shown in fig. 10), an etching rate of the first stop layer 211 (as shown in fig. 9) of the P-type region is greater than an etching rate of the second stop layer 221 (as shown in fig. 10) of the N-type region due to a load effect existing between the P-type region and the N-type region, when the first stop layer 211 of the P-type region is removed and the first protection layer 212 (as shown in fig. 11) is exposed, and the second stop layer 221 of the N-type region is continuously etched, an etching rate of the first protection layer 212 to the second stop layer 221 by plasma is smaller than an etching rate of the second stop layer 221 due to the plasma etching of the second stop layer 221 in an intermittent manner, and an etching selection ratio of the first protection layer 212 to the second stop layer 221 can reach 1:1 to 1:20, not only can the second stop layer 221 of the N-type region be removed to reduce the loading effect between the N-type region and the P-type region, but also the loss of the first protection layer 212 of the P-type region can be reduced, or the damage of the first gate structure 210 (as shown in fig. 11) of the P-type region caused by too much loss of the first protection layer 212 can be avoided, thereby improving the electrical performance of the semiconductor device.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a gate structure on the substrate;
forming a protective layer on the top of the gate structure;
forming a stop layer on the side wall of the gate structure and the protective layer;
forming a dielectric layer on the substrate between the grid structures, wherein the dielectric layer is exposed out of the stop layer on the protective layer, and the top of the dielectric layer is flush with the stop layer;
etching and removing all the stop layer on the top surface of the protective layer by adopting a plasma dry etching process, wherein in the plasma dry etching process, the stop layer is etched by the plasma in an intermittent mode, so that the etching rate of the plasma on the protective layer is smaller than that on the stop layer; the plasma dry etching process comprises a plurality of pulse periods, wherein in one pulse period, the pulse period comprises an etching period and a stopping period, in the stopping period, the output of radio frequency bias voltage and radio frequency power is stopped, the plasma is in a non-excited state, and etching byproducts generated by the etching process are discharged in the stopping period, so that the accumulation of the etching byproducts is avoided.
2. The method of forming a semiconductor structure of claim 1, wherein the step of etching the stop layer in an intermittent manner by the plasma comprises: and outputting radio frequency power in a pulse output mode, outputting radio frequency bias in a pulse output mode, and synchronizing the radio frequency power and the pulse of the radio frequency bias so as to etch the stop layer in an intermittent mode.
3. The method of forming a semiconductor structure of claim 2, wherein the plasma dry etch process comprises a plurality of pulse periods;
and within one pulse period, the duty ratio of the radio frequency bias voltage or the radio frequency power is output to be 20-90%.
4. The method of claim 3, wherein the plasma dry etching process has a process time of 5s to 30s and a pulse period time of 0.2ms to 0.07 ms.
5. The method of forming a semiconductor structure of claim 1, wherein the step of the plasma dry etch process comprises: the etching gas is NF3And CF4And the diluent gas is Ar.
6. The method of forming a semiconductor structure of claim 5, wherein in the step of performing a plasma dry etch process, the NF comprises3The gas flow rate of (1) is 20sccm to 100sccm, CF4The gas flow of the gas is 60sccm to 300sccm, the gas flow of Ar is 50sccm to 500sccm, the pressure is 10mTorr to 50mTorr, the etching frequency is 5000HZ to 15000HZ, the radio frequency bias is 5V to 35V, and the radio frequency power is 10W to 70W.
7. The method for forming a semiconductor structure according to claim 2 or 5, wherein an etching selection ratio of the plasma dry etching process to the protective layer and the stop layer is 1:1 to 1: 20.
8. The method of forming a semiconductor structure of claim 1, wherein a material of the protective layer is silicon oxide.
9. The method of forming a semiconductor structure of claim 1, wherein the protective layer has a thickness of 1.8nm to 2.2 nm.
10. The method of claim 1, wherein the stop layer is formed of silicon nitride.
11. The method of claim 1, wherein the stop layer is 0nm to 8.5nm thick after the dielectric layer is formed.
12. The method of forming a semiconductor structure of claim 1, further comprising: and after the dielectric layer is formed, removing the natural oxide layer on the surface of the stop layer before the stop layer on the top surface of the protective layer is removed by adopting a plasma dry etching process.
13. The method of claim 12, wherein the native oxide layer is formed of silicon oxide.
14. The method for forming a semiconductor structure according to claim 13, wherein a process of removing the native oxide layer on the surface of the stop layer is a wet etching process or a dry etching process.
15. The method for forming a semiconductor structure according to claim 14, wherein a wet etching process is used to remove the native oxide layer on the surface of the stop layer, and an etching solution used in the wet etching process is hydrofluoric acid;
or, removing the surface of the stop layer by adopting a dry etching processA natural oxide layer of the surface, wherein the etching gas of the dry etching process is CF4。
16. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises an N-type region and a P-type region;
and in the step of removing the stop layer on the top surface of the protective layer by adopting a plasma dry etching process, the etching rate of the stop layer in the P-type area is greater than that of the stop layer in the N-type area.
17. The method of claim 1, wherein the base comprises a substrate and a fin protruding from the substrate;
the gate structure crosses over the fin and covers a portion of a top surface and a sidewall surface of the fin.
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