CN107255748A - A kind of data signal measurement and generator - Google Patents
A kind of data signal measurement and generator Download PDFInfo
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- CN107255748A CN107255748A CN201710456190.1A CN201710456190A CN107255748A CN 107255748 A CN107255748 A CN 107255748A CN 201710456190 A CN201710456190 A CN 201710456190A CN 107255748 A CN107255748 A CN 107255748A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/28—Provision in measuring instruments for reference values, e.g. standard voltage, standard waveform
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
Abstract
The invention discloses a kind of measurement of data signal and generator, belong to signal measurement and generation technique field, including FPGA circuitry, single-chip microcomputer, signal conditioning circuit, anti-phase ratio discharge circuit and driving buffer circuit, FPGA circuitry includes integrated treatment module, frequency division module, equally accurate frequency measurement module, time interval selecting module, counting module A, counting module B, phaselocked loop, signal generating module and control bit module, and single-chip microcomputer includes LCD MODULE, counts processing module, keystroke handling module, rise time counting module and amplitude processing module.The present invention, which is realized, enters line frequency, dutycycle, time interval, amplitude, the measurement and generation of rise time to periodic rectangular pulse signal, has the advantages that the measured value degrees of accuracy such as frequency, cycle, dutycycle, time interval and rise time under certain amplitude are high.
Description
Technical field
The present invention relates to a kind of measurement of data signal and generator, belong to signal measurement and generation technique field.
Background technology
The very fast development of electronic technology, data signal measurement completes the extension of data signal function with generator, except
Outside the measurement of the baseband signal parameter such as measurement to frequency, dutycycle and time interval, the scope of frequency band becomes wider, and signal is surveyed
The degree of accuracy of amount is improved constantly, while the amplitude to pulse and the measurement of rise time are added, so as to realize signal measurement
With the multifunction of generator, based on simply conventional digit chip, then sophisticated software control is equipped with, in the plate of finite volume
The design of extensive, multi-functional electronic product is completed on son becomes increasingly simpler, by being updated on software and perfect,
Data signal measure with generator precision and function phase should expand it is more.
The content of the invention
The main object of the present invention is to provide for a kind of data signal measurement and generator, for solving pulse signal width
The problem of spending too high or too low and its not high Rise time measurement accuracy, realization enters line frequency to periodic rectangular pulse signal
Rate, dutycycle, time interval, amplitude, the measurement and generation of rise time.
The purpose of the present invention can reach by using following technical scheme：
A kind of data signal measurement and generator, including FPGA circuitry, single-chip microcomputer, signal conditioning circuit, anti-phase ratio fortune
Discharge road and driving buffer circuit, the input input signal A and signal B of the signal conditioning circuit, the signal condition electricity
The output end on road is electrically connected with the FPGA circuitry, the single-chip microcomputer, the anti-phase ratio discharge circuit respectively, the anti-phase ratio
The output end and the monolithic mechatronics of example discharge circuit, the single-chip microcomputer are adjusted with the FPGA circuitry and the signal respectively
Circuit electrical connection is managed, the FPGA circuitry is electrically connected with the driving buffer circuit, and the output end of the driving buffer circuit is entered
Row signal output, the single-chip microcomputer is also electrically connected with liquid crystal display and keyboard respectively, and the FPGA circuitry has been used for paired frequency, accounted for
Sky ratio, the measurement of time interval and signal occur, and the FPGA circuitry is additionally operable to control the measurement accuracy of data signal measurement,
The single-chip microcomputer is used for processing data and sends the measured value of data to the liquid crystal display, and the liquid crystal display is used to show number
According to measured value.
It is preferred that scheme be, the FPGA circuitry include integrated treatment module, frequency division module, equally accurate frequency measurement module, when
Between interval selecting module, counting module A, counting module B, phaselocked loop, signal generating module and control bit module, the General Office
Manage module respectively with the equally accurate frequency measurement module, the counting module A, the counting module B and the signal generating module
Electrical connection.
In any of the above-described scheme preferably, the output end of the frequency division module is defeated with the equally accurate frequency measurement module
Enter end electrical connection, the input input signal A of the equally accurate frequency measurement module, the input of the time interval selecting module is defeated
Enter signal A and signal B, the phaselocked loop is electrically connected with the counting module A and the counting module B respectively, the control bit
The output end of module is electrically connected with the signal generating module.
In any of the above-described scheme preferably, the output end of the time interval selecting module respectively with the count module
Block A and counting module B electrical connections, the time interval selecting module is used to carry out signal to the signal A and signal B of input
Selection, the counting module A and the counting module B are used for signal A and signal B processing to input, measure signal A
With the time between signal B.
In any of the above-described scheme preferably, the single-chip microcomputer is MSP430 single-chip microcomputers, the FPGA circuitry and described
Single-chip microcomputer is used for count measurement, duty ratio measuring and signal by described 8 data of control bit module transfer, the FPGA circuitry
Occur.
In any of the above-described scheme preferably, the driving buffer circuit includes 74HC573 chips and filter capacitor；Account for
The measurement of empty ratio is to measure high level and low level number in feeding signal a cycle respectively by the FPGA circuitry,
And send into the MSP430 single-chip microcomputers progress dutycycle calculating；The integrated treatment module is used for data storage, and to feeding
Square-wave signal, which is measured, obtains high accuracy data, the integrated treatment module be additionally operable to realize with the MSP430 single-chip microcomputers it
Between communication, signal receive and data transfer selection.
In any of the above-described scheme preferably, the signal of FPGA circuitry output through 74HC573 chips described in two panels,
The filter circuit and boost resistor, 5V, two panels institute are converted to for making the output maximum voltage of the FPGA circuitry by 3.3V
74HC573 chip cascades are stated, for driving buffering to make system output voltage stable.
In any of the above-described scheme preferably, the single-chip microcomputer includes LCD MODULE, counts processing module, button
Processing module, rise time counting module and amplitude processing module, the LCD MODULE are electrically connected with the liquid crystal display, institute
Keystroke handling module is stated to electrically connect with the keyboard, it is described counting processing module respectively with the counting module A and the counting
Module B is electrically connected.
In any of the above-described scheme preferably, the signal conditioning circuit include two comparator LM339, relay K1,
Relay K2 and relay K3, inputs of the comparator LM339 respectively with the single-chip microcomputer is electrically connected described in two, the single-chip microcomputer
Output end electrically connected respectively with the relay K1, the relay K2 and the relay K3；The relay K1's is defeated
Go out end to electrically connect with an OP07 transport and placing device, the OP07 transport and placing devices are electrically connected with the relay K2；The relay K2
Output end electrically connected with another OP07 transport and placing device, the OP07 transport and placing devices are electrically connected with the relay K3；It is described after
Electrical equipment K3 output end is electrically connected with another OP07 transport and placing devices, and the OP07 transport and placing devices are electrically connected with the relay K1；Institute
Input of relay K1, the relay K2 and the relay K3 output end with the single-chip microcomputer is stated to electrically connect.
In any of the above-described scheme preferably, the input and output end of the anti-phase ratio discharge circuit are connected to electricity
Resistance, the anti-phase ratio discharge circuit includes OP07 transport and placing devices；The OP07 transport and placing devices are connected after tested voltage signal, voltage amplitude
Spend amplification 5 times of the scope in 0.1V~0.4V；The OP07 transport and placing devices are connected after tested voltage signal, and voltage amplitude scope exists
0.4V~2.5V's is constant；The OP07 transport and placing devices are connected after tested voltage signal, contracting of the voltage amplitude scope in 2.5V~10V
It is small 5 times.
The advantageous effects of the present invention：Data signal measurement and generator according to the present invention, the number that the present invention is provided
Word signal measurement and generator, solve that pulse amplitude in the prior art is too high or too low and its Rise time measurement essence
The problem of exactness is not high, can realize and enter line frequency, dutycycle, time interval, amplitude, rising to periodic rectangular pulse signal
The measurement and generation of time, with the frequency under certain amplitude, cycle, dutycycle, time interval and rise time etc.
The high advantage of the measured value degree of accuracy, solves that pulse amplitude is too high or too low and its Rise time measurement accuracy is not high
The problem of.
Brief description of the drawings
Fig. 1 is the data signal measurement and the system structure diagram of a preferred embodiment of generator according to the present invention；
Fig. 2 is the data signal measurement and the FPGA circuitry structure chart of a preferred embodiment of generator according to the present invention,
The embodiment can be and Fig. 1 identicals embodiment or the embodiment different with Fig. 1；
Fig. 3 is the data signal measurement and the signal conditioning circuit circuit of a preferred embodiment of generator according to the present invention
Scheme, the embodiment can be and Fig. 1 or Fig. 2 identicals embodiment or the embodiment different with Fig. 1 or Fig. 2；
Fig. 4 is the data signal measurement according to the present invention and the signal conditioning circuit electricity of another preferred embodiment of generator
Lu Tu, the embodiment can be and Fig. 1 or Fig. 2 or Fig. 3 identicals embodiment or different with Fig. 1 or Fig. 2 or Fig. 3
Embodiment；
Fig. 5 is the data signal measurement and the anti-phase ratio discharge circuit of a preferred embodiment of generator according to the present invention
Circuit diagram, the embodiment can be with Fig. 1 or Fig. 2 or Fig. 3 or Fig. 4 identicals embodiment or with Fig. 1 or Fig. 2 or Fig. 3
Or the different embodiments of Fig. 4；
Fig. 6 is the data signal measurement and the driving buffer circuit circuit of a preferred embodiment of generator according to the present invention
Figure, the embodiment can be with Fig. 1 or Fig. 2 or Fig. 3 or Fig. 4 or Fig. 5 identicals embodiment or with Fig. 1 or Fig. 2 or figure
Embodiments different 3 or Fig. 4 or Fig. 5.
In figure：1-FPGA circuits, 2- single-chip microcomputers, 3- signal conditioning circuits, the anti-phase ratio discharge circuits of 4-, 5- driving bufferings
Circuit, 6- liquid crystal displays, 7- keyboards, 11- integrated treatment modules, 12- frequency division modules, 13- equally accurate frequency measurement modules, between the 14- times
Every selecting module, 15- counting modules A, 16- counting module B, 17- phaselocked loop, 18- signal generating modules, 19- control bit modules.
Embodiment
To make those skilled in the art's more clear and clear and definite technical scheme, with reference to embodiment and accompanying drawing
The present invention is described in further detail, but the implementation of the present invention is not limited to this.
As shown in Figure 1, Figure 2, shown in Fig. 3, Fig. 4, Fig. 5 and Fig. 6, a kind of data signal measurement that the present embodiment is provided is with occurring
Instrument, it is characterised in that：Including FPGA circuitry 1, single-chip microcomputer 2, signal conditioning circuit 3, anti-phase ratio discharge circuit 4 and driving buffering
Circuit 5, the input input signal A and signal B of the signal conditioning circuit 3, the output end difference of the signal conditioning circuit 3
Electrically connected with the FPGA circuitry 1, the single-chip microcomputer 2, the anti-phase ratio discharge circuit 4, the anti-phase ratio discharge circuit 4
Output end electrically connected with the single-chip microcomputer 2, the single-chip microcomputer 2 respectively with the FPGA circuitry 1 and the signal conditioning circuit 3
Electrical connection, the FPGA circuitry 1 is electrically connected with the driving buffer circuit 5, and the output end of the driving buffer circuit 5 is believed
Number output, the single-chip microcomputer 2 also electrically connects with liquid crystal display 6 and keyboard 7 respectively, and the FPGA circuitry 1 has been used for paired frequency, accounted for
Sky ratio, the measurement of time interval and signal occur, and the FPGA circuitry 1 is additionally operable to control the measurement essence of data signal measurement
Degree, the single-chip microcomputer 2 is used for processing data and sends the measured value of data to the liquid crystal display 6, and the liquid crystal display 6 is used for
The measured value of display data.
Further, in the present embodiment, as depicted in figs. 1 and 2, the FPGA circuitry 1 include integrated treatment module 11,
Frequency division module 12, equally accurate frequency measurement module 13, time interval selecting module 14, counting module A15, counting module B16, phaselocked loop
17th, signal generating module 18 and control bit module 19, the integrated treatment module 11 respectively with the equally accurate frequency measurement module 13,
The counting module A15, the counting module B16 and the signal generating module 18 are electrically connected, the frequency division module 12 it is defeated
Go out end to electrically connect with the input of the equally accurate frequency measurement module 13, the input input signal of the equally accurate frequency measurement module 13
A, the input input signal A and signal B of the time interval selecting module 14, the phaselocked loop 17 respectively with the count module
Block A15 and counting module B16 electrical connections, the output end of the control bit module 19 is electrically connected with the signal generating module 18
Connect.
Further, in the present embodiment, as depicted in figs. 1 and 2, the output end of the time interval selecting module 14 point
Do not electrically connected with the counting module A15 and the counting module B16, the time interval selecting module 14 is used for input
Signal A and signal B carry out signal behavior, the counting module A15 and the counting module B16 be used for the signal A of input and
Signal B processing, measures the time between signal A and signal B.
Further, in the present embodiment, as shown in Figure 1, Figure 2 with shown in Fig. 6, the single-chip microcomputer 2 is MSP430 single-chip microcomputers, institute
State FPGA circuitry 1 and the single-chip microcomputer 2 and 8 data are transmitted by the control bit module 19, the FPGA circuitry 1 is used to count
Measurement, duty ratio measuring and signal occur, and the driving buffer circuit 5 includes 74HC573 chips and filter capacitor；Dutycycle
Measurement is to measure high level and low level number in feeding signal a cycle respectively by the FPGA circuitry 1, and is sent
Enter the MSP430 single-chip microcomputers and carry out dutycycle calculating；The integrated treatment module 11 is used for data storage, and to the side of feeding
Ripple signal, which is measured, obtains high accuracy data, the integrated treatment module 11 be additionally operable to realize with the MSP430 single-chip microcomputers it
Between communication, signal receive and data transfer selection, the signal that the FPGA circuitry 1 is exported is through 74HC573 chips, institute described in two panels
Filter circuit and boost resistor are stated, 5V is converted to for making the output maximum voltage of the FPGA circuitry 1 by 3.3V, described in two panels
74HC573 chip cascades, for driving buffering to make system output voltage stable.
Further, in the present embodiment, as depicted in figs. 1 and 2, the single-chip microcomputer 2 includes LCD MODULE, counted
Processing module, keystroke handling module, rise time counting module and amplitude processing module, the LCD MODULE and the liquid
Crystalline substance screen 6 is electrically connected, and the keystroke handling module is electrically connected with the keyboard 7, and the counting processing module is counted with described respectively
Modules A 15 and counting module B16 electrical connections.
Further, in the present embodiment, as shown in Figure 3 and Figure 4, the signal conditioning circuit 3 includes two comparators
LM339, relay K1, relay K2 and relay K3, the inputs of comparator LM339 described in two respectively with the single-chip microcomputer 2
Electrical connection, the output end of the single-chip microcomputer 2 is electrically connected with the relay K1, the relay K2 and the relay K3 respectively
Connect；The output end of the relay K1 is electrically connected with an OP07 transport and placing device, the OP07 transport and placing devices and the relay K2
Electrical connection；The output end of the relay K2 is electrically connected with another OP07 transport and placing device, the OP07 transport and placing devices with it is described after
Electrical equipment K3 is electrically connected；The output end of the relay K3 is electrically connected with another OP07 transport and placing devices, the OP07 transport and placing devices and institute
State relay K1 electrical connections；The relay K1, the relay K2 and the relay K3 output end with the monolithic
The input electrical connection of machine 2.
Further, in the present embodiment, as shown in Figure 4 and Figure 5, the input of the anti-phase ratio discharge circuit 4 and
Output end is connected to resistance, and the anti-phase ratio discharge circuit 4 includes OP07 transport and placing devices；The OP07 transport and placing devices connect tested electricity
Press after signal, amplification 5 times of the voltage amplitude scope in 0.1V~0.4V；The OP07 transport and placing devices are connected after tested voltage signal,
Voltage amplitude scope is in the constant of 0.4V~2.5V；The OP07 transport and placing devices are connected after tested voltage signal, voltage amplitude scope
In 2.5V~10V 5 times of diminution.
Further, in the present embodiment, frequency division module carries out phase locking frequency multiplying by the crystal oscillator to 50MHz and frequency dividing is distinguished
200MHz and 1MHz clock are obtained, is that the clock required for following frequency measurement etc. is ready, equally accurate frequency measurement module passes through
The square-wave signal of feeding is measured and obtains high accuracy data, time interval selecting module to the A of feeding, B signal at
Reason, measures the interval data between them, and duty ratio measuring is measured respectively by FPGA in feeding signal a cycle
The number of low and high level, feeding single-chip microcomputer carries out calculating dutycycle, and signal generating module is used to produce 50% dutycycle and frequency
Rate value stores above three measuring circuits and the data of signal generating circuit in 1MHz pulse signals, integrated treatment module, together
When be used for and single-chip microcomputer complete communication, receive single-chip microcomputer control signal, selection single-chip microcomputer need data transfer.
Further, in the present embodiment, reference voltage is set to be respectively 0.4V and 2.5V to input voltage width LM339
Degree classification, sorted signal, the signal that the signal that 0.1V~0.4V is received receives for 00,0.4V~2.5V are received by single-chip microcomputer
It is that the signal that 01,2.5V~10V is received is 10, single-chip microcomputer receives and accordingly export to 3 relays K1, K2, K3 with 001,
010th, 100 signal control relays switch thus voltage range is identified, three relays export into voltage signal warp
The discharge circuit being made up of OP07, receives 001 signal Vi1, connects tested voltage signal amplitude scope in 0.1V~0.4V electricity
Press big 5 times, receive 010 signal Vi2, it is constant in 0.4V~2.5V voltages to connect tested voltage signal amplitude scope, receives
100 signal Vi3, connect tested voltage signal amplitude scope and reduce 5 times in 2.5V~10V voltages, output voltage sends monolithic back to
Machine handles and accurately shows surveyed data.Because single-chip microcomputer can not receive the voltage more than more than 5V in measuring circuit, more than 5V
Voltage need decompression handle after feeding single-chip microcomputer in analyzing and processing and by liquid crystal display.
Further, in the present embodiment, measured by anti-phase ratio discharge circuit it is the 10% of signal amplitude to rise to
Time required for 90%, voltage, by R1/R2 times that voltage obtained by OP07 inverting amplifiers U1 is input voltage, is 10%
Input voltage, it is the 90% of input voltage that similarly R3/R4, which obtains voltage through voltage obtained by OP07 inverting amplifiers U2, is passed through through single-chip microcomputer
The rise time is drawn after XOR analysis.
Further, in the present embodiment, divide by FPGA to the counting of reference pulse number and to internal 50M crystal oscillators
Frequency can realize the generation of 50% dutycycle and frequency values in 1MHz pulse signals.What the signal of FPGA outputs was cascaded through two panels
74HC573 chips and electric source filter circuit and boost resistor so that the signal output maximum voltage of generator can be with by 3.3V
5V is converted into, so as to meet the requirement that output amplitude is 5V.
Further, in the present embodiment, FPGA transmits 8 data with MSP430 single-chip microcomputers by control bit, and FPGA is born
Count measurement is blamed, MSP430 is responsible for processing data and shows corresponding measured value.Measured signal is by signal conditioning circuit point
It Shu Ru not analyzed in FPGA and MSP430, when measurement signal is the rise time, needs first through signal condition, transport again by inverted ratio
Electric discharge road.Signal occurs after FPGA outputs, by driving buffer circuit output is corresponding to occur signal.
In summary, in the present embodiment, the data signal measurement according to the present embodiment and generator, the present embodiment are provided
Data signal measurement and generator, solve that pulse amplitude in the prior art is too high or too low and its rise time surveys
Measure accuracy it is not high the problem of, can realize periodic rectangular pulse signal is entered line frequency, dutycycle, time interval, amplitude,
The measurement and generation of rise time, during with the frequency under certain amplitude, cycle, dutycycle, time interval and rising
Between wait the high advantage of the measured value degree of accuracy, solve that pulse amplitude is too high or too low and its Rise time measurement accuracy
Not high the problem of.
It is described above, it is only further embodiment of the present invention, but protection scope of the present invention is not limited thereto, and it is any
Those familiar with the art is in scope disclosed in this invention, and technique according to the invention scheme and its design add
With equivalent substitution or change, protection scope of the present invention is belonged to.
Claims (10)
1. a kind of data signal measurement and generator, it is characterised in that：Including FPGA circuitry (1), single-chip microcomputer (2), signal condition
Circuit (3), anti-phase ratio discharge circuit (4) and driving buffer circuit (5), the input input of the signal conditioning circuit (3)
Signal A and signal B, the output end of the signal conditioning circuit (3) respectively with the FPGA circuitry (1), the single-chip microcomputer (2),
Anti-phase ratio discharge circuit (4) electrical connection, output end and the single-chip microcomputer (2) of the anti-phase ratio discharge circuit (4)
Electrical connection, the single-chip microcomputer (2) electrically connects with the FPGA circuitry (1) and the signal conditioning circuit (3) respectively, the FPGA
Circuit (1) is electrically connected with the driving buffer circuit (5), and the output end of the driving buffer circuit (5) carries out signal output, institute
State single-chip microcomputer (2) also to electrically connect with liquid crystal display (6) and keyboard (7) respectively, the FPGA circuitry (1) has been used for paired frequency, accounted for
Sky ratio, the measurement of time interval and signal occur, and the FPGA circuitry (1) is additionally operable to control the measurement essence of data signal measurement
Degree, the single-chip microcomputer (2) is used for processing data and sends the measured value of data to the liquid crystal display (6), the liquid crystal display
(6) it is used for the measured value of display data.
2. a kind of data signal measurement according to claim 1 and generator, it is characterised in that：The FPGA circuitry (1)
Including integrated treatment module (11), frequency division module (12), equally accurate frequency measurement module (13), time interval selecting module (14), meter
Number modules A (15), counting module B (16), phaselocked loop (17), signal generating module (18) and control bit module (19), it is described comprehensive
Close processing module (11) respectively with the equally accurate frequency measurement module (13), the counting module A (15), the counting module B
(16) electrically connected with the signal generating module (18).
3. a kind of data signal measurement according to claim 2 and generator, it is characterised in that：The frequency division module (12)
Output end electrically connected with the input of the equally accurate frequency measurement module (13), the input of the equally accurate frequency measurement module (13)
Input signal A, the input input signal A and signal B of the time interval selecting module (14), the phaselocked loop (17) is respectively
Electrically connected with the counting module A (15) and the counting module B (16), the output end of the control bit module (19) with it is described
Signal generating module (18) is electrically connected.
4. a kind of data signal measurement according to claim 3 and generator, it is characterised in that：The time interval selection
The output end of module (14) is electrically connected with the counting module A (15) and the counting module B (16) respectively, the time interval
Selecting module (14) is used to carry out the signal A and signal B of input signal behavior, the counting module A (15) and the counting
Module B (16) is used for signal A and signal B processing to input, measures the time between signal A and signal B.
5. a kind of data signal measurement according to claim 2 and generator, it is characterised in that：The single-chip microcomputer (2) is
MSP430 single-chip microcomputers, the FPGA circuitry (1) and the single-chip microcomputer (2) transmit 8 data by the control bit module (19),
The FPGA circuitry (1), which is used for count measurement, duty ratio measuring and signal, to be occurred.
6. a kind of data signal measurement according to claim 5 and generator, it is characterised in that：The driving buffer circuit
(5) 74HC573 chips and filter capacitor are included；The measurement of dutycycle is to measure feeding respectively by the FPGA circuitry (1)
High level and low level number in signal a cycle, and send into the MSP430 single-chip microcomputers progress dutycycle calculating；It is described
Integrated treatment module (11) is used for data storage, and the square-wave signal of feeding is measured obtains high accuracy data, described comprehensive
Conjunction processing module (11) is additionally operable to realize with being communicated between the MSP430 single-chip microcomputers, signal is received and data transfer selection.
7. a kind of data signal measurement according to claim 6 and generator, it is characterised in that：The FPGA circuitry (1)
The signal of output is through 74HC573 chips, the filter circuit and boost resistor described in two panels, for making the FPGA circuitry (1)
Output maximum voltage 5V is converted to by 3.3V, 74HC573 chip cascades described in two panels, for drive buffering make system output electricity
Pressure is stable.
8. a kind of data signal measurement according to claim 2 and generator, it is characterised in that：Single-chip microcomputer (2) bag
Include LCD MODULE, count processing module, keystroke handling module, rise time counting module and amplitude processing module, it is described
LCD MODULE is electrically connected with the liquid crystal display (6), and the keystroke handling module is electrically connected with the keyboard (7), the meter
Number processing module is electrically connected with the counting module A (15) and the counting module B (16) respectively.
9. a kind of data signal measurement according to claim 1 and generator, it is characterised in that：The signal conditioning circuit
(3) include two comparator LM339, relay K1, relay K2 and relay K3, comparator LM339 described in two respectively with it is described
The input electrical connection of single-chip microcomputer (2), the output end of the single-chip microcomputer (2) respectively with the relay K1, the relay K2
With relay K3 electrical connections；The output end of the relay K1 is electrically connected with an OP07 transport and placing device, the OP07 fortune
Device is put to electrically connect with the relay K2；The output end of the relay K2 is electrically connected with another OP07 transport and placing device, and this is described
OP07 transport and placing devices are electrically connected with the relay K3；The output end of the relay K3 is electrically connected with another OP07 transport and placing devices, should
The OP07 transport and placing devices are electrically connected with the relay K1；The relay K1, the relay K2 and the relay K3's
Input of the output end with the single-chip microcomputer (2) is electrically connected.
10. a kind of data signal measurement according to claim 1 and generator, it is characterised in that：The anti-phase ratio fortune
The input and output end of electric discharge road (4) are connected to resistance, and the anti-phase ratio discharge circuit (4) includes OP07 transport and placing devices；Institute
State OP07 transport and placing devices to connect after tested voltage signal, amplification 5 times of the voltage amplitude scope in 0.1V~0.4V；The OP07 amplifiers
Device is connected after tested voltage signal, and voltage amplitude scope is in the constant of 0.4V~2.5V；The OP07 transport and placing devices connect tested electricity
Press after signal, diminution 5 times of the voltage amplitude scope in 2.5V~10V.
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| CN201710456190.1A CN107255748A (en) | 2017-06-16 | 2017-06-16 | A kind of data signal measurement and generator |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108761316A (en) * | 2018-07-24 | 2018-11-06 | 江苏理工学院 | Amplitude versus frequency characte tester and amplitude versus frequency characte test system |
| CN109283390A (en) * | 2018-10-10 | 2019-01-29 | 江苏理工学院 | A kind of spectrum analyzer of intelligence automatic growth control |
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| CN104460462A (en) * | 2014-12-13 | 2015-03-25 | 华北电力大学 | Sampling circuit compatible with unipolar and bipolar analog signals |
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| CN109283390A (en) * | 2018-10-10 | 2019-01-29 | 江苏理工学院 | A kind of spectrum analyzer of intelligence automatic growth control |
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